JPS61290545A - Automatic output device for vertification use data - Google Patents

Abstract

PURPOSE:To execute automatically the decision and the work of the verification of a normal operation of the logic by executing the comparison of a designated file data with the data of the same file saved already, and extracting only a data having the dissidence of the data contents. CONSTITUTION:A verification data comparing mechanism 2 extracts from a signal 82 all the data of the designated area range of a data file to be compared 8 registered in a verification data output designating register 5 from a signal line 52. Next, a coincidence check to a data saved already in a comparing data saving buffer 6 is executed. As for a data whose dissidence is detected, a data which becomes an object to be an output data buffer 7 and the saving buffer 6 from a signal 27 and a data of the same item in a file 8 are recorded. In-file relative address information of a data in which dissidence to a code of the file 8 is detected, and the dissidence detection time are added and recorded to an output buffer 7 from the signal 27.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention is an automatic data output device for eliminating human errors in logic verification work during the software production process of a computer system.

[Background of the invention]

As a device for logic verification, for example,
As shown in Publication No. 3216, assuming there is a bug, there is a mechanism that determines a logic error if the boyfriend comparison address is included within the specified area (address). Are known.

This method assumes that the logic operates correctly, and recognizes data changes within the range specified by multiple coded areas (multiple areas can be specified for each data file), rather than by direct address specification. This is the way to do it.

,Also, as a program logic verification laboratory, we have traditionally assumed the normal operation of the program.

Intermediate data or final data of the processing results are written in the test plan for verification, and the result data is artificially output at the verifier's discretion during verification.

The method used was to compare the output results with the expected results of the test plan, which often resulted in human verification errors, so there was a need for automation.

[Purpose of the invention]

An object of the present invention is to provide an automatic data output device that automates the judgment and work of verifying the normal operation of logic.

゛ [Summary of the Invention] - The present invention provides the following features:
It functions after data is saved to the specified file information save area, and after each event occurs or after a certain period of time immediately after a schedule point, assuming the lower program group ends its operation, the specified file data and the specified file data are already saved. Comparisons are made with data from the same file, and only data with inconsistent data content is extracted and output together with additional information such as detection time.

Also, the latest data is moved to the save area.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to a block diagram of an automatic program verification data output device shown in the figure.

Reference numeral 1 denotes an input mechanism for verification data output designation information, which is a general input device that takes in the verification data output designation information input from the input signal 10, and inputs data in a designated area range of the designated compared data file 8. After the comparison data is saved in the save buffer 6, the information items inputted from the output signal 10 are registered in the verification data output designation register 5.

Reference numeral 2 denotes a verification data comparison mechanism, and a comparison request is made by a signal 42 from a comparison request delay mechanism built into the application program 4. The verification data comparison mechanism 2 extracts from the signal 82 all the data in the designated area range of the compared data file 8 registered in the verification data output designation register 5 from the signal 82, and extracts the data that has already been saved to the comparison data save buffer 6. A match check is performed with the data in
7 to output data buffer 7. The data to be compared in the comparison data save buffer 6 and the data of the same item in the compared data file 8 are recorded, and the in-file relative address information of the data for which a mismatch with the code of the compared data file 8 is detected. , and a signal 27 indicating the mismatch detection time.
Therefore, additional recording is performed in the output buffer 7. After this, only the mismatched data of the compared data file 8 where mismatch was detected.

When the signal 26 indicates that six or more processes for updating the data in the comparison data save buffer 6 have been completed for all data extracted from the signal 82, if at least - pieces of mismatched data are detected, the signal 23 is detected. The verification data output mechanism 3 requests the verification data output mechanism 3 to output mismatched data, and when an output request is generated from the signal 23, the output data buffer 7 outputs registered output target information from the signal 27. The comparison request delay mechanism 4, which extracts data from 73 and outputs it to an arbitrary output medium, is built into the supervisor function of the application program group, and triggers an event to lower-level application programs and from the time when a scheduling point occurs. , after a period of time that allows it to be considered that the operations of the lower-level application programs have ended, a signal 42 is used to initiate a comparison request to the verification data comparison mechanism 2.

Based on the verification data output results, a verification plan has been written in advance to verify the operation of any application program. The thick validity of the program to be verified is checked by comparing the intermediate or final output data of the program operation results with the verification data output value.

Moreover, by specifying a plurality of files at the same time as the data files to be compared, it becomes an effective means for discovering defects such as data corruption in files other than the predetermined files due to program logic defects to be verified.

〔Effect of the invention〕

According to the present invention, in program verification work, mistakes in specifying an output area when outputting verification data after program operation, mistakes in creating a verification method due to mistakes in assuming program operations, etc.
Further, it is possible to early discover the details of a problem related to a program logic failure.

[Brief explanation of the drawing]

The figure is a block diagram of one embodiment of the present invention. 1... Verification data output designation input mechanism, 2... Verification data comparison mechanism, 3... Verification data output mechanism, 4...
Comparison request delay mechanism, 5... Verification data output designation register, 6... Comparison data save buffer, 7... Output buffer, 8... Compared data file.

Claims (1)

[Claims] 1. At the stage of producing software for a computer system that has an event-driven or scheduling processing structure, it is necessary to check the operation target during the operation verification test of each function, after the occurrence of each event, or immediately after the schedule point. Information files accessed by the program
A means for specifying and registering a code, detecting a data change in the information file specified before and after the occurrence of each event or before and after the schedule point,
A means for automatically outputting code, file addresses, and data changes along with detection times, and essential information for verifying the consistency of the expected operation contents of each program as output information of program operation results. 1. An automatic verification data output device comprising a means for automatically reporting data.