JPS61288475A - Manufacture of photo detector - Google Patents

Abstract

PURPOSE:To enable to remove promptly the slow component due to the diffusion of positive holes, by taking out electron current and positive hole current into an external circuit with these currents being separated. CONSTITUTION:On the surface of a semi-insulating InP substrate 21, SiO2mask 32 is deposited by a CVD method or the like, and a stripe-shaped opening with a width of about 2mum is formed by a normal photo lithography technique to expose the InP substrate 21. Next, etching forms a stripe-shaped trench with a depth of about 0.3mum and a width of about 2mum. Next, molecular beam epitaxy causes a P-type InGaAs hole current absorbing layer 22 to grow. Next, etching forms P-type InGaAs only in the trench. Thereafter, molecular beam epitaxy laminates an N-type InGaAs light-absorbing layer 23, an undoped Al InAs two-dimensional electron gas forming spacer layer 24, an N-type A4l InAs charge supplying layer 25 and an N-type InGaAs electrode forming layer 26. In the electrode forming process, the surfaces of the hole current absorbing layer 22 and the semi-insulating InP substrate 21 are exposed, and the charge supplying layer 25 is also exposed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a photodetector used in optical communication devices and the like.

(Prior art and its problems) Modulation doped photodetector (MD
A photodetector (abbreviated as PD) is a photodetector with high-speed response characteristics, and is a semiconductor device having a meridian junction. Examples of conventionally reported MDPD include Applied Fixtures Letters (Appl, Phys, L@tt,
43 (1983) 308)
The structure is shown in FIG. 6 in cross section. This MDPD structure is
Undoped AJ nAs on the semi-insulating InP substrate 11
A buffer layer 12, an undoped (n-type) nGaAs light absorption layer 13, an undoped AJ-nAs spacer layer 14 for forming a two-dimensional electron gas, and an n-type AI nAs
It has a charge supply layer 15 and an n-type nGaAs electrode formation layer 16 for electrode formation. The source electrode 17 and the drain electrode 18 are gold-germanium (AuGe) alloy electrodes, and the alloy extends deep into the two-dimensional electron gas region as shown by the broken line.

In this structure, among the electron-hole pairs excited by the incident photons, the electrons are connected to the InGaAs layer 13 and the AlInA layer 13.
Two-dimensional electron gas (created on the InGaAs layer 13 side at the interface between 13 and 14) due to the internal electric field created at the interface of the g layer 14
It can be extracted to the outside as a current flowing in response to the voltage applied between the source and drain. Since this device has extremely high electron mobility in the two-dimensional electron gas region, it is expected to respond quickly, and in fact, the signal rise time is extremely short in the aforementioned paper. However, experimental data shows that the fall time is very long. The reason for such a long fall time is that the holes generated by photoexcitation move to the depths of the light absorption layer 13, that is, in the opposite direction to the two-dimensional electron gas region, and recombine with electrons over a relatively long period of time. It is known that the cause is that the current reaches the electrodes as a diffusion current component without being absorbed.

Therefore, in order to obtain high-speed response characteristics in MDPD, it is necessary to create a device structure in which slow current components due to holes can be detected or ignored as much as possible.

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a method for manufacturing an MDPD that responds quickly to both the rise and fall of a signal current.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the method for manufacturing a photodetector provided by the present invention includes forming a p-type first semiconductor region on a part of the surface of a semi-insulating substrate. a p-type region forming step, and at least an n-type second semiconductor layer on the substrate and an n-type semiconductor layer for two-dimensional electron gas generation having a larger pand gap than the second semiconductor layer.
an epitaxial growth step of sequentially stacking a third semiconductor layer of the same type and an n-type electrode formation layer with a small pad/de gap; and a position on the electrode formation layer sandwiching the first semiconductor region. The first and second electrodes are arranged up to the region where the two-dimensional electron gas is formed, and the third electrode is arranged in the region located between the first and second electrodes on the surface of the third semiconductor layer. The method is characterized by comprising an electrode forming step of forming an electrode and a fourth electrode in the first semiconductor region, respectively.

(Summary of the Invention) Next, an MDPD manufactured according to the present invention will be explained with reference to the drawings. FIG. 4 is a perspective view of a novel MDPD manufactured according to the first to third embodiments of the present invention, which will be described later. In this MDPD, a hole current sucking layer (the first semiconductor Area) 22 is depth ~0.3μ
m1 width is formed in the range of ~2 μm, and further thereon, an n-type 1nGa film 8 (N~3 x 10"cx-", thickness ~1.5 μm) light absorption layer (second semiconductor layer) 23, Undoped An Aa (thickness ~ 100 people) 2-dimensional electron gas formation spacer layer (third semiconductor layer) 24, n-type AI NA
s (N ~ 5X 10I?cIL-", thickness ~ 1000 people) Charge supply layer (third semiconductor layer) 25, n-type nGaAs
(I x 10"(m"", thickness ~ 150 people)) has an electrode formation layer 26. Also, as an electrode, a source electrode (
The first electrode) 28 and the drain electrode (second electrode) 27 are made of gold and germanium, the gate electrode (third electrode) 29 is made of titanium/gold, and the hole current extraction electrode (fourth electrode) 30 is made of zinc. Each is formed separately. In this MDPD, there is a flat area in which the surfaces of the semi-insulating InP substrate 21 and the p-type 1nGaAs hole current extraction layer 22 are exposed, and the hole current extraction electrode 3o is formed in this area.

In FIG. 5, in the plane shown by the broken line 31 in FIG.
A cross-sectional view of the DPD is shown. In this device, when light is incident, electron-hole pairs are generated in the light absorption layer (second semiconductor layer) 23. Among these, the electrons reach the two-dimensional electron gas region within a short time due to the internal electric field generated near the two-dimensional electron gas region, so that they can be taken out as a signal current between the source and drain. In a two-dimensional electron gas, electrons are less likely to be scattered and have a higher mobility than a normal single-layer semiconductor, so the transit time of electrons between electrodes is short and the response is fast. On the other hand, holes move in the opposite direction to electrons, but in a structure in which a hole sucking layer (first semiconductor region) 22 is provided as in the present invention,
With the electrodes 29 and 30 biased in the opposite direction, it is possible to extract the hole current to the electrode 30 as a hole current.

As mentioned above, in this MDPD, by separating the electron current and hole current and outputting them to an external circuit, it is possible to quickly remove the slow component due to hole diffusion, which has been a problem in the past. is now possible.

(Example) According to the manufacturing method of the present invention, a novel MDPD having the excellent properties as described above can be obtained.

Embodiments of the present invention will be described in detail below with reference to the drawings. FIGS. 1(a) to 1(f) are diagrams showing the main steps of the first embodiment of the present invention. First, the surface of the semi-insulating Ink (100) substrate 21 shown in FIG. On top of that, j5 EiiO is applied by CVD method etc.
, a mask 32 is attached, and striped openings with a width of 2 .mu.m are provided using a conventional photolithography technique to expose the nP substrate 21 and form a structure as shown in FIG. 2(b). Next, in the same figure (C), a striped groove having a depth of 0.3 .mu.m and a width of 2 .mu.m is formed in Oj5 by chemical etching using the aforementioned bromine/methanol mixture or by dry etching using ions. Next, the p-type 1nGaAs (N
~5 X 10"CI!-") Hole current extraction layer 2
Grow 2. P-type nGaAs hole current extraction layer 2
2 is also deposited on the mask 32 at 81o, but if the substrate crystal is taken out from the molecular beam epitaxy apparatus and etched with 7-acid, S10. It is removed together with the mask 32. In this way, p-type nGaAs is formed only in the grooves to obtain a substrate crystal as shown in FIG. 2(d). This is the p-type region formation process.Next, the substrate crystal on which the p-type InGjLAa hole current extraction layer 22 has been formed is again introduced into the molecular beam epitaxy apparatus, and the following layers are sequentially formed using the molecular beam epitaxy method. An epitaxial growth process is performed to stack layers to obtain the structure shown in FIG. 1(e). That is, n-type nGaAs (N ~ 3 x 1
0"cm-") The light absorption layer 23 is 1.5 μm thick, and the undoped layer 2 has a 82-dimensional electron gas formation space layer 2.
4 to 100λ, n type Aj engineering nA1! (N~5×10”c
m-”) The charge supply layer 25 is 0.1 μm thick and is made of n-type InGa.
8 (N~1×101cIIL″″3) electrode forming layer 26
There are 150 people involved.

Next, in the electrode forming step, a film of Sin and a mask is formed on the n-type InGaAs electrode forming layer 26 by the CVD method, and at least p-type InGaA holes of the Sin and mask are formed by ordinary photolithography technology. A portion of the current extraction layer 22 including the area directly above it is removed to expose the n-type nGaAa electrode formation layer 26. Subsequently, using the same etching method as in the p-type region forming step, the exposed portion is etched with n-type nGaAs.
Electrode formation layer 26, n-type AjIn layer 8 charge supply layer 25, A
The n-type nAa spacer layer 24 and the n-type nGaAs light absorption layer 23 are removed, and a p-type rnGa layer is formed as shown in FIG. 1(f).
As hole current extraction layer 22 and semi-insulating InP substrate 21
O to expose the surface of 810. The mask is further processed by photolithography to form a hole current extraction layer 22.
A striped opening is provided directly above the n-type nGaAs.
The electrode forming layer 26 is exposed. Next, in the same manner as the p-type region forming step, only the n-type nGaAθ charge supply layer 26 is removed in stripes, and the n-type AJNAs charge supply layer 25 is removed.
expose. Through the above steps, the structure shown in FIG. 1(f) is formed. Subsequently, gold/germanium is deposited on both of the remaining pair of n-type nGaAs+ electrode formation layers 26 to form an alloy to a depth that penetrates the a/doped AjInAs spacer layer 24 to form a source electrode 28 and a drain electrode 27. Further, gold and zinc are deposited on the exposed surface of the p-type InGaAa hole current extraction layer 22 and alloyed to form the hole current extraction electrode 30, and then the n-type one-layer nAa charge supply layer exposed in a stripe shape is formed. Titanium and gold are deposited on the gate electrode 25, and the M of the present invention shown in FIG. 4 is used as the gate electrode 29.
DPD is realized.

FIGS. 2<a> to 2(d) are diagrams showing a p-type region forming step in a second embodiment of the present invention. In this example, a S
10. Step of forming the mask 32 (FIG. 2(a), (
b) Since the steps up to ) are the same as those of the first embodiment described above, the explanation will be omitted. In the p-type region forming step of this embodiment, zinc is diffused as a p-type impurity into the substrate 21 shown in FIG.
) region (first semiconductor region) 22 with a width of ~2 μm1 and a depth of ~
A structure as shown in FIG. 3(0) is obtained by forming a layer over 0.3 μmK. Then 810. If the mask 32 is removed using hydrofluoric acid, a substrate crystal having a structure as shown in FIG. 3(d) will be obtained.

This completes the p-type region forming step. The subsequent epitaxial growth process and electrode formation process are the same as those in the first embodiment, and their explanation will be omitted. The second embodiment of the wooden tablet differs from the first embodiment in that the first semiconductor region is p-type nP22, but it has the advantage that epitaxial growth in the entire process can be performed only once, and is different from the first embodiment. MDP with the same effect as the example
D is realized.

Further, in the embodiment of wooden tablet 2, diffusion was used as the method for introducing the p-type impurity, but it goes without saying that ion implantation may also be used, and the impurity may be beryllium, magnesium, manganese, etc. instead of zinc.

FIG. 3(a) #(kl) is a diagram showing a p-type region forming step in a third embodiment of the present invention. p of this example
In the mold region forming step, the semi-insulating engineered nP substrate 21 is treated and cleaned in the same manner as in the first embodiment described above.
) and then introduced into a vacuum chamber equipped with a focused ion beam source. In this vacuum chamber, a beryllium ion beam was implanted as a p-type impurity in a stripe pattern (Fig. 1(1)).
The p-type InP hole current extraction layer 22 has a width of 2 μm as shown in FIG.
, is formed over a depth of 0.3 μm.

In the subsequent epitaxial growth step, the substrate crystal is introduced into a molecular beam epitaxy apparatus without being exposed to the atmosphere. A laminated structure was formed in the same manner as in the second embodiment, and as shown in FIG.
) to obtain the same structure. The subsequent electrode forming process is the 1st step. Since this is the same as the second embodiment, the explanation will be omitted.

According to the embodiment of wooden tablet 3, it is possible to perform the p-type region formation step and the epitaxial growth step in a consistent dry environment. This means that crystal defects due to contamination that occur when the substrate crystal is exposed to the atmosphere between processes and the complexity of the process are eliminated. Therefore, MDPDs with excellent device reliability and characteristics can be obtained with a high yield.

In the first to third embodiments, the p-type 1nGaAs hole current sinking layer 2 is etched after the epitaxial growth process in order to provide the hole current sinking electrode 30.
2 is exposed, and a hole current extraction electrode 30 is attached thereto. As another procedure, 1310. This objective can also be achieved by forming a selective growth mask such as the above and not forming a laminated structure by an epitaxial growth process on the mask, or by removing the mask and the laminated structure thereon later.

In addition, in the molecular beam epitaxy growth method in the above example,
The temperature during growth of the nP substrate 21 was controlled at 500° C., and Si was used as the n-type impurity and beryllium was used as the p-type impurity. The impurity may be an for n-type, and manganese, magnesium, etc. for p-type. Furthermore, it goes without saying that metal-organic vapor phase epitaxy, vapor phase epitaxy using halogen or halide, or liquid phase epitaxy may be used as the epitaxial method as long as they satisfy the requirements of the present invention.

Although the mask 32 was explained using S10° made by the CVD method, it may be made by the sputtering method, and the mask material may be 8ixNY, Alx0Y, or a resist film.

Furthermore, as an example, an InGjLAjAa-based material was explained using a semi-insulating engineered nP substrate 21, but I
It is clear that the present invention can be applied to other semiconductor materials such as nGanGa type, GaAa substrate, GaAjAs type using Ga8b substrate, and GaAjSb type. Also, the board 2
It goes without saying that 1 does not need to be a semiconductor as long as it is semi-insulating.

(Effects of the Invention) As described above in detail, according to the manufacturing method of the present invention, it is possible to obtain a novel photodetector with excellent high-speed response at a high yield.

[Brief explanation of drawings]

FIGS. 1(a) to (f) are diagrams showing the steps of the first embodiment of the present invention, and FIGS. 2(JL) to (d) are the steps of forming the p-type region in the second embodiment of the present invention. A diagram showing FIG. 3(a),
(1)) is a diagram showing the p-type region forming step in the third embodiment of the present invention, FIG. 4 is a perspective view of MDPD manufactured according to the first to third embodiments of the present invention, and FIG. is a sectional view taken along the broken line 310 in Fig. 4, and Fig. 6 is a conventional MDP.
It is a sectional view of D. 11.21... Semi-insulating nP substrate, 12... Undoped AJ nAs buffer layer, 22-1) Mold nGa
Aa (or InP) hole current extraction layer (first semiconductor region), 13#23-n WIInGaAs light absorption layer (second semiconductor layer), 14.24...A/doped layer nAa spacer layer (third semiconductor layer), 15.25・
...N-type 4-layer nAs charge supply layer (third semiconductor layer), 1
6.26...N-type nGaAs electrode formation layer (electrode formation layer), 17°27...Drain electrode (second electrode), x
L 28...source electrode (first electrode), 29...
Gate electrode (third electrode), 30... hole current extraction electrode (fourth electrode). Agent Patent Attorney Shinsuke Honjo Figure 1 Figure 1 (e) l (f) Figure 2 (a) (b) (c) Figure 3 (a) (b) ■0 P-type child feature Iomi / Fig. 4 21-Takuji connection base 22-Hole electric barley bite ridge L4 z3-44 collection layer 24-1-sube wt layer 25-f load thorn supply layer 26-sleep JFb type bemaro 27-- - Input i pole 28-111 North tun, 131 me 29--G °-t f pole 30--One hole embankment L pole Fig. 5 Fig. 6

Claims (1)

[Claims] a p-type region forming step of forming a p-type first semiconductor region on a part of the surface of the semi-insulating substrate; and at least an n-type second semiconductor layer on the substrate, the bandgap being larger than the second semiconductor layer. an epitaxial growth step of sequentially stacking an n-type third semiconductor layer for two-dimensional electron gas generation and an n-type electrode formation layer having a smaller band gap than the third semiconductor layer; and the first semiconductor on the electrode formation layer. The first layer is alloyed up to the region where the two-dimensional electron gas is formed at positions sandwiching the region.
and a second electrode on the surface of the third semiconductor layer.
and an electrode forming step of forming a third electrode in a region located between the second electrodes and a fourth electrode in the first semiconductor region.