JPS61288251A - Interruption vector generating method for programmable controller - Google Patents

Abstract

PURPOSE:To generate the interrupt vector of a programmable controller without using a setting switch by adding address contents, which are determined in accordance with the attaching position, to the interruption vector of an input/ output module. CONSTITUTION:Before the interruption processing is started, the input/output modules I/O1-I/On with interruption are accessed to store a decoding address signal ADR in a flip-flop F/F, and this signal is used as a part of vector information. This vector information is peculiar information determined in accordance with the attaching position of the input/output module. When an interruption signal IRP is active, a CPU activates a priority level determining signal PRT. This signal PRT passes modules in series, and modules closer to the CPU out of modules where the interruption signal IRP is generated respond successively to send a data signal to the data bus of a bus BUS, and the vector is reported to the CPU.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for generating an interrupt vector used for detecting an interrupt in a programmable controller.

[Technical background of the invention and its problems]

Generally programmable controller (hereinafter referred to as PC)
is equipped with a plurality of input/output modules in order to accommodate m number of control objects.

Since a PC performs simple loop program control such as scheduled scan control and free scan control via an input/output module, the interrupt processing function is limited compared to a normal computer.

Therefore, if you simply decide the control signals for the PC and input/output module by considering the use of the input/output module for interrupt control,
In general, input/output modules that do not have interrupts also require extra circuitry, which increases the overall cost.

Figure 5 is a system diagram showing the interface between the input/output module with interrupts and the computer in a normal computer.
U is the computer main body, BUS is the interface bus excluding interrupt signals, IRP is the interrupt signal, PRT is the priority determination signal, l101 to l10n are input/output modules with interrupts, DE
C is a decoder, and S1 to Sn are setting switches.

In FIG. 5, one interrupt address and information at the time of occurrence of an interrupt are set by setting switches 81 to Sn.

FIG. 6 is a timing chart showing the interrupt detection operation in FIG.
Activate I3.

The priority determination signal PRT is sent to the input/output modules l101~
110n in series, so among the input/output modules that generate the interrupt signal IRP, the computer main body CPU
Input/output modules close to the BUS respond sequentially and send data signals to the data bus in the BUS, thereby informing the CPU of encoded information and vectors.

CPLI reads the vector and returns PRT to inactive at time T3, and interrupt signal IRP returns the responding input/output module with interrupt to inactive on the l101 to l10n side (if the interrupt is duplicated, , other modules continue to output interrupts.) The problem here is that setting switches S, ~So are required.

In the case of a PC, there is generally no setting switch on the input/output module, and the PC side distinguishes the input/output module depending on its mounting position, but if a VL constant switch is added, the output module will not have an interrupt, as mentioned above. There is also rJJg that an extra circuit configuration is required for this, leading to an overall cost increase.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an interrupt vector generation method for a programmable controller that can control an interrupt module without using a setting switch and allowing the same handling as a general input/output module.

[Summary of the invention]

The present invention provides a programmable controller having an input/output module with an interrupt, in which address contents determined in accordance with the mounting position are added to the interrupt vector of the input/output module, thereby eliminating the need for a setting switch. This is an interrupt vector generation method.

[Embodiments of the invention]

An embodiment of the present invention is shown in FIG.

In the first [, the PC is a programmable controller,
ADH is the input/output module I with interrupt among the address signals.
10. Decoder address signal required to individually select ~l10n, DEC is decoder, SL□~S
Ln is a selection signal output from the decoder DEC.

FIG. 1 shows a method for classifying input/output modules, which is a feature of a PC, by mounting position using a decoder DECt-
In some cases, this is done by making a mistake.

Input/output module with interrupt when interrupt occurs 10. ~l10
The operation of n is similar to that shown in the timing chart of FIG.

In the case of FIG. 1, vector data is generated by storing the state of the decoder address signal ADH indicating the mounting position, so the setting switch 5 as in the conventional case of FIG.
L-Sn becomes unnecessary.

FIG. 2 shows an example of a circuit for storing the decoder address signal DR.

In FIG. 2, ADH is the address signal for the decoder in FIG. 1, and SL is one of the selection signals SL to SLn in FIG. 1, which are connected depending on the mounting position.
5TII is a strobe signal used in general input/output processing other than interrupt processing, F/F is a flip-flop, AND
is an AND gate, 13F is a gated buffer, G is a gate enable signal, and DATA is a data bus included in the ink face bus BUS in FIG.

In Fig. 2, before starting interrupt processing, the input/output module with interrupt is accessed once on the PC side, the decoder address signal ^DR is stored in the flip-flop F/F, and vector information is stored. Department.

The vector information with interrupt input/output modules l101 to I
/ It is unique and determined by the installation position of On.
There is no risk of duplication.

Another embodiment of the invention is shown in FIG.

Figure 3 shows the case where input/output modules are distinguished on the input/output module side, and PT, ~PTn are address signals ^DR provided according to the mounting position of the input/output module.
This is a fixed pattern signal for obtaining a match corresponding to.

In this case, the selection signals SL1 to SLl in FIG.

, address signal ADR and fixed pattern signal PT, ~
It is obtained inside the turnout module by matching PTn.

In the case of FIG. 3 as well, it is possible to classify the single-person output module according to the mounting position, and the circuit shown in FIG. 4 may be used to output vector information.

That is, in FIG. 4, the vector generation of the input/output module with interrupts is based on the fixed pattern signals PT, ~P in FIG.
Fixed pattern input section PT for inputting T.

It is sufficient to always output the state as part of the vector information.

〔Effect of the invention〕

As explained above, according to the present invention, the interrupt vector information of the input/output module with interrupts of the programmable controller can be set via the interface, so a setting switch is unnecessary, and this makes the input/output module with interrupts suitable for general use. This makes it possible to treat it in the same way as an input/output module, and also prevents a decrease in reliability and an increase in cost due to setting errors and contact failures due to the use of an H constant switch.

[Brief explanation of drawings]

FIG. 1 is an interface system diagram showing one embodiment of the present invention, FIG. 2 is a vector information storage/output circuit diagram in FIG. 1, and FIG. 3 is an interface system diagram showing another embodiment of the invention. Figure 4 is a vector information output circuit diagram in Figure 3;
FIG. 5 is an interface system diagram of a conventional input/output module with interrupts, and FIG. 6 is an operation timing diagram of interrupt detection. cpu Computer main body BUS Interface bus IRP Interrupt signal PRT Priority determination signal DATA Data bus ADH address signal for decoder DEC decoder 5Lr (SL1 to 5Ln) Selection signal STB
Strobe signal PT! (Pd□~PTn) Mounting position fixed pattern signal AND gate F/F Flip-flop 8F Gated buffer (8733) Agent Patent attorney Yoshiaki Inomata (1 person) @1 Figure 2 PT I PTZ PT Figure 3 Figure 4

Claims (1)

[Claims] An interrupt vector generation method for a programmable controller having an input/output module with an interrupt, the method comprising: adding address contents determined in accordance with a mounting position to the interrupt vector of the input/output module.