JPS61285831A - Decision feedback type automatic equalizer - Google Patents

Decision feedback type automatic equalizer

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Publication number
JPS61285831A
JPS61285831A JP12601085A JP12601085A JPS61285831A JP S61285831 A JPS61285831 A JP S61285831A JP 12601085 A JP12601085 A JP 12601085A JP 12601085 A JP12601085 A JP 12601085A JP S61285831 A JPS61285831 A JP S61285831A
Authority
JP
Japan
Prior art keywords
adder
signal
output
interference component
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12601085A
Other languages
Japanese (ja)
Inventor
Ritsuko Shinozuka
篠塚 立子
Hiroshi Takatori
鷹取 洋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12601085A priority Critical patent/JPS61285831A/en
Publication of JPS61285831A publication Critical patent/JPS61285831A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To equalize correctly an input pulse signal including a forward interference component independently of the quantity of backward interference component by eliminating the forward interference component from the signal obtained by eliminating the backward interference component of an input pulse signal by a decision feedback equalizer. CONSTITUTION:A pulse a1 with distorted waveform is fed to an input terminal. A discriminator 3 compares the output of an adder 2 with a threshold value at a timing 0 to decide whether '1' to '0'. The output pulse (b) of the discriminator 3 is subjected to the multiplication of coefficients C<(1)>, C<(2)> by multipliers 5-1, 5-2 via delay elements 4-1, 4-2 having a delay time T, becomes signals b1,b2, which are returned to the adder 2. Thus, the backward interference component is eliminated from the input pulse a1 by timing points T, 2T, 3T. The output of the adder 2 is retarded by a time equal to the basic period T of the input pulse by the delay element 7-1 and the result is fed to an adder 8. On the other hand, a multiplier 6-1 multiplies a coefficient C<(-1)> with the output pulse (b) of the discriminator 3 to form a signal b3. The adder 8 subtracts the forward interference component b3 from the input pulse signal extracted by the backward interference component.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は判定帰還形自動等化器、更に詳しく言えば、入
力パルス信号のレベルを判定し、その判定した信号に一
定の処理加えて入力パルスの歪成分(干渉波形)を検出
して、入力パルス信号から差引くことによって、等化さ
れた波形のパルスを自動的に得る等化器に係る。
[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a decision feedback type automatic equalizer, and more specifically, the present invention determines the level of an input pulse signal, performs certain processing on the determined signal, and processes the input pulse signal. The present invention relates to an equalizer that automatically obtains pulses of an equalized waveform by detecting a distortion component (interference waveform) of and subtracting it from an input pulse signal.

〔発明の背景〕[Background of the invention]

伝送によって波形が歪んだパルス信号から再生パルスを
得る場合には、伝送器の5特性を5等化器によって等化
を行った後、上記判定帰還形等化器によって、パルスの
識別時点における干渉波形の成分を除く回路が知られて
いる。
When obtaining a reproduced pulse from a pulse signal whose waveform has been distorted by transmission, the five characteristics of the transmitter are equalized by a five equalizer, and then the decision feedback equalizer is used to eliminate interference at the time of pulse identification. Circuits that remove waveform components are known.

パルス信号の速度(ボーレート)が速くなると、パルス
信号の識別時点よりパルス周期以前の時点がOとならな
い、いわゆる前方干渉成分が生じる。
When the speed (baud rate) of the pulse signal increases, a so-called forward interference component occurs, in which the pulse signal does not become O at a point before the pulse period from the point of identification of the pulse signal.

この前方干渉成分を除くものとして、判定帰還形等化器
の前段にトランスバーサルフィルタを配し、前方干渉成
分を除いた後、判定帰還等化器で後方干渉成分を除くも
のが知られている【昭59信学全国大会の講演集Nα4
75「ディジタル信号処理形自動等化LSIの構成J)
。しかし、上記の等化器では後方干渉を含んだ信号を一
度識別してから擬似的に前方干渉成分を作り出すもので
あるため、後方干渉成分が大きい場合はパルスの識別が
正しく行われない場合が生じるという問題がある。
A known method for removing this forward interference component is to place a transversal filter in front of a decision feedback equalizer, remove the forward interference component, and then use a decision feedback equalizer to remove the rear interference component. [Collection of lectures from the 1980 National Conference on IEICE Nα4
75 “Configuration of digital signal processing automatic equalization LSI J)
. However, since the above-mentioned equalizer first identifies a signal containing backward interference and then creates a pseudo forward interference component, if the backward interference component is large, the pulses may not be identified correctly. There is a problem that arises.

〔発明の目的〕[Purpose of the invention]

したがって、本発明の目的は後方干渉成分の大小に係ら
ず、前方干渉成分を含む入力パルス信号を正しく等化す
ることができる自動等化器を実現することができる。
Therefore, an object of the present invention is to realize an automatic equalizer that can correctly equalize an input pulse signal including a forward interference component, regardless of the magnitude of the backward interference component.

〔発明の概要〕[Summary of the invention]

本発明は上記目的を達成するために、入力パルス信号の
後方干渉成分を判定帰還等化器で除去した信号から、前
方干渉成分を除去するようにしたものであり、後方干渉
成分を除く場合には判定帰還等化器の構成より、前方干
渉成分の影響を受けることがなく、また、前方干渉成分
の除去は、後方干渉成分を除いた信号から前方干渉成分
が抽出されるため、前方及び後方干渉の周成分を正しく
除去することができる。
In order to achieve the above object, the present invention removes the forward interference component from a signal obtained by removing the backward interference component of the input pulse signal using a decision feedback equalizer. is not affected by the forward interference component due to the configuration of the decision feedback equalizer, and the front interference component is extracted from the signal excluding the rear interference component, so the front interference component is extracted from the signal excluding the rear interference component. The circumferential component of interference can be correctly removed.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の実施例を図面を用いて詳細に説明する。 Embodiments of the present invention will be described in detail below with reference to the drawings.

第1図は本発明による自動等化器の一実施例の構成を示
すブロック図である。第2図は上記第1図の実施例の動
作説明のための波形図である。なお、本実施例は説明の
簡明のため最も簡単な構成の例を示す。
FIG. 1 is a block diagram showing the configuration of an embodiment of an automatic equalizer according to the present invention. FIG. 2 is a waveform diagram for explaining the operation of the embodiment shown in FIG. Note that this embodiment shows an example of the simplest configuration for simplicity of explanation.

入力端子にはa□のような前方干渉成分および後方干渉
成分を含んだ歪んだ波形のパルスが加えられる。これら
の波形は理想的にはタイミング時点n T (n=Oe
±T、2T、−)で干渉成分が0となることが望ましい
。この入力信号a1は加算器2で後述の帰還信号(擬似
後方干渉成分)が差引かれる。
A distorted waveform pulse containing a forward interference component and a backward interference component such as a□ is applied to the input terminal. These waveforms are ideally located at timing points n T (n=Oe
It is desirable that the interference component be 0 at ±T, 2T, -). This input signal a1 is subjected to an adder 2 from which a feedback signal (pseudo rear interference component), which will be described later, is subtracted.

識別器3は加算器の出力をタイミング時点Oで閾値と比
較し、′1”か“OPIを判定する。なお。
The discriminator 3 compares the output of the adder with a threshold value at timing point O and determines '1' or 'OPI'. In addition.

入力信号がバイポーラ符号であるときは更に極性の識別
を行うが、説明は単極性の場合として説明する。
When the input signal is a bipolar code, the polarity is further identified, but the description will be made assuming a unipolar case.

識別器の出力パルスbは遅延時間Tを有する、直列接続
された遅延素子4−1および4−2に加えられる。各遅
延素子4−1および4−2の出力はそれぞれ、乗算器5
−1および5−2で係数CD) 、 ()、 (z)が
乗ぜられ、信号b□およびb2 となる。これらの係数
は、後で説明するように識別タイミング時点、nTで干
渉成分を擬似的に作るように決定される。これらの擬似
的に作られた後方干渉成分は帰還信号として前記加算器
2に加えられる6従って2例えば正極性の連続する入力
パルスがあるときは、上記第2図(a)の入力パルスa
工は(凍)のようになり、タイミング時点T。
The output pulse b of the discriminator is applied to series-connected delay elements 4-1 and 4-2 having a delay time T. The output of each delay element 4-1 and 4-2 is outputted to a multiplier 5, respectively.
-1 and 5-2 are multiplied by coefficients CD), (), and (z), resulting in signals b□ and b2. These coefficients are determined so as to create a pseudo interference component at the identification timing point nT, as will be explained later. These pseudo-generated backward interference components are added to the adder 2 as a feedback signal 6 Therefore, 2 For example, when there are continuous input pulses of positive polarity, the input pulse a in FIG.
The process becomes like (frozen), and the timing is T.

2T、3Tで後方干渉成分が除かれたものとなる。The backward interference component is removed at 2T and 3T.

上記加算器2の出力は更に遅延素子7−1によって、入
力パルスの基本周期Tに等しい時間遅されたのち加算器
8に加えられる。−万乗算器6−1は上記、識別器3の
出力パルスbに、後で説明する係数C(−1)を乗じ、
信号b3とする。このb3は、入力パルスのタイミング
時点−Tでの前方干渉成分h0に等しいレベルの信号で
ある。
The output of the adder 2 is further delayed by a delay element 7-1 by a time equal to the fundamental period T of the input pulse, and then added to the adder 8. - The multiplier 6-1 multiplies the output pulse b of the discriminator 3 by a coefficient C (-1), which will be explained later,
Let it be signal b3. This b3 is a signal with a level equal to the forward interference component h0 at timing point -T of the input pulse.

加算器8では、後方干渉成分が除かれた入力パルス信号
から擬似的に作られた前方干渉成分b3が差引かれる。
The adder 8 subtracts the artificially created forward interference component b3 from the input pulse signal from which the backward interference component has been removed.

第2の識別回路9は上記加算器8からの前方及び後方干
渉成分を除かれた、すなわち等化波形から入力パルス信
号が1”かROIIかを判別し、出力端子10より、識
別出力パルスを発生する。
The second discrimination circuit 9 discriminates whether the input pulse signal is 1'' or ROII from the equalized waveform after removing the forward and backward interference components from the adder 8, and outputs the discrimination output pulse from the output terminal 10. Occur.

加算回路11は、前述の係数C”、C(1)。The adder circuit 11 uses the above-mentioned coefficients C'' and C(1).

C(リ を決定する係数制御回路(図示されていない)
を駆動するための信号θ、すなわち識別器の入出力信号
の誤差信号を得るためのものである。
Coefficient control circuit (not shown) that determines
This is to obtain the signal θ for driving the discriminator, that is, the error signal of the input/output signal of the discriminator.

これらの係数制御回路は一般に知られているので詳細な
構成は省略するが、原理的には次の式の演算を行う回路
で実現される。すなわち、入力パルス信号のレベルをX
、誤差信号のレベルをe、更新ステップ幅をΔとしたと
き、 c、、1==c m+Δ・SGN (8−+−t) ’
 Xm+z+1  ”’(’)C14、=C,+Δ・S
GN (am−2)” x、−、−1−j=(2)の演
算を行うことによって実現される。ここで、SGN (
e)は誤差信号eの極性を表す。上記式のi = −1
、j =1 、2としたものが、第1図の実施例であっ
て(1)式は前方干渉成分除去のための係数c −1を
得るためものであり、(2)式は後方干渉成分を除去す
るための係数G (1)、 C(2)を得るための式で
ある。
Since these coefficient control circuits are generally known, their detailed configuration will be omitted, but in principle they are realized by a circuit that performs the calculation of the following equation. In other words, the level of the input pulse signal is
, when the level of the error signal is e and the update step width is Δ, c,, 1==c m+Δ・SGN (8-+-t)'
Xm+z+1 ”'(')C14,=C,+Δ・S
GN (am-2)" x, -, -1-j = (2).Here, SGN (
e) represents the polarity of the error signal e. i = −1 in the above formula
, j = 1, 2 is the embodiment shown in FIG. This is a formula for obtaining coefficients G (1) and C (2) for removing components.

第3図は本発明による自動等化器の他の実施例の構成を
示すブロック図である。本実施例は前方及び後方干渉が
長いタイムスロットにわたって考慮する必要がある場合
に有効なもので、構成上、第1図の実施例に比べ、遅延
素子4−1〜4−kが多いこと、遅延手段7の遅延時間
が長い場合を除いては、実質的に第1図の場合と同じで
、同じ機能を示すブロックについては同一の番号を付し
ている。
FIG. 3 is a block diagram showing the structure of another embodiment of the automatic equalizer according to the present invention. This embodiment is effective when forward and backward interference needs to be considered over a long time slot, and in terms of configuration, there are more delay elements 4-1 to 4-k than in the embodiment shown in FIG. Except for the case where the delay time of the delay means 7 is long, this is substantially the same as in FIG. 1, and blocks having the same functions are given the same numbers.

〔発明の効果〕〔Effect of the invention〕

以上述べたように本発明によれば、前方干渉除去の操作
を後方干渉除去した後の信号を用いて行なうため、50
%以上の後方干渉を持つ入力に対しても前方干渉の等化
ができる自動等化器の実現をすることができる。また、
前方及び後方の干渉を取り除いた後より抽出した等化誤
差よりフィルタ係数の制御情報を取り出す構成をとって
いるので前方干渉除去の系と後方干渉除去の系の誤り波
及の防止ができる。
As described above, according to the present invention, since the forward interference cancellation operation is performed using the signal after the backward interference cancellation,
It is possible to realize an automatic equalizer that can equalize forward interference even for inputs having backward interference of % or more. Also,
Since the filter coefficient control information is extracted from the equalization error extracted after the forward and backward interferences are removed, it is possible to prevent errors from spreading between the forward interference cancellation system and the backward interference cancellation system.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明による自動等化器の一実施例の構成図、
第2図は上記実施例の動作説明のための波形図、第3図
は本発明による自動等化器の他の実施例の構成図である
。 1・・・入力端子、2,8.11・・・加算器、3,9
・・・識別器、4,7・・・遅延素子、5,6・・・乗
算器。 早 l 目 S−t      Φ−2 第 2 回 すおエコ’:l:l。
FIG. 1 is a block diagram of an embodiment of an automatic equalizer according to the present invention;
FIG. 2 is a waveform diagram for explaining the operation of the above embodiment, and FIG. 3 is a configuration diagram of another embodiment of the automatic equalizer according to the present invention. 1...Input terminal, 2,8.11...Adder, 3,9
... Discriminator, 4, 7... Delay element, 5, 6... Multiplier. Early 1st S-t Φ-2 2nd Suo Eco':l:l.

Claims (1)

【特許請求の範囲】 1、入力パルス信号から第1の帰還信号を差引く第1の
加算器と、上記第1の加算器の出力を判定する第1の識
別回路と、上記第1の識別回路の出力より上記入力パル
ス信号中の後方干渉信号を抽出して上記第1の帰還信号
及び上記入力パルス信号中の前方干渉信号を作るディジ
タル回路と、上記第1の加算器の出力を上記入力パルス
信号の周期の整数倍時間遅延する遅延手段と、上記遅延
手段の出力から上記前方干渉信号を差引く第2の加算器
と、上記第2の加算器の出力を判定し等化出力信号とす
る第2の識別回路を具備して構成された判定帰還形自動
等化器。 2、第1項記載の自動等化器において、上記ディジタル
回路は縦続接続された複数の遅延素子と、上記複数の遅
延素子のそれぞれの入出力に係数を乗する係数回路と、
上記第2の識別回路の入出力の差信号によつて上記係数
を制御する手段を具備して構成された判定帰還形自動等
化器。
[Claims] 1. A first adder that subtracts a first feedback signal from an input pulse signal, a first identification circuit that determines the output of the first adder, and the first identification circuit. a digital circuit that extracts the backward interference signal in the input pulse signal from the output of the circuit and generates the first feedback signal and the forward interference signal in the input pulse signal; and the output of the first adder is input to the digital circuit. a delay means for delaying the pulse signal by an integral multiple of the period of the pulse signal; a second adder for subtracting the forward interference signal from the output of the delay means; and an equalized output signal for determining the output of the second adder. A decision feedback type automatic equalizer configured to include a second discrimination circuit. 2. In the automatic equalizer described in item 1, the digital circuit includes a plurality of cascade-connected delay elements, a coefficient circuit that multiplies the input and output of each of the plurality of delay elements by a coefficient,
A decision feedback type automatic equalizer comprising means for controlling the coefficients based on a difference signal between the input and output of the second discrimination circuit.
JP12601085A 1985-06-12 1985-06-12 Decision feedback type automatic equalizer Pending JPS61285831A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12601085A JPS61285831A (en) 1985-06-12 1985-06-12 Decision feedback type automatic equalizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12601085A JPS61285831A (en) 1985-06-12 1985-06-12 Decision feedback type automatic equalizer

Publications (1)

Publication Number Publication Date
JPS61285831A true JPS61285831A (en) 1986-12-16

Family

ID=14924491

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12601085A Pending JPS61285831A (en) 1985-06-12 1985-06-12 Decision feedback type automatic equalizer

Country Status (1)

Country Link
JP (1) JPS61285831A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5995545A (en) * 1996-03-11 1999-11-30 Fujitsu Limited Signal reproducing method and apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5995545A (en) * 1996-03-11 1999-11-30 Fujitsu Limited Signal reproducing method and apparatus

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