JPH0669157B2 - Automatic equalizer - Google Patents

Description

The present invention relates to an automatic equalizer, and more particularly to an automatic equalizer used for equalizing propagation distortion in a communication system.

[Conventional technology]

An automatic equalizer equipped with a transversal filter is used for equalization of time-varying propagation distortion in a communication system. For example, it is used for equalizing propagation distortion due to selective fading in a digital wireless communication system.

Such an automatic equalizer generates a tap control signal from the (equalization) error signal and the data signal output by the demodulator used at the same time. The demodulator reproduces the carrier signal inside. If the propagation distortion due to the selective fading becomes excessive and the equalizer cannot be fully equalized, the demodulator may not be able to reproduce the carrier signal. At this time, the data signal and the error signal have irregular values, and therefore the tap control signal also does not correspond to the propagation distortion, so that the output of the automatic equalizer has irregular distortion. Once such a state occurs, even if the selective fading is restored, the output of the automatic equalizer remains irregularly distorted, and the demodulator cannot reproduce the carrier signal, thus not returning to normal operation. In order to avoid such a situation, there is an automatic equalizer that has a function of resetting the carrier signal to the initial state (the input and output of the automatic equalizer have the same waveform) when the demodulator cannot reproduce the carrier signal. . If the automatic equalizer is reset, the demodulator can regenerate the carrier signal and return to normal operation when the selective fading is restored.

FIG. 2 is a partial block diagram showing an example of a tap signal generator included in a conventional automatic equalizer having such a reset function, which is the nth variable weighting circuit of the automatic equalizer. Only the part that generates the tap control signal Cn that controls the is shown. Therefore, the tap signal generator 13 has the same number of parts as the part surrounded by the chain line in FIG.

The portion of the tap signal generator 13 shown in FIG. 2 includes a correlation circuit 121 that inputs the data signal s ₃ and the error signal e and outputs the signal C ₁₁ , and a signal C ₁₁ , tap control signal Cn, and reset signal r. Reset circuit 122 which inputs the signal C ₁₃ and outputs the signal C _13, and the integration circuit 123 which inputs the signal C ₁₃ and outputs the tap control signal Cn.
And is configured. The reset circuit 122 uses the signal C
_11. AND gate G ₁ for inputting the reset signal r, AN for inputting the inverted signal of the reset signal r and the tap control signal Cn AN
Input the output of D-gate G ₂ and AND gates G ₁ and G ₂ to signal C ₁₃
And an OR gate G ₃ for outputting Integrating circuit 123
Has a resistor R ₁ , R ₂ , R ₃ , a capacitor C, and an operational amplifier OP that outputs a tap control signal Cn. The other end with the input reference signal V to one end of the resistor R ₁ is connected to the positive input terminal of the operational amplifier OP, one end and the other end to the signal C ₁₃ is input to the resistor R ₂ is the resistance R ₃ · capacitor C One end of those connected in parallel is connected to the negative input terminal of the operational amplifier OP in common, and the other end of the resistor R ₃ and the capacitor C connected in parallel is connected to the output terminal of the operational amplifier OP.

The demodulator used together with the automatic equalizer having the tap signal generator 13 outputs a reset signal r in addition to the data signal s ₃ and the error signal e. The reset signal r is in the state "1" when the demodulator is normally reproducing the carrier signal, and is in the state "0" when the carrier signal cannot be reproduced.

In the tap signal generator 13, the correlation circuit 121 performs a predetermined correlation calculation for correlating the data signal s ₃ and the error signal e, and outputs the result as a signal C ₁₁ . When the reset signal r is in the state “1”, the AND gate G ₁ in the reset circuit 122
And the AND gate G ₂ is closed, the signal C ₁₃ which is the output of the OR gate G ₃ becomes the signal C ₁₁ itself. That is, at this time, the signal C ₁₃ which is the output of the reset circuit 122 becomes the signal C ₁₁ itself. At this time, the integration circuit 123 integrates / smooths the signal C ₁₃ (that is, the output of the correlation circuit 121) and tap control signal C
Output as n. The tap control signal Cn controls the nth variable weighting circuit of the automatic equalizer.

When the reset signal r is in the state “0”, the AND gate G ₁ is closed and the AND gate G ₂ is opened in the reset circuit 122, so that the OR gate G ₃ outputs the output of the AND gate G ₂ to the integrating circuit 123 as the signal C _13. Output. AND gate if the value of one tap control signal Cn is the input of G ₂ is greater than the threshold of the AND gate G ₂ output of the AND gate G ₂ is a state "1" is the output of the integration circuit 123 The value of the tap control signal Cn decreases.
On the contrary, when the value of the tap signal Cn is smaller than the threshold value of the AND gate G ₂ , the output of the AND gate G ₂ becomes the state “0”, and the value of the tap control signal Cn increases. Therefore, at this time, the value of the tap control signal Cn is fixed to the threshold value of the AND gate G ₂ . When the tap control signal Cn has this value, the output of the n-th variable weighting circuit has the value "0". Since the reset signal r is in a state "0" the values of all of the tap control signals in this manner is fixed to the threshold of the AND gate G _2, an automatic equalizer outputs an input waveform as it is. That is, it is reset.

By the way, it is desirable that the automatic equalizer is configured with CMOS LSI as wide as possible in order to reduce power consumption, reduce size, and improve productivity. However, the tap signal generator 13 is
If it is configured with this LSI, the AND gate G ₂ may be damaged. As is well known, a CMOS-structured logic circuit is configured to include a series connection pair of an n-channel transistor and a P-channel transistor, and one transistor is always in an on state and the other transistor is in an off state to form a series connection pair. Almost no current flows. However, AND
Since one of the inputs of the gate G ₂ is held at the threshold value at the time of reset, neither of the transistors in the series connection pair is turned off. Therefore, the current may rapidly increase and the power consumption of the LSI including the plurality of AND gates G ₂ may sharply increase, which may damage the LSI.

As explained above, conventional automatic equalizers use CMOS LS
The I configuration has the disadvantage that the gate may be damaged.

[Problems to be solved by the invention]

A problem to be solved by the present invention, in other words, an object of the present invention is to solve the above-mentioned drawbacks and to provide an automatic equalizer without damaging a gate composed of a CMOS LSI. .

[Means for solving problems]

The automatic equalizer of the present invention is a transversal filter that inputs a digitally modulated signal, equalizes and outputs a waveform, and a data signal obtained by inputting the signal output by this transversal filter to a demodulator. One of a correlation circuit for performing a correlation calculation with an error signal and outputting a calculation result, a buffer circuit, and an output signal of the correlation circuit or an output signal of the buffer circuit corresponding to the state of a binary reset signal. A reset circuit that selects and outputs
The reset circuit includes an integrator circuit that inputs a signal output from the reset circuit and outputs a tap control signal to the transversal filter and the buffer circuit, and the correlation circuit and the reset circuit are configured by a CMOS LSI. Is configured separately from the LSI.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings illustrating an embodiment.

FIG. 1 (b) is a block diagram showing an automatic equalizer 1 according to an embodiment of the present invention and an example 2 of a demodulator used at the same time.

The automatic equalizer 1 inputs the received signal s ₁ , the data signal s ₃ , the error signal e. The reset signal r, and outputs the equalized signal s ₂ .
The demodulation device 2 inputs the equalized signal s _2, and outputs the data signal s ₃ , error signal e, and reset signal r.

The automatic equalizer 1 comprises a transversal filter 11 and a tap signal generator 12. The transversal filter 11 includes delay circuits T _{1 to} T ₄ and a multiplication circuit M ₁
And ~M _8, is constituted by a synthesizer A ₁ to A _3. The received signal s ₁ is input to the delay circuit T ₁ , and the delay circuit Tm (m is 1 ·
The output of 2 or 3) is input to the delay circuit Tm _{+ 1} . The received signal s ₁ and the outputs of the delay circuits T ₁ , T _3, and T ₄ are each divided into two and input to the multiplication circuits M _{1 to} M ₈ . The tap control signal Cn is input to the multiplication circuit Mn (n is an integer of 1 to 8). The outputs of the multiplication circuits M ₂ , M ₄ , M ₆ , M ₈ and the delay circuit T ₂ are input to the combiner A _1, and the outputs of the multiplication circuits M ₁ , M ₃ , M ₅ , M ₇ are combined A ₂ To enter. The 0-degree pin-90 degrees terminal combiner A ₃ is input the output of the combiner A ₁ · A _2, synthesizer A ₃ outputs the equalized signal s _2. The tap signal generator 12 outputs the data signal s ₃
Input the error signal e and the reset signal r, and output the tap control signal Cn.

The demodulator 2 includes a detection circuit 21 that inputs the equalized signal s ₂ and the carrier signal Cr and outputs a baseband signal s ₂₁ , and a carrier reproduction circuit 22 that outputs the carrier signal Cr and the reset signal r.
And a discrimination circuit 23 which inputs the baseband signal s ₂₁ and outputs the data signal s ₃ and the error signal e.

First, the operation of the demodulation device 2 will be described.

The equalized signal s ₂ is obtained by waveform-equalizing the digitally modulated received signal s ₁ in the intermediate frequency band by the automatic equalizer 1, and the baseband signal s ₂₁ is detected by the carrier signal Cr in the detection circuit 21. Becomes The carrier reproduction circuit 22 reproduces the carrier signal Cr and sets the reset signal r to the state "1" when the carrier signal Cr is reproduced normally. When the carrier signal Cr cannot be reproduced, the reset signal r is changed to the state “0”.
To The discrimination circuit 23 discriminates the baseband signal s ₂₁ and outputs the data signal s ₃ and the error signal e. The data signal s ₃ is
This is the signal transmitted by the received signal s ₁ . The error signal e is a signal representing the deviation of the level of the baseband signal s _{21 at} the discrimination point from the normal level, and the equalized signal s ₂
It corresponds to the equalization error of.

Next, the operation of the automatic equalizer 1 will be described.

In the transversal filter 11, the delay circuit Tk (k
Is an integer of 1 to 4) and outputs a signal that is shifted by the time kT from the received signal s ₁ . The multiplying circuits M ₁ and M ₂ operate as variable weighting circuits and output the amplitude of the received signal s ₁ by controlling it with tap control signals C ₁ and C ₂ . Similarly multiplier circuit M ₃ ~M ₈ and the outputs to control the amplitude of the output of the delay circuit T ₁ · T ₃ · T ₄ by the tap control signal C ₃ -C _8. The outputs of the multiplying circuits M ₂ , M ₄ , M _6, and M ₈ are combined with the output of the delay circuit T _{2 by} the combiner A ₁ to equalize the common mode distortion of the received signal s ₁ . The outputs of the multiplication circuits M ₁ , M ₃ , M _5, and M ₇ are orthogonally combined with the output of the combiner A _{1 by} the combiner A ₃ via the combiner A ₂ to equalize the orthogonal distortion of the received signal s _1. To do.

When the reset signal r is in the state “1”, the tap signal generator 12 changes the data signal s ₃ and the error signal e from the tap control signals c ₁ to.
produces c ₈ . When the reset signal r is in the state "0",
The values of the tap control signals c _{1 to} c ₈ are fixed to a certain constant value. When the values of the tap control signals c _{1 to} c ₈ reach this constant value, the outputs of the multiplication circuits M _{1 to} M _{8 in} the transversal filter 11 become the value “0”, and the transversal filter 11 delays the delay circuit T ₂
Output only the output of. Therefore, the automatic equalizer 1 is
When the reset signal is in the state “0”, the same signal as the received signal s ₁ is output as the equalized signal s ₂ except that it is shifted by 2T, that is, reset.

FIG. 1 (a) is a partial block diagram showing the details of the tap signal generator 12 in FIG. 1 (b), and shows only the portion for generating the tap control signal Cn. The tap signal generator 12 has eight parts equivalent to the parts sandwiched by the chain lines in FIG. 1 (a).

In the part shown in FIG. 1 (a), the tap control signal Cn is input to the part of the tap signal generator 13 shown in FIG.
It is configured by adding a non-inverting gate 124 for outputting to the ND gate G ₂ .

Of the circuits forming the tap signal generator 12, each of the eight correlation circuits 121 and the reset circuit 122 are integrally formed by a CMOS gate array, and each of the non-inverting gates 124 is separated from the gate array. TTL (transistor transist
or logic).

The portion of the tap signal generator 12 shown in FIG. 1 (a) performs the same operation as the portion of the tap signal generator 13 shown in FIG. 2 when the reset signal r is in the state "1", and the data signal s _3. Generate the tap control signal Cn from the error signal e.

When the reset signal r is in the state “0”, the reset circuit 122 is A
The output of the ND gate G ₂ is output to the integrating circuit 123 as the signal C13. At this time, the value of the tap control signal Cn is
Signal C12 goes to state “1” if
Since the output of the ND gate G ₂ also becomes the state “1”, the value of the tap control signal Cn decreases. Conversely, if the value of tap control signal Cn is less than the threshold of non-inverting gate 124, then signals C12 and
The output of AND gate G ₂ goes to state “0” and tap control signal C
The value of n increases. Therefore, at this time, tap control signal C
The value of n is fixed at the threshold of the non-inverting gate 124. Output value "0" of the multiplier circuit M ₁ ~M ₈ of the transversal filter 11 the tap control signal C1~C8 of this value is inputted,
The automatic equalizer 1 is reset.

Signal C12 at reset becomes repetition of the state "1" and "0", since it will not remain in the vicinity of the threshold of the AND gate G _2, there is no possibility that the AND gate G ₂ is damaged. Also,
Each of the non-inverting gates 124 has a correlation circuit 1 for the number of taps.
21 and the reset circuit 122 are physically separated from the built-in gate array, the amount of heat generated by the increase in current due to the input value being held at a threshold value is the same as that of the conventional gate array. It is sufficiently smaller than the quantity, so there is no risk of damage.

〔The invention's effect〕

As described in detail above, since the present invention uses the means of providing the non-inverting gate that gates the tap control signal, the automatic equalizer of the present invention is configured by CMOS LSI without fear of damage. Therefore, there is an effect that the power consumption can be reduced, the size can be reduced, and the productivity can be improved.

[Brief description of drawings]

1 (a) is a partial block diagram showing the details of the tap signal generator 12 in FIG. 1 (b), and FIG. 1 (b) is an embodiment of the automatic equalizer of the present invention.
FIG. 2 is a block diagram showing an example of a demodulator used at the same time, and FIG. 2 is a partial block diagram showing an example of a tap signal generator included in a conventional automatic equalizer. 121 ... Correlation circuit, 122 ... Reset circuit, 123 ... Integration circuit, 124 ... Non-inverting gate.

Claims (1)

[Claims] 1. A transversal filter for inputting a digitally modulated signal and equalizing and outputting the waveform, and a data signal and an equalization error signal obtained by inputting the signal output by the transversal filter to a demodulator. A correlation circuit for performing a correlation calculation and outputting a calculation result; a buffer circuit;
A reset circuit that selects and outputs either the output signal of the correlation circuit or the output signal of the buffer circuit according to the state of the reset signal of the value, and the signal output by the reset circuit is input and tapped. The transversal filter and an integrator circuit for outputting a control signal to the buffer circuit are provided, the correlation circuit and the reset circuit are configured by a CMOS LSI, and the buffer circuit is the L circuit.
An automatic equalizer characterized by being configured separately from SI.