JPS61285721A - Etching method for silicon oxide - Google Patents

Etching method for silicon oxide

Info

Publication number
JPS61285721A
JPS61285721A JP12741885A JP12741885A JPS61285721A JP S61285721 A JPS61285721 A JP S61285721A JP 12741885 A JP12741885 A JP 12741885A JP 12741885 A JP12741885 A JP 12741885A JP S61285721 A JPS61285721 A JP S61285721A
Authority
JP
Japan
Prior art keywords
etching
sio2
substrate
atoms
silicon oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12741885A
Other languages
Japanese (ja)
Other versions
JPH0646628B2 (en
Inventor
Kazunari Oota
一成 太田
Masahiro Hagio
萩尾 正博
Masaru Kazumura
数村 勝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP12741885A priority Critical patent/JPH0646628B2/en
Publication of JPS61285721A publication Critical patent/JPS61285721A/en
Publication of JPH0646628B2 publication Critical patent/JPH0646628B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To enable the complete etching of SiO2 by placing the etching auxiliary material consisting of Si atoms adjacently to the object to be etched before etching the SiO2 formed on a substrate not including Si atoms. CONSTITUTION:Before etching the SiO2 thin film 2 formed on a GaAs substrate 1, the whole substrate 1 is placed on a crystal (SiO2) plate 3 for etching. A plenty of SiFx ions produced by etching the crystal plate 3 exist even right before the SiO2 2 on the substrate 1 is eliminated, so that those are accelerated by self-bias voltage and bump against the wafer surface, thereby preventing the formation of polymer. At this time, an etching rate of SiO2 is always constant and does not change before the quantity of remaining SiO2 2 becomes zero. Thus, the complete removal is done.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置の製造において広く使われる酸化シ
リコンのエツチング方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for etching silicon oxide, which is widely used in the manufacture of semiconductor devices.

、 従来の技術 酸化シリコンは、絶縁性に優れ、形成も容易であること
から、半導体装置の眉間絶縁膜として広く使われている
。半導体装置の高集積化に伴い、酸化シリコンのエツチ
ングも従来の弗酸系によるウェットエツチングから、よ
り微細な形状加工の可能なドライエツチングへと移行し
てきた。
, Conventional Technology Silicon oxide has excellent insulating properties and is easy to form, so it is widely used as a glabellar insulating film for semiconductor devices. As semiconductor devices become more highly integrated, the etching of silicon oxide has shifted from the conventional wet etching using hydrofluoric acid to dry etching, which allows finer shape processing.

5102のドライエツチングはガスプラズマ、特にRI
Eと呼ばれる反応性ガスで行われることが多く、ガスと
してはC3F8.CF4.CHF3 等種々報告されて
いる。(たとえば プロシーディング オン ザ ファ
ースト シンポジウム オンドライ ブロモx  (1
979) (Proceedingof  the f
irst symposium on dry−pro
cess特にCHF3ガスによるエツチングではS 1
02と他の物質(GaAs+、  SL等)とのエツチ
ング選択比が大きくとれることと、異方性エツチングが
可能であることから、多く用いられている。第1表にC
HF3ガスによるRIEでのS io2.GaAs 、
 S i 、ホトレジストのエツチング特性の比較を行
なう。
Dry etching of 5102 is performed using gas plasma, especially RI.
It is often carried out using a reactive gas called C3F8. CF4. CHF3 and other various substances have been reported. (For example, Proceedings on the First Symposium Ondry Bromo x (1
979) (Proceeding of the f.
irst symposium on dry-pro
Especially in etching with CHF3 gas, S1
It is widely used because it has a high etching selectivity between 02 and other materials (GaAs+, SL, etc.) and allows anisotropic etching. C in Table 1
S io2. in RIE with HF3 gas. GaAs,
S i , the etching characteristics of photoresists are compared.

以下余白 この表かられかるようにSiO3のエツチング選択比(
エツチングレートの比)は他の材料に比べて4.0以上
と大きい。しかし、SlO□のエツチングレートはエツ
チング中、常に一定な訳ではない。
The following margin shows the etching selection ratio of SiO3 (
The etching rate ratio) is 4.0 or more, which is large compared to other materials. However, the etching rate of SlO□ is not always constant during etching.

発明が解決しようとする問題点 第2図に5lO2のエツチング残量とエツチングレート
の関係を示す。破線は5lo2をSi上に付着したもの
、実線はGaAs上に付着したものである。Si の上
に付着したものはエツチングレートにほとんど変化はな
いが、GaAsの上のものはS 102のエツチングが
進み、残量が500Å以下になるとエツチングレートの
急激な減少がおこり、それ以上のエツチングが進行しな
くなる。逆にCHF3が分解してできたC−H−ポリマ
ーがウェハー上にたい積してしまう。すなわち、CHF
3プラズマによるエッチ、ングでは、ポリマーのたい積
と5102のエツチングは同時に進行するが、5lo2
残量が多く、エツチングによって遊離した5iFx(x
=1.2.3.4)が充分にある時はその5iFxによ
りポリマーの形成が阻止される。しかし、5102残量
が少なくなり、5iFxが少なくなれば、質量の軽いC
F!、 CHFx (x=1 、2.3 )等のイオン
ではポリマーを除去することができず、エツチングが進
行しなくなってしまう。5102を81 上に付着した
ものはS i02残量が少なくなっても、Sl基板のエ
ツチングで5iFxが作られるため、エツチングレート
の減少は発生しない。以上のように、従来法では510
2の載置基板の種類により、エツチングが異なり、特に
基板にsi 原子を含まない場合には完全なS 102
のエツチングは不可能であった。
Problems to be Solved by the Invention FIG. 2 shows the relationship between the remaining etching amount of 5 lO2 and the etching rate. The broken line shows 5lo2 deposited on Si, and the solid line shows 5lo2 deposited on GaAs. For those deposited on Si, there is almost no change in the etching rate, but for those deposited on GaAs, etching of S102 progresses, and when the remaining amount is less than 500 Å, the etching rate decreases rapidly, and further etching is difficult. will stop progressing. Conversely, C-H-polymer produced by decomposition of CHF3 accumulates on the wafer. That is, CHF
3 In plasma etching, polymer accumulation and 5102 etching proceed simultaneously, but 5lo2
There is a large amount of 5iFx (x
=1.2.3.4), the formation of the polymer is inhibited by the 5iFx. However, if the remaining amount of 5102 decreases and 5iFx decreases, the C
F! , CHFx (x=1, 2.3), etc., cannot remove the polymer, and etching does not proceed. In the case where 5102 is attached to 81, even if the remaining amount of SiO2 becomes small, 5iFx is created by etching the Sl substrate, so the etching rate does not decrease. As mentioned above, in the conventional method, 510
Etching differs depending on the type of substrate on which No. 2 is placed, and in particular, when the substrate does not contain Si atoms, complete S102
etching was impossible.

問題点を解決するための手段 上記問題点を解決するため、本発明のエツチング法では
、被エツチング物に隣接してエツチング補助材料として
Si 原子を含む材料を置・き、同時にエツチングを行
うことを特徴とする。
Means for Solving the Problems In order to solve the above problems, the etching method of the present invention includes placing a material containing Si atoms as an etching auxiliary material adjacent to the object to be etched, and performing etching at the same time. Features.

作  用 このエツチング補助材料の設置により、5lo2のエツ
チング終了直前においても、エツチング補助材料より5
iFzイオンが供給され、ポリマーの形成を阻止し、完
全なる5i02のエツチングを可能にする。
By installing this etching auxiliary material, even just before the end of 5lo2 etching, the etching auxiliary material
iFz ions are supplied to prevent polymer formation and allow complete 5i02 etching.

実施例 以下、本発明の一実施例について第1図を参照しながら
説明する。
EXAMPLE Hereinafter, an example of the present invention will be described with reference to FIG.

CHF3より成るエツチングガスをα02toxrに保
ち、カソードカップリングで13.56 MHzのRF
によりプラズマを発生させる。この時アノードーカンー
ド間にはセルフバイアス電圧がかかり、o、 1swA
−1!の電力密度の時的500vの値が得られる□ G
aAs I 上に3000人形成した51022をエツ
チングするに際し、第1図に示すように基板1全体を石
英(SiO2)板3上に配置してエツチングを行なう。
The etching gas consisting of CHF3 was kept at α02toxr and 13.56 MHz RF was applied by cathode coupling.
generates plasma. At this time, a self-bias voltage is applied between the anode and the electrode, and o, 1swA
-1! □ G
When etching 3000 pieces of 51022 formed on aAs I, the entire substrate 1 is placed on a quartz (SiO2) plate 3 as shown in FIG.

石英板3がエツチングされてできた5iFx(x=1 
、2.3.4)  イオンはGaAs上のS z022
が無くなる直前でも多量に存在するため、セルフバイア
ス電圧により加速され、ウェハー表面に衝突し、ポリマ
ーの形成を阻止する。この時51o2のエツチングレー
トは常に320A/mlnと一定で、5ooO人のSi
O□2の残量が0になるまでエツチングレートは変化せ
ず、完全な除去が行なわれる。
5iFx (x=1
, 2.3.4) Ions are S z022 on GaAs
Since it exists in a large amount even just before it disappears, it is accelerated by the self-bias voltage, collides with the wafer surface, and prevents polymer formation. At this time, the etching rate of 51o2 is always constant at 320A/mln, and the etching rate of 5ooO2 is always constant at 320A/mln.
The etching rate does not change until the remaining amount of O□2 becomes 0, and complete removal is performed.

以上のように、本実施例によれば、被エツチング物に隣
接してSt原子を構成元素とするエツチング補助材料を
置くことにより、Sio2の完全なエツチングが可能と
なる。
As described above, according to this embodiment, complete etching of Sio2 becomes possible by placing an etching auxiliary material containing St atoms as a constituent element adjacent to the object to be etched.

なお、本実施例ではエツチング補助材料として5102
を用いたが、これにとられれるものではなく、St原子
を含む材料であればよく、たとえばSi3N4.81単
体なども可能である。
In this example, 5102 was used as the etching auxiliary material.
However, it is not limited to this, and any material containing St atoms may be used, such as Si3N4.81 alone.

発明の効果 以上のように本発明は、CHF3ガスを含むプラダマ中
での9102のエツチングにおいて、被エツチング物に
隣接して、SL原子を構成元素とするエツチング補助材
料を置くことにより、8102の完全なエツチングを可
能にし、半導体の高集積プロセスへの応用に、大きな効
果が得られる。
Effects of the Invention As described above, the present invention enables complete etching of 8102 by placing an etching auxiliary material containing SL atoms as a constituent element adjacent to the object to be etched during etching of 9102 in a plasma containing CHF3 gas. It enables highly effective etching and has great effects in applications to highly integrated semiconductor processes.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例による被エツチング材料とエ
ツチング補助材料の位置関係を示した図、第2図は5i
02のエツチング残量とエツチングレートの関係図であ
る。 1・・・・・・GaAs基板、2・・・・・・S 10
2.3・・・・・・石英板(S 102 ) 0 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 第2図
FIG. 1 is a diagram showing the positional relationship between the material to be etched and the etching auxiliary material according to an embodiment of the present invention, and FIG.
FIG. 2 is a diagram showing the relationship between the remaining amount of etching and the etching rate of No. 02. 1...GaAs substrate, 2...S 10
2.3...Quartz plate (S 102) 0 Name of agent Patent attorney Toshio Nakao and 1 other person 1st
Figure 2

Claims (1)

【特許請求の範囲】[Claims] Si原子を含まない基板の上に形成された酸化シリコン
をエッチングするにあたり、前記基板に隣接してSi原
子を含む材料を配置してCHF_3ガスを含むプラズマ
ガス中でエッチングすることを特徴とする酸化シリコン
のエッチング方法。
When etching silicon oxide formed on a substrate that does not contain Si atoms, a material containing Si atoms is placed adjacent to the substrate and etching is performed in a plasma gas containing CHF_3 gas. Silicon etching method.
JP12741885A 1985-06-12 1985-06-12 Etching method of silicon oxide Expired - Lifetime JPH0646628B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12741885A JPH0646628B2 (en) 1985-06-12 1985-06-12 Etching method of silicon oxide

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12741885A JPH0646628B2 (en) 1985-06-12 1985-06-12 Etching method of silicon oxide

Publications (2)

Publication Number Publication Date
JPS61285721A true JPS61285721A (en) 1986-12-16
JPH0646628B2 JPH0646628B2 (en) 1994-06-15

Family

ID=14959471

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12741885A Expired - Lifetime JPH0646628B2 (en) 1985-06-12 1985-06-12 Etching method of silicon oxide

Country Status (1)

Country Link
JP (1) JPH0646628B2 (en)

Also Published As

Publication number Publication date
JPH0646628B2 (en) 1994-06-15

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