JPS61284796A - Display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to a display device, and particularly to a cursor display.

In general, various information processing devices such as office computers, personal computers, word processors, image editing processing systems, workstations, and CAD/CAM are equipped with display devices such as bit map displays.

The bit map display is equipped with a cursor pattern memory that stores cursor pattern data from the host side, and selectively displays multiple types of cursors by directly rewriting the data in the cursor pattern memory from the host side. I try to do that.

In this case, if the host rewrites the cursor pattern data during one display period, a flash will occur in the display. This is done within the blanking period.

By the way, some information processing apparatuses are equipped with pointing devices such as mice, and in this case, the cursor pattern often changes frequently.

Therefore, the host side must detect the vertical blanking period and rewrite the pattern every time the cursor pattern changes, which reduces system throughput and increases the response time for changing the cursor pattern. It's inconvenient.

``-'' Hiroshi This invention was made in view of the above points, and an object thereof is to shorten the display response time when changing a cursor pattern.

1. In order to achieve the above object, this invention not only instructs the host side at the timing of displaying the cursor, but also
According to the result of the instruction, successive address data for the cursor pattern memory and write address data from the host side are selected.

Hereinafter, a detailed explanation will be given based on one embodiment of the present invention.

FIG. 1 is an external perspective view showing an example of an image editing processing device as an information processing device embodying the present invention.

This information processing device uses character information as an input device.

A keyboard 1 for inputting various information such as control information.

It includes a mouse 2, which is a pointing device, and an image scanner 3, which reads original images and the like.

It also includes a CRT display 4 that displays various information as an output device, and a laser printer 5 that prints out various information.

Furthermore, the main body 6 is provided with a floppy disk device (FDD) and a hard disk device (HDD) as storage devices.

FIG. 2 is a block diagram showing the control section of this information processing device.

This control section 10 controls the entire processing device by a microcomputer system consisting of a microprocessor (MPU) 11 consisting of, for example, a 16-bit microprocessor and a main memory 12.

Note that the main memory 12 is stored in the floppy disk device 7 or the hard disk device at the time of startup. System area (resident area) that stores resident programs such as the operating system loaded from f8.

It consists of a non-resident area that stores non-resident programs, a data area, and a RAM that constitutes a working area.

The control unit 10 also includes a keyboard interface (I/F) 13 for inputting information from the keyboard 1.
, a mouse interface 14 that detects the movement direction, movement amount, and movement speed based on the X pulse and Y pulse from the mouse 2 as a pointing device, and a scanner interface for inputting read data from the image scanner 3. 15.

Furthermore, this control unit 10 includes a CRT interface 16 for controlling the CRT display 4, a printer interface 17 for controlling the printer 5, and a floppy disk device! (FDD) 7, a floppy disk controller (FDC) 18 that controls the hard disk drive (HDD)
)8 hard disk controller (HDC) that controls
It is equipped with 19.

The CRT interface 16 and CRT display 4 constitute a bit map display as a display device, and the microprocessor (MPU) 11
is the host for this bitmap display.

Furthermore, the control unit 10 also includes a communication control unit (CCU) 20 that controls transmission and reception of information with other communication terminal devices.

FIG. 3 is a block diagram showing an example of the CRT interface 16.

The CART controller (CRTC) 21
This is a circuit that controls the entire interface 16, and C
Horizontal synchronization signal H8YNC for RT display 4,
A display period signal DISP that outputs the vertical synchronization signal VSYNC and controls the output period of the video signal VIDEO.
Output.

The frame buffer 22 is a bit map memory, which is allocated as part of the memory access space of the MPU (microprocessor) 11 as a host in FIG. The display data is sequentially read out by a display timing signal from the CRTC 21.

Based on the display timing signal from the CRTC 21 and the cursor position information from the MPU (microprocessor) 11 as a host shown in FIG.
At the cursor display timing, it outputs a cursor display timing signal CD15P which becomes a wait instruction signal WAIT that instructs "wait" to the MPUI 1, and also outputs a display address (
Read address) data is output.

A multiplexer (MPX) 24 is one selection means, and M
Select write address data from the PUII to the cursor pattern memory 25 and display address data from the cursor control unit 23 in accordance with the cursor display timing signal CD15P from the cursor control unit 24,
While the cursor display timing signal CD15P is being input, the display address data from the cursor control section 23 is output.

The cursor pattern memory 25 is allocated as part of the memory access space of the MPU (microprocessor) 11 as the host in FIG.

The MPU 1i writes cursor pattern data to be displayed on the CRT display 4 at a designated write address, and the cursor control unit 23 sequentially reads out the cursor pattern data at designated display addresses (read addresses).

The shift register 26 converts the display data read from the frame buffer 22 from parallel to direct and outputs the result, and the shift register 27 converts the cursor pattern data read from the cursor pattern memory 25 from parallel to serial and outputs the result. Output. Note that the shift load signal LD and shift clock CLK necessary for parallel-to-serial conversion of the shift register 27 are input from the cursor control section 23.

The gate circuit 28 is an exclusive OR circuit or an OR circuit.
It consists of circuits, etc., and the display period signal DI from the CRTC2i.
Only while SP is being input, each shift register 26.
A video signal VIDEO, which is a composite of the serial display data and cursor pattern data from 27, is output to the CRT display 4.

Next, the operation of this embodiment configured as described above will be explained with reference to FIGS. 4 and 5.

When displaying data on the CRT display 4, the MPU 11 writes the display data to the frame buffer 22. Note that writing to the frame buffer 22 is difficult because the amount of data is large when bit map display control is being performed. For example, as shown in FIG. 4, this is performed during the vertical non-display period (vertical blanking period) TVII.

In addition, the MPU 1l stores necessary cursor pattern data in the cursor pattern memory 20 each time the pattern changes, regardless of the display timing.
Specify the write address using the write address data and write the required cursor pattern data.

On the other hand, when the display period begins, the CRTC 21 outputs a display timing signal for reading display data to the frame buffer 22, and also outputs a one display period signal DISP to the gate circuit 28 to open the gate.

As a result, the display data read out from the frame buffer 22 is converted into serial data by the shift register 26, and then sent to the video signal VIDEO via the gate circuit 28.
The image is transferred to the CRT display 4 and displayed.

Further, the cursor control unit 23 controls the cursor when the cursor display timing for displaying the cursor CA is reached, for example, as shown in FIG. It outputs the display timing signal CD15P and also outputs display address data for the cursor pattern memory 25. Note that in FIG. 5, the area surrounded by diagonal lines is the image display period.

The cursor control unit 23 also outputs a shift load signal LD and a shift clock CLK to the shift register 27 at this cursor display timing.

At this time, the multiplexer 24
While the cursor display timing signal CDl5P from .

As a result, the cursor pattern data is sequentially read from the cursor pattern memory 25, the read cursor pattern data is converted into serial data by the shift register 27, and the data is transferred to the frame buffer 2 by the gate circuit in 2 days.
The video signal VIDEO is synthesized with the display data from 2.
The image is sent to the CRT display 4 and displayed.

On the other hand, while the cursor control section 23 outputs the cursor display timing signal CDl5P.

The MPU II enters a wait state, and the MPU 1 l waits for cursor pattern data to be written into the cursor pattern memory 25 .

Therefore, when the writing timing of the MPUI 1 to the cursor pattern memory 25 conflicts with the cursor display timing, the MPUI 1 enters a wait state and the cursor display timing signal CDl5P changes to 0H#.
The wait state is released when the MPU
The cursor pattern data on the system bus is written into the cursor pattern memory 25 at the rise of the 11 write signal (active L'').

In this way, the MPU on the host side is placed in a wait state at the cursor display timing, and read address data to the cursor pattern memory and write address data from the MPU are selected depending on whether or not the cursor display timing occurs. , select only the read address at the cursor display timing and display the cursor pattern.
Access memory.

Therefore, since the host side (MPU) can write the cursor pattern into the cursor pattern memory of the display device regardless of the display timing, a decrease in system throughput is suppressed.

Furthermore, the display response time when changing the cursor pattern is shortened.

It goes without saying that the display device according to the present invention can also be used in information processing devices other than the information processing device in the above embodiment.

Toyo-Higashi As explained above, according to the present invention, display responsiveness when changing a cursor pattern is improved.

[Brief explanation of drawings]

FIG. 1 is an external perspective view showing an example of an information processing device equipped with a display device embodying the present invention. FIG. 2 is a block diagram showing the control section thereof, and FIG. 3 is a block diagram showing an example of the CRT interface. FIGS. 4 and 5 are timing charts for explaining the display control. 4...CRT display 10...Control unit 1
6...CRT interface 21...CRT controller 22...Frame buffer 23...Cursor control unit 24...Multiplexer 25...Cursor pattern memory FIG.

Claims (1)

[Claims] 1. In a display device equipped with a cursor pattern memory that stores cursor pattern data from the host side,
cursor control means for instructing the host side to enter a wait state at a cursor display timing and outputting read address data for the cursor pattern memory; 1. A display device comprising: selection means for selecting write address data from a host side and write address data from a cursor control means.