JPS61283906A - Programmable controller - Google Patents

Abstract

PURPOSE:To attain the wiring check with high efficiency just with a single operator by deciding that the signals arrives at >=2 input terminals at a time and delivering sensibly all input terminals related to the simultaneous arrival of input signals. CONSTITUTION:When a mode changeover switch is set in a wiring check mode, a CPU1 performs the wiring check processing. In this case, an operator gives the simulated operations to various switches 41 connected to the input terminals of an input interface 4 as well as to a register 42 connected to a group of input terminals according to a fixed order written on an I/O allocation table. Thus the states of those input terminals are scanned successively at a high speed and stored in an input state memory 6. If >=2 input terminals are short- circuited here, a short circuit mark is written to a history memory 8. A console panel 9 displays the input order of input terminals, the input numbers the display contents of the panel 9 are collated with those of the I/O allocation table for checking.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of the Invention) The present invention relates to a novel programmable controller with a wiring short circuit check function.

(Summary of the invention) This invention is a limit switch and a photoelectric switch.

When an input device such as a digitizer that generates a bit code is connected to each input terminal, one worker can easily check whether there is a wiring short circuit between the input device and the input terminal. .

(Prior art and its problems) Conventionally, it has been checked whether the corresponding input devices (for example, limit switches, photoelectric switches, M products, etc.) are correctly wired to each input terminal of the programmable controller 1 to roller. To do this, place a worker on each input device side and on the input terminal side of the programmable controller 1 to roller, and conduct a continuity test on each wire one by one while checking each other with a transceiver etc. was the norm.

However, such a wiring check method requires a worker to check the continuity of each wire one by one using a tester, etc., which is time consuming and inefficient. It had the following problems.

(Objective of the Invention) The object of the invention is to provide a program that eliminates the need to perform this type of wiring check, since it is a human task, and the efficiency J, <tJ'::j. [J Grammar Conn I [] - It is possible to cover the information provided by Lano.

With this release/closing (,!, Limit 1 ~ Switch, Photodens.

Connect an input device such as a digitizer that outputs a code to each input terminal (if connected, wire between the input 1sM device and the input terminal), and remove the 0 circuit in a short time by one person. The purpose is to make it possible to check.

(Description of Embodiments) FIG. 1 is a block diagram showing the hardware configuration of an embodiment device according to the present invention.

In the same figure, the CPU"l is mainly composed of a microprocessor, and is responsible for various processing operations such as various service processing, input update processing, instruction execution processing, and output 7J update processing as described later). It is under your control.

The system program memory 2 consists of ROM, and the CP
Various system programs such as various service processes executed by U1, input update vlFT processing, instruction execution processing, and output update processing are stored.

Neezab "1g" Nomunu tl J: 3+, t, tl
R(,)
' Tsubu [<A'~・1'S iM formation 31t, user '?
[1ha1 has been done.

The input interface 4 is equipped with a large number of human power terminals, and each input terminal has a switch to limit 1.

Various switches/11 corresponding to the photoelectric switch G47 or a digitizer 42 that covers the bit code are connected.

The output interface 5 includes a large number of output terminals, and a relay 51 is connected to each output terminal.

The input/output state memory 6 is composed of RAM, and the human interface 4. Outside the input/output canister corresponding to the output interface 5, an internal recessed area, counter area, timer area, etc. are provided.

The working memory 7 is composed of a RAM and is used as a sequential performance storage area for the performance in the CPU 1, and is provided with various registers to be described later.

The history memory 8 is used both as a history memory and as an input order memory according to the present invention, and is composed of a RAM.

Each address of this history memory 8 can be addressed by a memory address register MAR provided in the working memory 7.

The console panel 9 includes a high-density graphic display panel 91, such as an LCD, as shown in FIGS. 2 and 3. Numeric keypad 922 Step key 93. Group designation key 94. History key 95, mode changeover switch 96
and a power switch 97 are each movable.

As will be explained in detail later, on the graphic display panel 91, when the mode selector switch 96 is set to the read position, as shown in FIG. Short circuit marks 917 according to the present invention are displayed as a pair, or as a second
As shown in the figure, input order 913. Group No.
914° All input numbers 915 and bit codes 916 forming the group are displayed in pairs.

As shown in FIG. 4, the entire system program of this programmable controller includes various service processing 4.
0'l and input update processing 403, which is the original function of the programmable controller. User command execution processing 404. It is broadly divided into output update processing 405.

When the program starts due to power-on, etc., various registers are initialized during initial processing.

After initial setting of counters, etc. (step 400)
, execute various service processes 40' as necessary (step 401), and when the mode changeover switch 96 is set to the operating position on the console panel 9 (step 402), input update processing 403. The user command execution process 404 and the output update process 405 are repeated.

= 6− Here,! The 1t; state of each input taken in from the input/output state memory 6 is transferred to the input canister of the input/output state memory 6, and the output The history VD process is to transfer the contents of the output area of the input/output state memory 6 to the output interface 5.

Furthermore, each user command is executed by referring to the contents of the input/output canister, auxiliary relay area, counter area, etc. of the input/output status memory 6, and the result is stored in the input/output status memory 6. The main purpose is to rewrite the content of the output file, and its details are shown in Figure 8.

In the figure, when the instruction execution process is started, the instruction specified by the contents of the program counter PC is read from the program memory 3 (step 800), and on the condition that this is not an END instruction (step 801).
(Yes), execution processing corresponding to the content of the instruction is performed (step 802).

As mentioned above, the basics of this instruction execution process are
Nick 1. ．． ．． ．． ．． ．． D, AND, OF
Then, execute the operation specified by 0LJl-, 'l' IN・1, etc., for example, in the internormator method, and write the execution contents as power-no']-register P[niheself-hatred,
Furthermore, the contents of the corresponding output in the input/output state memory 6 are changed depending on the contents of the power flow register P[.

When the instruction execution process is completed, the contents of the program counter PC and the power flow register P, which are filled with 1 at that point, are memoria 1, address register N, and IAR, respectively.
The data is stored at the address in the history memory 8 specified by as shown in FIG. 12 (step 803).

The stored contents of the history memory can be sequentially displayed at two-column intervals on the graphic display panel 91 by interrupt processing accompanying the operation of the history successive key 95, as will be explained in detail later in the flowchart of FIG. It has become.

When the storage of the PC contents and the storage of the PF contents are completed, the contents of the memory address register are updated by +1 (step 804), and the jump is continued until the contents of the memory address register MAR reach the maximum value (step 805, negative). on the condition that it is not an accompanying command (step 8
07 (No), the contents of the program counter PC are updated by +1 (step 808), and the above operations are repeated.

On the other hand, when the contents of the memory address register MAR reach the maximum value (step 805), the contents of the memory address register MAR are reset to the initial value "1" (step 806), and the above-mentioned process is performed in the same manner. A series of processes is repeated.

Therefore, as shown in FIG. 12, a series of addresses in the history memory 8 contain a program counter PC for each instruction execution cycle during the continuation of the operating mode.

The contents of the power flow register PF are cyclically read and written.

Then,) ■ mode, that is, mode changeover switch 9
With 6 set to the operating position, press the history display key 95.
When is operated, the history continuation process is performed as shown at flow 9-yard in FIG.

That is, when the history continuation key 95 is operated (step 900 affirmative), the value obtained by subtracting 1 from the contents of the MAR at that time is saved as the @new history data address (step 901), and then specified in the current MAR. The contents of the address (PC and PF) are displayed on the graphic display panel 91 for 2 seconds (step 9Q2).
).

After 2 seconds have elapsed, it is confirmed that the contents of the MAR are not the latest saved data address g<Step 903 No)
, Confirm that MAR is not the maximum value (step 904)
(step 905), add +1 to the contents of MAR and remove the PC and PF of the address.
Repeat the process of displaying the contents for 2 seconds (step 9
02).

During this time, if MAR reaches its maximum value, step 904
Yes), the contents of the MAR are reset to the initial values (step 906), and the same process is repeated until the contents of the MAR reach the latest data address stored (step 903), and this pruning process is completed. 1;'4. be terminated.

This conclusion is not shown on the graphic display panel 91 or 2 seconds 1? The contents of the PC and PF will be displayed one after another, and you can confirm this. By doing so, debugging etc. can be easily performed.

Next, the wiring check process, which is the main part of the present invention, will be explained with reference to the flowcharts of FIGS. 5, 6, and 7.

When the mode selection switch 96 shown in FIG. 3 is set to the group position, the mode is read in the various service processes shown in FIG. 5 (step 50'l).
), it is determined that the mode is group setting mode (step 50).
2 (affirmative), group setting processing is then performed (steps 503, 504).

In this group setting process, the operator first presses the numeric keypad 921, step key 93. Using the group designation key 94 and dot key 98, you can easily configure group settings and check target settings by performing the following operations! ] f, zou.

Assuming now, human power W, 10 ('), H) 1,102.10
3 to 4 pits 1 to Hay',' 9Q, vessel touching 17°C
:l;'), this is defined as group N0.1.

This lift, r(3Jr1jr・), group No.
, 1, and then rlJ [O-1rOJ "・,
1 rlj rOJ rut r・Jrllr
o, 1 "2" [・J rlj rOi r3J
Each input number belonging to group N0.1 is set by operating each M1 key.

Then, in the flowchart of FIG. 5, group No. 1, input No. 'tO0, 101°10
2.103 are detected, and these are stored in the check target input 0 record area formed in a part of the history memory 8 as shown in FIG.

Roughly, specify the input check target with a predetermined code, for example 1lfr]o4. J, r105j, r107J,
Set and store the input number such as r109J. If this is done, these input numbers will also be registered as objects to be checked, as shown in FIG.

Next, when the mode selector switch 96 shown in FIGS. 2 and 3 is set to the wiring check mode, in the flowchart of FIG. 5, following the mode reading (step 501), the wiring check mode is determined (step 5).
05) and wiring check processing is executed (step 506).

In this wiring check process, the operator selects the various switches 41 such as limit switches and photoelectric switches connected to each input terminal and the digitizer 42 connected to some input terminals according to the I10 allocation table shown in FIG. Perform the simulated operations in sequence according to the specified order.

The I10 allocation table shown in FIG. 13 is commonly used for wiring this type of programmable controller, and in particular, this invention uses this ■/○ allocation table to
10NO, write the simulated operation procedure as 13 to 22, 25°23 together with the groups NO and G1, and with reference to this table, simulate the operation of each switch or digitizer in order.

Meanwhile, in the flowchart of FIG.
Initialize the contents of R (set L9 to "1" in step 601)
After storing the initial states of all L inputs in the input/output state memory (step 602) and displaying the completion of the wiring check on the graphic display panel 91 (step 603)
), the state of the name input terminals is then sequentially scanned at high speed, and the state is set to wait for the presence or absence of an input change.

That is, after resetting the search input NO and register JNR to initial values (for example, address 1) (step 604
), on the condition that the input is set as a check target (step 601), it is determined whether there is a change in the INR specified input (step 606).

It should be noted that confirmation that the input is set as a check target is made by referring to the contents of the registration area shown in FIG. 11.

In addition, when determining whether there is an input change in step 606, it is further determined whether or not the input has changed during the previous search. Care has been taken to ensure that input changes other than 1 are detected, and this prevents the same manual number from being continuously stored in the history memory, thereby reducing the publication efficiency of the memory.

Furthermore, since the determination before the input change in step 606 is determined based on the initial state of all inputs stored in the input/output state memory in step 602, the input terminal has an a contact, No matter which of the b contacts is connected, input changes can be reliably detected.

Next, if there is no change in the input specified by INR (step 606, negative), JNR is updated by +1 until the content of INR reaches the maximum value (step 610, negative), and the new INR is specified (step 607). The presence or absence of a state change in the input input is checked (step 606).

By the way, the presence or absence of a state change is determined only for inputs registered as check targets (step 6).
05 (affirmative), there is no need to specifically prohibit inputs that are not applicable, and the device can continue to operate as usual.

In this way, if JNR reaches the maximum of 110 (step 610), the contents of INR are reset to the initial value again, provided that the wiring check mode is continued (step 6111). Dafu (Step '60
4>, similarly, the state change of each input is repeatedly checked at high speed (step 606).

By the way, immediately after the INR +1 update process (step 607), the search-cycle confirmation process (step 608) and the flag reset process (step 609) are performed during the short-circuit check, which will be described later. - This is to confirm that the cycle has been completed, and will be explained in detail later.

While repeatedly checking for input changes (step 6)
06) If a state change is detected in any of the inputs as a result of the simulated operation by the operator (step 606 affirmative), the input specified by NR at that point in time is stored in the input/output state memory 6. state (step 6] 2).

This is to ensure that the next change in the input is detected.

Next, the table shown in FIG. 11 is referred to based on the contents of the INR at the time, and it is determined whether the input is registered in group B (step 613).

Here, if it is determined that the input is a group-registered input (Yes at step 613), then the group processing that has already been applied by the present applicant is performed (
step 614).

In this group processing, the group area shown in FIG. 11 is referred to, and the status of all inputs related to the group is read, and as shown in FIG. 10, this is stored in the history memory 8 specified by the memory address register MAR. Store it in the appropriate location.

On the other hand, if it is determined that the input is not a group-registered input (No in step 613), the short circuit check flag F
On the condition that LG is not “1” (step 615
Step 616), setting the flag FLG, storing input number -17 indicating the start point of the short circuit check search (step 616), and then storing the input number as shown in FIG.

is stored in the MAR designated address of the history memory (step 617).

Thereafter, the process returns to the input change check processing in steps 604 to 6co1, and waits to see if an input change is detected again while the search for I: Input No., which is stored in step 616, is completed. do.

Here, if two or more input terminals are shorted together,
While the search completes one cycle, it is sure to detect whether there is an input change again. Then, following the input change (step 6064
(step 612), input/output status memory rewrite processing (step 612)
, Probability 2 processing of non-group registration input (step 613)
After passing through, it is determined that the short circuit check flag FLG = 1 (
After storing the input number at the address designated by MAR in the history memory (step 615),
), short circuit marks are written in the corresponding addresses of the current and previous history memories (step 619).

That is, as shown in MAR=2/'4.25 in FIG. 10, input No. 109. 1 C) ↑゛l each! By adding the IΩ contact mark 1;, input NO, 109 and 10L4 or n 9aI8c\t'
Being t will be remembered. Here, the short circuit mark is provided with @ in addition to nido, and MAR = 24.25.26
Even if two sets of short circuits occur in consecutive addresses such as 0.27, this can be reliably identified. Further, if two sets of short circuit marks are used alternately, the number of short circuit sets that can be detected is not limited to the actual number.

When the wiring check process is completed in this manner, as shown in FIG. Each of these will be memorized.

In addition, before setting the short circuit check FLG to 1P,
The reason for determining the presence or absence of group registration (step 613) is that the inputs of single-pole double-throw switches, position vi, and devices also cause simultaneous changes in two or more input lines.
θ connection]...! This is to remove it from the first dye.

Next, fill in the details of the history memory and the contents.
- Set to readout 1 device. When covered, 71-1 in Figure 5
- Step 5 following mote loading in Tito-1
0]), successive mode and i11 constant are performed (step 5
071), the C4 withdrawal process shown in FIG. 7 is executed (step 508).

7j, that is, when flowcharts 1 to 7 in FIG. 7 are started, the initial value of the input order area is first set to MAR (
Step 701), and then the contents of the address specified by the MAR are read out (step 702).

Here, if it is determined that the group number is not specified by referring to the identification pins of the addresses that have been successively issued (step 7
03 negative), as shown in FIG. 3, the input order 911, input No. 912, and short circuit mark 917 are displayed on the graphic display panel 91 without indicating the order of the 1q operation.
are displayed side by side.

Therefore, based on these displays, it can be confirmed that input numbers with the same short-circuit mark are short-circuited.

On the other hand, based on the contents of the identification bits, group N
If it is determined that o is specified (Step 703)
, Detecting the group number by referring to the memory contents in FIG. 10 (step 70B>, all inputs N related to the group
Display 914 of the bonds and group numbers for which the detection of (step 709) and the detection of each input state (step 710) were performed in sequence. Display 915 of all input numbers. Display 916 of each input state, that is, the bit code. The input order is displayed 913 (step 711).

Next, when the advance key 93 is operated (step 705
(step 706), and the contents of MAR are updated by +1 (step 706).
), on the condition that the l ratio processing is continued (step 707 negative), the above operations (steps 702 to 7
06) is repeated.

As a result, as is clear from FIGS. 2 and 3, the simulated operation order is displayed in order from 1 on the graphic display panel 91, and the input number or bit code is displayed accordingly. By comparing the display with the simulated operation order on the I10 layout table shown in Figure 13, it is possible to perform this type of wiring check efficiently with -10000000000000000000000 workers. Based on the presence or absence of 917, inputs that are short-circuited can be easily confirmed.

In the above embodiment, various information is output by displaying on the graphic display panel 91, but instead of this, a scanning printer such as a wired driver 1 or the like or a voice synthesis LSI outputs a simulated operation order by voice. , input number, and bit code may of course be output.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the hardware configuration of an embodiment of the present invention, FIGS. 2 and 3 are front views of the console panel, and FIG. 4 is a schematic diagram of the entire system program of the programmable controller. Flowchart X-1 to show details of various service processes, Figure 5 1. Flowchart showing details of wiring check processing = 1., 7th
Figure 8 is a flowchart showing details of instruction execution processing, Figure 9 is a flowchart showing details of history reading processing by interrupt, and Figure 10 is a flowchart showing details of history reading processing using an interrupt. A memory map showing the state in which signal arrival order information is stored. Fig. 11 is a memory map showing the contents of the check pair @ registration area formed in a part of the history memory. Fig. 12 schematically shows the storage state of the history memory. Figure 13 is an explanatory diagram showing a state in which the order of simulated operations is written on the I10 allocation table. 1...CPU 2...System program memory 3...User program memory 4... - Input interface 5... Output interface 6... Input/output status memory 7... Working memory 8... History memory 9... Console panel 91... Graphic display panel 92...
Numeric keypad 93...Step selection key 94...Group specification key 95...History reading key 96...Mote selection switch 97...Power switch 98...Dot specification switch 911...Input order display 912 ... Input No., display 913 ... Input order display 914 ... Group No., display 915 ... Each input No. 1 display 916 ... Bit code display Fig. 2 Fig. 3 Fig. 4 Fig. 8 9 flash 0'' ゞ In -++=88 Kuzu 111 Σ °i → -to; Soup Figure 12 R

Claims (1)

[Claims] (1) Mode setting means for setting the operation mode to wiring check mode; Signal arrival detection means for detecting the arrival of signals to each input terminal; Determining that signals have arrived at two or more input terminals at the same time. A programmable controller comprising: simultaneous arrival determination means; and output means for intuitively outputting all input terminal numbers related to simultaneous arrival.