JPS59164970A - Inspecting device - Google Patents

Inspecting device

Info

Publication number
JPS59164970A
JPS59164970A JP58039950A JP3995083A JPS59164970A JP S59164970 A JPS59164970 A JP S59164970A JP 58039950 A JP58039950 A JP 58039950A JP 3995083 A JP3995083 A JP 3995083A JP S59164970 A JPS59164970 A JP S59164970A
Authority
JP
Japan
Prior art keywords
inspection
memory
procedure
fault
found
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58039950A
Other languages
Japanese (ja)
Inventor
Akira Oota
明 太田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yokogawa Electric Corp
Original Assignee
Yokogawa Hokushin Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Hokushin Electric Corp filed Critical Yokogawa Hokushin Electric Corp
Priority to JP58039950A priority Critical patent/JPS59164970A/en
Publication of JPS59164970A publication Critical patent/JPS59164970A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE:To achieve a higher efficiency of inspection work with a relatively simple construction by additionally storing a series of procedures into a memory for inspection procedures when a fault is found in a circuit of an electronic equipment. CONSTITUTION:A procedure program stored into a memory 4 is executed to change the operation mode when no fault is found and inspection is carried out in the desired procedure as specified sequentially with an operation key 2 and a display 3 by a worker. When a fault is found, a series of inspection procedures so far stored sequentially into the memory 5 are additionally stored into a program having specified inspection contents of the memory 4 as procedure program. Subsequently, identical fault can be detected easily by executing the specified series of procedure programs including that being added.

Description

【発明の詳細な説明】 本発明は、検査装置に関するものであって、詳しくは、
電子装置の回路の故障発見に有効な装置を提供するもの
である。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an inspection device, and more specifically,
The present invention provides a device that is effective in finding faults in circuits of electronic devices.

一般に、電子装置の回路の故障を発見するのにあたって
は、回路図を参照してその回路を理解している人が判断
しながら任意の手順で検査を実行したり、検査内容毎に
予め作成された手順プログラムに従って検査を実行する
ことが行われている。
Generally, when discovering a fault in the circuit of an electronic device, a person who understands the circuit refers to the circuit diagram and performs the test according to an arbitrary procedure, or a test is created in advance for each test content. The inspection is carried out according to the established procedure program.

しかし、前者の方法では、経験によるところが多く、習
熟に相当の期間を要するという欠点がある。これに対し
、後者の方法によれば、プログラムにより示される手順
に従って段階的にチェックを進めればよく、前者の方法
はどの経験は必要としないが、検査対象である電子装置
の回路のあらゆる故障を網羅するようにしてプログラム
を作成することは不可能であり、プログラムされていな
い故障についてはその都度前者の方法に従わざるをえな
かった。
However, the former method relies heavily on experience and has the disadvantage that it takes a considerable amount of time to become proficient. On the other hand, according to the latter method, the check can be carried out step by step according to the steps shown by the program. It is impossible to create a program that covers all of the problems, and the former method has to be followed each time for failures that are not programmed.

本発明は、このような従来の欠点を解決したものであっ
て、検査内容毎に予め作成された手順プログラムを格納
する第1のメモリと、任意の手順で行われる検査手順を
逐次格納する第2のメモリとを備え、第1のメモリに格
納された手順プログラムを実行して故障が見つからない
場合には故−陣が見つかるまで任意の手順で検査を実行
し、故障が見つかった段階でそれまでに第2のメモリに
逐次格納されている一連の検査手順を手順プログラムど
lyで第1のメモリに追加格納することを特徴とするも
のである。
The present invention solves these conventional drawbacks, and includes a first memory that stores procedure programs created in advance for each inspection content, and a second memory that sequentially stores inspection procedures performed in arbitrary steps. If the procedure program stored in the first memory is executed and no fault is found, the inspection is carried out in any procedure until the fault is found, and when the fault is found, it is This method is characterized in that a series of test procedures that have been sequentially stored in the second memory are additionally stored in the first memory using a procedure program.

以−ト、図面を用いて詳細に説明する。Hereinafter, a detailed explanation will be given using the drawings.

図面は、本発明の一実施例を示す要部のブロック図であ
って、1はCPU、2は操作キー、3は表示器、4は第
1のメモリ、5は第2のメモリ、6は出力端子、7は入
力端子である。
The drawing is a block diagram of essential parts showing one embodiment of the present invention, in which 1 is a CPU, 2 is an operation key, 3 is a display, 4 is a first memory, 5 is a second memory, and 6 is a The output terminal and 7 are the input terminals.

CPU1は、本発明に係る装置の動作を総括して制御り
るものである。操作キー2は、動作上−ドを切り換え!
こり、任意の手順で行う検査手順を逐次入カヅ−るため
の・もの【゛ある。表示器3は、検査手順の内容や検査
結果などを表示するものである。第1のメーしり4は、
検査内容毎に予め作成された手順プログラムを格納する
ものである。第2のメゞしり5は、任意の手順で行われ
る検査手順を逐次格納するものである。出力端子6は、
検査対象に検査信号を送出するための端子である。入力
端子アは、検査信号に応じて検査対象から送出される出
力信号が入力される端子である。
The CPU 1 controls the overall operation of the device according to the present invention. Operation key 2 switches the operational mode!
However, there is a tool for sequentially inputting inspection procedures to be performed in any order. The display 3 displays the contents of the inspection procedure, the inspection results, and the like. The first mail 4 is
It stores procedure programs created in advance for each inspection content. The second register 5 is for sequentially storing inspection procedures performed in arbitrary steps. The output terminal 6 is
This is a terminal for sending a test signal to the test target. Input terminal A is a terminal into which an output signal sent from the object to be inspected is input in response to an inspection signal.

このように構成された装置の動作について説明する。The operation of the device configured in this way will be explained.

通常の検査は、第1のメモリ4に格納されている検査内
容毎に予め作成された所定の手順プロクラムに従って行
う。検査の実ijにあたっては、読み出された検査手順
とその検査結果が表示器3に逐次表示されるので作業者
は表示器3の表示から故障個所を知ることができる。こ
のような第1のメモリ4に格納された手順プログラムを
実行して故障が見′つからない場合には動作モードを切
り換え、作業者が操作キー2と表示器3で゛逐次指定J
る任意の手順で検査を実行する。すなわら、作業者は、
指定しIC手順による検査結果を判断しながら故障が見
つかるまで任意の手順で検査を実行する。ここで、これ
ら一連の任意の手順は、運次第2のメモリ5に格納され
ている。そして、故障が見つかった段階でそれまでに第
2のメモリ5に逐次格納されている一連の検査手順を手
順プロゲラ私として第1のメモリ4の所定の検査内容プ
ログラムに追加して格納する。これにより、次回からは
、同一故障はこの新たに追加された手順ブ[1グラムを
含む所定の一連の手順プログラムを大(j′tiること
により、容易に見つけることができる。
A normal inspection is performed according to a predetermined procedure program created in advance for each inspection content stored in the first memory 4. During the actual inspection, the readout inspection procedure and the inspection results are sequentially displayed on the display 3, so that the operator can know the location of the failure from the display on the display 3. When the procedure program stored in the first memory 4 is executed and no failure is found, the operation mode is switched and the operator uses the operation keys 2 and the display 3 to
Perform the inspection using any procedure that follows. In other words, the worker
While judging the inspection results according to the specified IC procedure, the inspection is executed according to an arbitrary procedure until a failure is found. Here, these series of arbitrary procedures are stored in the memory 5 of 2 depending on luck. Then, when a failure is found, a series of inspection procedures that have been sequentially stored in the second memory 5 up to that point are added to the predetermined inspection content program in the first memory 4 as a procedure programmer and stored. As a result, from the next time onwards, the same fault can be easily found by enlarging (j'ti) a predetermined series of procedure programs including this newly added procedure program.

このような構成によれば、従来のような回路図を見なが
らの検査作業を大幅に少くすることができ、作業の能率
を高めることができる。また、比較的短期間で検査作業
を習得することもできる。
According to such a configuration, it is possible to significantly reduce the conventional inspection work while looking at a circuit diagram, and it is possible to improve work efficiency. Additionally, inspection work can be learned in a relatively short period of time.

なお、上記実施例では、第1のメモリ4と第2のメモリ
5とをそれぞれ独立させた例を示したが、これらは物理
的に独立したものでなくてもよく、共通のメモリを使い
分けるようにしてもよい。
In addition, in the above embodiment, an example was shown in which the first memory 4 and the second memory 5 were made independent, but they do not need to be physically independent, and it is possible to use a common memory separately. You can also do this.

以上説明したように、本発明によれば、比較的簡単な構
成で、作業性が優れ電子装置の回路の故障発見に有効な
検査装置が実現でき、実用上の効果は大きい。
As described above, according to the present invention, it is possible to realize an inspection device with a relatively simple configuration, excellent workability, and effective for finding faults in circuits of electronic devices, and has great practical effects.

【図面の簡単な説明】[Brief explanation of drawings]

図面は本発明の一実施例を示す要部のブロック図である
。 1・・・CPU、2・・・操作キー、3・・・表示器、
4・・・第1のメモ1ハ5・・・第2のメモ1ハロ・・
・出力端子、7・・・入力端子。
The drawing is a block diagram of essential parts showing an embodiment of the present invention. 1...CPU, 2...Operation keys, 3...Display device,
4...First memo 1 ha 5...Second memo 1 halo...
・Output terminal, 7...Input terminal.

Claims (1)

【特許請求の範囲】[Claims] 検査内容毎に予め作成された手順プログラムを格納する
第1のメモリと、任意の手順で行われる検査手順を逐次
格納する第2のメモリとを協え、第1のメモリに格納さ
れた手順プログラムを実行して故障が見つからない場合
には故障が見つかるまで任意の手順で検査を実行し、故
障が見つかった段階でそれまでに第2のメモリに逐次格
納されそいる一連の検査手順を手順プログラムとして第
1のメモリに追加格納することを特徴どする検査装置。
A first memory that stores a procedure program created in advance for each inspection content and a second memory that sequentially stores inspection procedures performed in an arbitrary procedure, and the procedure program stored in the first memory. If no fault is found, the test is performed in an arbitrary manner until the fault is found, and when a fault is found, a series of test procedures that are likely to be sequentially stored in the second memory are stored in the procedure program. An inspection device characterized in that additional storage is performed in a first memory.
JP58039950A 1983-03-10 1983-03-10 Inspecting device Pending JPS59164970A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58039950A JPS59164970A (en) 1983-03-10 1983-03-10 Inspecting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58039950A JPS59164970A (en) 1983-03-10 1983-03-10 Inspecting device

Publications (1)

Publication Number Publication Date
JPS59164970A true JPS59164970A (en) 1984-09-18

Family

ID=12567238

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58039950A Pending JPS59164970A (en) 1983-03-10 1983-03-10 Inspecting device

Country Status (1)

Country Link
JP (1) JPS59164970A (en)

Similar Documents

Publication Publication Date Title
US5253158A (en) Apparatus for supporting the development of sequence software to be used in automated equipments, and method thereof
JPS59164970A (en) Inspecting device
JPH0577143A (en) Failure diagnosis device for automated line
JP2734176B2 (en) How to create a sequence program
JPH04174059A (en) Patrol inspection system
JPS61283906A (en) Programmable controller
JPS61138184A (en) Hardware confirmation method of tester by test program
JP2001243084A (en) Power system monitor controller and storage medium with program for executing the same stored
JPH0566735U (en) Keyboard simulator
JP2772999B2 (en) Experimental system
JPS60122449A (en) Input and output controller of address variable system
JPH06250709A (en) Peripheral equipment of programmable controller
JPH03198103A (en) Terminal equipment for programmable control
JPS60193056A (en) Single chip microcomputer
JPS61223569A (en) Inspection of control substrate
KR20020057732A (en) Method for diagnosing of digital TV
JPH0581388A (en) Graphic information display function insepcting system
JPS61275640A (en) Testing machine for computer control material
JPH01237851A (en) Automatic debugging device
JP2002243803A (en) Method and device for debugging program for testing semiconductor integrated circuit and program for debugging program for testing the same
JPH06139194A (en) Information processor capable of displaying terminal use condition
JPS58181345A (en) Communication device
JPS62262107A (en) Pio simulator device for emulator
JPH0528000A (en) Controller for construction machinery
JPS63241602A (en) Sequence controller