JPS61283224A - Digital-analog converter - Google Patents

Abstract

PURPOSE:To attain high speed operation handling a high band signal by using five MOSFETs so as to constitute a unit cell and switching current path so as to turn on/off the cell. CONSTITUTION:The titled converter consists of two N-channel MOS FETs N1, N2 and two P-channel MOS FETs P1-P3. The 1st terminal of the FET N1 is connected to a ground GND, the 2nd terminal is connected to the 1st terminal of the FET N2 to form a node ND and the 2nd terminal of the FET N2 is connected to an output terminal Iout. Bias voltages Bias 1, 2 are given to the gate of the FETs N1, N2. The 1st terminal of the FET P1 is connected to a positive power supply VDD, the 2nd terminal is connected to the node ND, the 1st terminal of the FET P2 is connected to the 2nd terminal of the FET P3, the 2nd terminal is connected to the node Nd and the 1st terminal of the FET P3 is connected to the power supply VDD. Signals CCi, CFi FFj are given to gates to the FETs P1-P3 based on the inputted data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a digital/analog converter, particularly a plurality of MOS
The present invention relates to a digital/analog converter for video signals that converts high-speed digital signals into analog signals using semiconductor circuit cells of the form.

[Technical background of the invention and its problems]

Digital/analog converter (hereinafter referred to as DAC) for video signals
Technology for converting MOS-type monolithic ICs into MOS-type monolithic ICs has been rapidly developing in recent years. These conventional technologies focus on improving cost performance, and in particular, new circuit technologies are introduced to miniaturize the silicon chip, increase the signal band speed (20M87 or higher), make it glitch-free, and reduce power consumption. In addition, the device structure is MO
8-type semiconductors are becoming mainstream, and 0MO8-type semiconductors in particular have various advantages. Below is a conventional DA like this
We will briefly explain three examples of C and point out the problems with each.

Figure 8 shows the DA disclosed in U.S. Patent No. 4,393,370.
FIG. 2 is a circuit diagram of one constant current cell of C.

In order to actually operate as a DAC, these constant current cells are arranged in a matrix and operated.

A predetermined bit of the input digital signal is input to the input terminal 241.
242, and a constant current is output to output terminals 251 and 252 according to the value of this predetermined bit. Since the explanation of the operation will be omitted here, please refer to the patent publication for details. This circuit has the following problems.

(1) Counting the number of elements per unit cell, assuming that the logic gates 292 and 293 are composed of N-channel MO8FETs, seven FETs are required.

Therefore, a relatively large number of elements are required, resulting in high cost.

(2) When the switch is turned on, the NOR gate 292 acts as an amplifier, and the FET2
Since there is a feedback loop through 91, the operation tends to be oscillatory and unstable, the settling time is long, and the glitch characteristics are poor.

(3) When the FET 291 turns off, the gate voltage changes rapidly from ■ (intermediate voltage) to V (GND voltage) ON OFF, so charge feedthrough occurs through the parasitic capacitance between the gate and drain. By the output terminal 25
1. Extra current flows through 252, causing a glitch.

(4) The NOR gate 292 functions as an amplifier as described above, but the characteristics of this amplifier vary depending on the manufacturing process of the element. For this reason, the output impedance of the FET 291 as a switch also varies, and the constant current characteristics vary among the plurality of cells.

(5) Since the NOR gate 292 works as an amplifier, current consumption increases.

Figure 9 is I E E E International
l 5olidState C1rcuits Con
ference Feb,' 241983 p188
FIG. 2 is a circuit diagram of one constant current cell of the DAC disclosed in FIG. In order to actually operate as a DAC, these constant current cells are arranged in a matrix as shown in FIG. 10 and operated. The predetermined bit of the input digital signal is 5el
A constant current ■ is applied to the ect and 5elect terminals according to the value of this predetermined bit. ut is output. 10th
In the figure, each constant current cell circuit is shown within a double box. For detailed operation, please refer to the above-mentioned document. The problems with this circuit are as follows.

(1) The unit cell not shown in Figure 9 uses five FETs, but when these unit cells are arranged in a matrix as shown in Figure 10, switch elements other than this unit cell are required. In the end, the number of elements per unit cell is eight. Therefore, the cost increases.

(2) Since the gate voltage of the transistor Ml is controlled by the switch transistors MON and MOFF, it takes extra time to charge the gate capacitance of the transistor Mr, and when arranged in a matrix as shown in Figure 10, Voo V. Since the cylinder pressure of ff is transmitted to each cell via a plurality of switch elements, the cell access time becomes longer depending on the on-resistance and distribution of the switch elements. Therefore, the overall operating time is slowed down.

FIG. 11G is a block diagram of the circuit configuration of the product TML1840 manufactured by MO8INC, Inc. (Sunnyville, CA, U, S, A,). Of each bit line of the input 8-bit digital signal, the lower 4 bits B1 to B4 are given to the decoder DC1, and the higher 4 bits B5 to B8 are given to the decoder DC2, respectively.
Here, it is decoded into 15 parallel signals (15 signals are sufficient because nothing is output for the value 0), and the register R
G1. Input terminals D1 to D1 of RG2. given to. Register RG1. RG2 outputs outputs 01 to Q15 corresponding to D1 to D15 in synchronization with the synchronization clock OK. This output is for each cell CE1~CE15 and CE16~
Given to CE30. Cells CEI to CE15 include three transistors Tl1. T12. From T13, also C
E16-CE30 are three transistors T'21. T2
2. It is composed of T23. Transistor TI2. T
A bias power supply Biasl is connected to the gate of transistor T13. Bias power supply B is applied to the gate of T23.
ias2 is given. When each cell turns off the transistor Tll or T21, the transistor T
Output terminal I via I2 and T13 or T22 and T23. Supplies constant current to. Transistor T'
When T11 or T21 is turned on, a bypass current flows through this transistor and no current is output. Here, the driving ability of transistors T22 and T23 is 16 times that of transistors T12 and T13, so each cell of CE16 to CE30 is
It is possible to output a current with a weight 16 times that of E15. In this way, the output terminal I. An output analog signal corresponding to the input digital signal is obtained.

For detailed information, please refer to the TM published by Oki1MO8INC.
Please refer to the data catalog of L1840-VIDEODAC. However, this circuit has the drawback of poor glitch characteristics.

This is because the digital input is handled separately into a low bit group and a high bit group, so a large number of cells may be turned on or off at the same time in response to an increase or decrease in the ILSB of the input digital signal.

For example, consider a case where the input digital signal changes from a value of 15 to a value of 16. At a value of 15, all cells CE1 to CE15 are on and all cells CE16 to CE30 are off. However, for the value 16, all of the cells CE1 to CE15 must be turned off, and only CE16 among the cells GE16 to CE30 must be turned on. Therefore, to make an increase of only 1 LSB from the value 15 to the value 16, 16 cells would have to change their on/off states.

That is, 16 of the glitches that occur when one cell changes.
There will be twice as many glitches.

As described above, conventional DACs have various drawbacks.

[Purpose of the invention]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a digital/analog converter that can operate at high speed to handle high-band signals, has a small number of components, has extremely good glitch characteristics, and consumes little power.

[Summary of the invention]

A feature of the present invention is that the digital/analog converter is
a first MOSFET of a first channel type with an end connected to a first power supply and a first bias power supply applied to the gate;
and the first end is connected to the second end of the first MOSFET,
a first channel type second MOSFE whose second end is connected to the output terminal and whose gate is applied with a second bias power supply;
T, a third channel-type MOSFET of ff12 whose first end is connected to a second power supply and whose second end is connected to a connection point between the first MOSFET and the second MOSFET, and a second end thereof. a fourth MOSFET of the second channel type connected to the connection point of the first MOSFET and the second MOSFET;
T and a fifth MOSFET whose first end is connected to the second power supply and whose second end is connected to the first end of the fourth MOSFET.
It is configured by arranging a plurality of cells having a total of five MOSFETs, and applies a signal corresponding to the high-order bit of the input digital signal to the gates of the third and fourth MOSFETs, and applies a signal corresponding to the high-order bit of the input digital signal to the gate of the fifth MOSFET. , it provides a signal corresponding to the low-order bits of the input digital signal and outputs the converted analog signal from the output terminal, allowing high-speed operation to handle high-band signals, and having a small number of components. The glitch characteristics are extremely good and the power consumption is low.

[Embodiments of the invention]

The present invention will be described below based on illustrated embodiments. 1st
The figure is a circuit diagram of a unit cell that constitutes a DAC according to the present invention. This circuit consists of two N-channel MO8FETs N
l, N2 and three P-channel MO8FETs Pl,
P2. It consists of P3. The first of transistor N1
The end is connected to the ground point GND, and the second end is connected to the first terminal of the transistor N2.
The terminals are connected to each other to form a node ND.

Further, the second end of the transistor N2 is connected to the output terminal (2). Bias voltages BiaS1 and Bias2 are applied to the gates of transistors N1 and N2, respectively. The first end of the transistor P1 is connected to the positive power supply DO, and the second end is connected to the node ND. The first end of the transistor P2 is connected to the second end of the transistor P3, and the second end is connected to the node ND. The first end of P3 is the power supply ■. ,It is connected to the. Transistor P1. P2
．． Signals CCi, CFi, and FFj based on the respective input data are applied to the gate of P3. Each of these signals will be described later.

The operation of this cell is as follows. That is, when this cell is turned on, a constant current is output from the output terminal
It will flow through 2. On/off of the cell is determined by the voltage value of node ND.

In other words, if the sum of the voltage at the node ND and the threshold voltage of the transistor N2 is smaller than Bias2, the transistor N2 is turned on, a constant current flows, and the cell is turned on. The voltage at node ND is the voltage at transistor P1.
P2. Determined by the operation of P3. When the transistor P1 is turned on, the potential of the node ND is approximately V. D, so the cell is turned off. Also, transistors P2 and P3
Even if both are turned on, the potential of node ND is approximately ■DO
The cell then turns off. Therefore, the condition for this cell to turn on can be expressed as a logical formula as shown in formula (1>).

(Pi is off) AND ((P2 is off > 0R (P3 is off)) ・・・・・・・・・(1) Substitute this logical formula for each transistor's gate signal CC1°CFi,
Rewriting using FFj results in equation (2).

(CCi=1)AND((CFi-1)OR(FFj-
1)) ・・・・・・・・・(2
) The meaning of such logical operation will be discussed later, but let us now consider the characteristics of this cell's operation. First, the number of elements per unit cell is 5 MOSFETs.
The number of elements is smaller than that of a conventional DAC unit cell. Therefore, the cost can be reduced, and the area occupied on the silicon chip is also reduced, making it suitable for integration.

Also, when the cell is on, transistors N1 and N
When the cell is off, a constant current flows through the bus consisting of transistors N1 and P1 (or P2 and P3), so the cell is switched on/off. can perform only the operation of switching this constantly flowing constant current bus at the node ND, and can operate at high speed, and can also operate with a band signal of 20 MH7 or more. Furthermore, when the cell is turned on, a constant current is output from the transistor N2 having a high resistance, so that the transistors P1, P2, . Due to the field-through of charges based on the on/off of the gate signal of P3, no extra current is output, and glitch characteristics are also improved.

Furthermore, since there is no current consumption other than the constant current that always flows through the transistor N1, power consumption can be reduced.

Next, the overall configuration of the DAC according to the present invention will be explained using the block diagram of FIG. 2. Now, a digital signal consisting of 4 bits 81 to B4 is input, and the corresponding analog voltage is output from the output terminal I and the positive Ou [power supply ■. , is generated via a resistor R between them. In this case, 16 unit cells shown in FIG.
Arrange them on a matrix of 4. In FIG. 2, these 16 cells are represented by CEI to CE16. The input 4-bit digital signal is divided into 2 low-order bits and 2 high-order bits and given to the decoder. That is, the lower bits 81. B2
is sent to the low bit group decoder LDC, and the high order bits B3 . B4
are given to high bit group decoders 1-IDc, respectively.

The low bit group decoder LDC converts this input 2-bit data into a parallel signal and sends it to registers LRG1 to LR.
It is applied to each cell as signals FFI to FF4 via G4. In addition, the high bit group decoder HDC converts the input 2-bit data into a parallel signal and sends it to registers HRG1 to
Signals CF1-CF4 and CG1-C via HRG8
Give each cell as C4. Signal CCi in FIG.
.

CF+ and FFj are the signals CG1 to CG1 in FIG. 2, respectively.
CC4, CF1-CF4. Corresponds to FF1 to FF4.

Here, i = 1 to 4, j-1 to 4, and the value of i that each cell should take is determined from the Co1uu value at that cell position, and j
The value of is determined from the Row value at that cell position. Each register LPG1 to RG4 and HRG1 to HRG8 outputs a signal in synchronization with clock signal GK. Also, each cell has B
ias1 generation circuit BGI and Bias2 generation circuit BG
Bias voltage is supplied from 2.

Low bit group decoder LDC and high bit group decoder l
- To explain the conversion function performed by IDC, please refer to Figure 4~
Figure 6 shows the truth table. Low bit group decoder L”DC
is the 2-bit signal B1. B2 is input, and FF1 to FF4 are output based on the truth table shown in FIG. The high bit group decoder IIDC receives the 2-bit signal B3. B4
, and based on the truth table shown in Figure 5, CF2=C
Output F2 and CG1 based on the truth table shown in Figure 6.
~Output CC4. Each cell receives these signals and performs on/off operations based on the logic of equation (2). FIG. 7 shows a truth table of the on/off state of each cell for all digital input values. Here, "1" indicates that the corresponding cell is in the on state, and '0' indicates that the corresponding cell is in the off state.As the digital input value increases as shown in this table, cells CE1 to As the number of cells turned on increases toward CE16, the current flowing through the output terminal ut increases, and the voltage across the resistor R also increases.Since cell 16 is always off, in reality It becomes a dummy cell and does not need to be provided.From Figure 7, when the digital input value increases or decreases by I LSB, only one cell is always turned on or off.Therefore, large glitches occur due to increase or decrease in I LSB. No. No. 1
The cell shown in the figure can also be constructed by a circuit in which transistors with opposite channel shapes are substituted, as shown in FIG.

Finally, the characteristics of the DAC according to the present invention can be summarized as follows.

(1) Five elements per unit cell can be arranged on a matrix, saving silicon chip area and reducing costs.

(2) Only one cell is always turned on/off in response to an increase or decrease of 1LSB of the digital input, and glitches can be suppressed to a maximum of 188 minutes even with the slightest asynchrony of the switch control signal.

(3) Transistor N1 is always on and passes a constant current, and the cell is turned on/off by switching this path, which eliminates the setup time required for charging and discharging, enabling high-speed operation. .

(4) Cell control signals based on digital inputs are provided by transistors P1. P2. It only controls the on/off of the gate electrode of P3, and the transistor N that constitutes the current source
Since on/off control of the gate electrodes of transistors P1.2 is not performed, the gate electrodes of transistors P1. P2. Due to the feedthrough effect via the parasitic capacitance between the gate and drain or the gate and source of P3, no ripple is directly added to the output current. Further, since the ripple component generated at the node ND is reduced by the transistor N2 having high resistance, an excessive ripple does not occur in the output current.

(5) Since the power consumed in the study within the cell is only due to the current constantly flowing through the transistor N1, power consumption can be reduced.

(6) As mentioned above, there is no excessive ripple in the output current, and all cells can be formed within a small silicon chip area, so there is no variation in constant current characteristics for each cell, and conversion linearity is improved. Get better.

〔Effect of the invention〕

As described above, according to the present invention, in the digital/analog converter, five MOSFETs constitute a unit cell, and this cell is turned on and off by switching the current bus, so that signals in the ^band can also be handled. The number of components is small, the bridge characteristics are extremely good, and power consumption is reduced.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of a unit cell constituting a DAC according to the present invention, FIG. 2 is a block diagram of an embodiment of a DAC according to the present invention, and FIG. 3 is a circuit diagram of an embodiment of a unit cell constituting a DAC according to the present invention. Figures 4 to 7 are diagrams for explaining the operation of the DAC shown in Figure 2, and Figures 8 to 11 are diagrams for explaining the conventional DAC. FIG. Nl, N2. Pi, P2. P3. N1'. N2', N3', Pi', P2'...MOSF
E.T. CFi, CCi, FFj...Cell control signal, LDC
...Low bit group decoder, HDC...High bit group decoder, LRG1 to LRG4. HRGI~HRG8...
・Register, CE1 to CE16...Cell, BGl, B
G2...Bias voltage generation circuit, 290°291...
・MOSFET, 292.293...Logic circuit, Ml
, MD, MB, MON, MOFF...MOSFET,
DCl, DC2...decoder, RGl, RG2...
register. Applicant's agent Kiyoshi Inomata Fj Figure 1 Figure 3 Figure 4 Figure 5 Figure 6 (81) (AI) Figure 8 Figure 9 Figure 10 Figure 11

Claims (1)

[Claims] A first channel-type first MOSF whose first end is connected to a first power supply and whose gate is applied with a first bias power supply.
ET and a second MOSFET of a first channel type having a first end connected to a second end of the first MOSFET, a second end connected to an output terminal, and a second bias power supply applied to the gate. M
an OSFET, and a second channel type third MOS having a first end connected to a second power supply and a second end connected to a connection point between the first MOSFET and the second MOSFET.
FET, and a second end is connected to the first MOSFET and the second MOSFET.
a fourth MOSFET of a second channel type connected to a connection point with the MOSFET, a first end connected to a second power supply, and a second end connected to the first end of the fourth MOSFET. A total of five MOSFETs, including a fifth MOSFET
A plurality of cells having T are provided, a signal corresponding to the high-order bit of the input digital signal is applied to the gates of the third and fourth MOSFETs, and a signal corresponding to the high-order bit of the input digital signal is applied to the gate of the fifth MOSFET. A digital/analog converter characterized in that it provides a signal corresponding to a bit and outputs a converted analog signal from the output terminal.