JPS61281635A - Time division multiplexing signal separating system - Google Patents

Abstract

PURPOSE:To execute the stable writing and reading action by returning a reading clock signal frequency to an original frequency after the contracted part only returns to the original condition while the relative address of read write of the frame buffer memory receives the dummy data. CONSTITUTION:A reading clock frequency control circuit 19 receives a dummy flag detecting output DMF and the output of a frequency dividing circuit 18 when the dummy flag is detected by a dummy flag is detected by a dummy flag bit detection circuit 13, for example, from when the writing to the fist frame memory MF1 is executed, a reading clock signal frequency f0 is reduced from a frequency f1 to a frequency f3 gradually. After the difference for two frames between addresses of the writing of the first frame memory MF1 and the reading from the first frame MF1 is detected, the frequency is increased from the frequency f3 to the frequency f1 by the output of a read/write relative address detecting circuit 20. consequently, the stable separating action is executed for the drifting of the reading clock frequency control circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention is a method for converting multiplexed signals obtained by time-division multiplexing of a plurality of digital or analog information signals having different sampling frequencies or clock signal frequencies into multiplexed signals before multiplexing. This invention relates to a time division multiplex signal separation method for separating original information signals.

BACKGROUND OF THE INVENTION One of the applicants has proposed that when receiving television waves, for example from a broadcasting satellite, and retransmitting the received signal to a wired system, such as a communal viewing facility, a particularly encoded audio signal can be used. Multiple channels are transmitted in the form of encoded signals without demodulation (channels here mean the number of satellite broadcasting channels corresponding to the number of video channels).

) has been applied for a time-division multiplex transmission system suitable for time-division multiplexing and retransmission to a transmission line for one channel of communal viewing equipment (Japanese Patent Application No. 59-254220).

This time division multiplexing transmission method uses the sampling frequency or clock signal of the N channels of information signals to time division multiplex and transmit the N channels of information signals having different sampling frequencies or clock signal frequencies through one transmission path. A reference clock signal obtained by multiplying the highest frequency or higher frequency by N,
The information signals of the N channels are time-division multiplexed, and a pair of dummy flags and dummy signals are inserted into the portion where the information signal is insufficient to obtain a continuous time-division multiplexed signal.

(Object of the Invention) The present invention facilitates write control and read control of a memory unit with respect to a read clock signal whose frequency is changed when separating a time division multiplexed signal that has been time division multiplexed by the above method into the original signal. The separation operation is stable against fluctuations in the clock signal frequency of the signal before multiplexing caused by temperature and Doppler shift of the satellite, fluctuations in the clock signal frequency of the time division multiplexed signal, and drift of the readout clock signal frequency control circuit in the demultiplexing decoder. The purpose of this invention is to provide a time-division multiplexing signal separation method that can perform the following steps.

(Summary of the Invention) In the above-described time division multiplex transmission system, when dummy data is generated at intervals of X frames after multiplexing, the true information is (x-1) frames between the dummy data. Therefore, when separating the time-division multiplexed signal into the original signal, the readout clock signal frequency is time-divided in order to read out the true information (x-1) frame in the X frame period of the time-division multiplexed signal. It is necessary to control the transmission lock signal frequency to be lower than 1/N of the multiplexed transmission lock signal frequency.

Therefore, according to the method of the present invention, the write frame and read frame of the buffer memory are monitored, and the read clock signal frequency is controlled based on the difference between them.

(Structure of the Invention) In the time division multiplex signal separation method of the present invention that separates the original signal from the above-described time division multiplex signal, the amount of delay between writing and reading is divided into (α+βx) frames (a real number with α≧0, β is a value whose unit is the data transmission amount of one frame (β>O real number, X≧1 integer), and after detecting the dummy flag bit, the read clock signal frequency is Control and get a continuous pit stream.

In the initial state, the frame buffer memory is set so that the delay between the write frame and the read frame is (α+βx) frames, and the read clock signal frequency f is equal to the write clock signal frequency f.
Make it 1/N of w. When this relationship exists between image frequencies, it is also referred to as a clock non-controlled state in the following description.

When a dummy flag bit is detected, writing for β frames is temporarily stopped every time a dummy flag bit is detected. Then, the read clock signal frequency is lowered, and when the difference between the write frame and the read frame returns to β frame or more, the read clock signal frequency is returned to the original fw.
/N frequency to restore the original data before time division multiplexing.

Therefore, when the shortest period in which dummy data appears is Tim, the frequency control period T during which the read clock signal frequency is controlled is x Therefore, the clock frequency fluctuation of the information signal can be small.

(Embodiment of the Invention) Prior to detailed explanation of the embodiment, the audio subcarrier of satellite broadcasting was demodulated to QPSK, and the obtained 2,048 Mbit/
The frame structure when the pit streams of s are multiplexed into four channels using the above-described method is as shown in FIG. In other words, 16-bit frame synchronization data,
8-bit dummy information, 2032-bit A channel information signal, 8-bit dummy information, 2032-bit B channel information signal, 8-pin dummy information, 20
A unit frame sequence is formed by a 32-bit C-channel information signal, 8-bit dummy information, a 2032-bit D-channel information signal, and a 16-bit remainder focus. The dummy information before the information signal of each channel includes a dummy flag bit indicating whether the information signal of the following channel is dummy data. By checking this dummy flag bit, it is determined whether the information signal of the following channel is dummy data or not.

The present invention will be explained below using examples.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. One embodiment of the invention is α=0, β=1 and X −=
The case of l is shown as an example.

A time division multiplexed signal obtained by the above-described time division multiplexing method is manually inputted to the input terminal 10. In this embodiment, for example, 4 x 2.048 Mbtt/s in Figure 5 (a
It is assumed that the pit streams shown in -1) and (a-2) are input. In addition, Fig. 5 (a-1) and (a
-2) is shown partially overlapping, but continues in time.

This pit stream is transmitted to the frame synchronization signal detection circuit 11.
The frame synchronization signal detection circuit 11 detects the frame synchronization signal, and the clock signal reproduction circuit 12 reproduces the write clock signal WCK. Further, the pit stream and write clock signal WCK are supplied to the dummy flag bit detection circuit 13, which detects the dummy flag bit in the dummy information and determines whether the information signal of the following channel is dummy data or not. When it is determined, it outputs an inhibition instruction signal WINM that inhibits counting by a write address counter 16, which will be described later.

Frame synchronization signal, write clock signal WcK, channel selection instruction switch 14 for selecting the reception channel
The output of , and a read clock signal RCK to be described later are supplied to a system timing generation circuit 15, and the system timing generation circuit 15 generates a timing signal necessary for a decoding operation by a time division multiplex signal separation device (hereinafter also referred to as a decoder) main body M. Occur.

On the other hand, in this embodiment, four frame memories (MP l
~MF4) i-configured buffer frame memory 17-1;
Frame memory selector switches 17-2 and 17-4
, channel selection instruction switch from the pit stream to the frame memory changeover switch 17-2! The memory block 17 includes an input selection switch 17-3 that supplies an information signal of a channel selected by a memory block 17-3. Here, the one frame memory is set to a capacity that can store the amount of data sent for one frame (2032 bits in this example).

The write clock signal wcK is supplied to the write address counter 16 to generate a write address signal WA and a frame memory number signal WF corresponding to the write frame memory number.

The write address signal WA is supplied to the memory block 17 to designate a write address, and the frame memory number signal WF controls the changeover switch 17-2 to select a write frame. On the other hand, the prohibition instruction signal W4a is also supplied to the write address counter 16, and the prohibition instruction signal W4a is supplied to the write address counter 16.
The advance of the address signal is stopped by INH, and the write operation for one frame memory in the memory block 17 is prohibited.

The write clock signal WCK is also supplied to the frequency dividing circuit 18 and is frequency-divided to have a frequency (= f I) that is 1/N of the transmission lock signal frequency after time division multiplexing.

The output signal of the frequency dividing circuit 18 is supplied to the read clock frequency control circuit 19, and
9, a read clock signal RCK of frequency f0 is generated. The read clock frequency control circuit 19 outputs the dummy flag detection output DMF and the frequency dividing circuit 1 when the dummy flag is detected by the dummy flag pit detection circuit 13.
8, the read clock signal frequency f0 is gradually lowered from the frequency f to the frequency f from the time of writing to the specific frame memory, for example, the first frame memory M F + of the memory block 17 after the dummy flag is detected. Then, if a difference of two frames is detected between addresses written in the first frame memory MF and read from the first frame memory MF, the frequency is determined by the output of the read/write relative address detection circuit 20. The configuration is such that the frequency is increased from the frequency f to the frequency f.

The read clock signals R, ck are supplied to a read address counter 21, and the read address counter 21 generates a read address signal RA and a frame memory number signal RF corresponding to the read frame memory number. The read address signal RA is supplied to the memory block 17 to designate a read address, and the frame memory number signal RF controls the changeover switch 17-4 to select a read frame.

5 (a-1) and (a
A multiplexed transmission lock signal, that is, a write clock signal WCK and a frame synchronization signal are detected from the pit stream shown in -2), and frame synchronization is performed.

In addition, a timing signal from the system timing generation circuit 15 causes a delay of one frame to be provided between the write frame memory and the read frame memory when the power is turned on and when the selected channel is switched by the channel selection instruction switch 14. The changeover switches 17-2 and 17-4 are controlled so as to provide an offset of two frames, where one frame exists, between the write frame memory and the read frame memory. It is now assumed that the B channel is selected by the channel selection instruction switch 14, and that the sampling frequency or clock signal frequency of the B channel is lower than that of the other channels before multiplexing on the transmitting side.

After frame synchronization is achieved, the timing signal from the system timing generation circuit 15 causes the input selection switch 1 to
The B channel information signal is extracted from the pit stream via 7-3, and the frame memory number signal WF'
By switching the changeover switch 17-2, one channel of information signals is sequentially supplied to one frame memory, and the frame memories MF+, MFz, . . . MF, , MF, , .
− are written sequentially. If this state is shown schematically, the fifth
As shown in Figures (b-1) and (b-2). In addition,
Parts (b-1) and (b-2) of FIG. 5 are shown overlappingly, illustrating the case where dummy data is inserted every 100th B channel.

On the other hand, the write clock signal WCK is frequency-divided by N in the frequency divider circuit 18 and read clock frequency control circuit 19
A read clock signal RCK with a frequency of f+ (=fw/4) is output from.

Further, the frame changeover switch 17-4 is switched by the frame memory number signal RF, and is switched two frames behind the write frame memory and in synchronization with the read clock signal RCK, so that the frame memory MF1
, . This state is schematically shown in Figure 5 (C-1), and it is clear from comparing it with Figure 5 (b-1) that the read frame memory is Frames are behind.

However, dummy data DU is inserted in the 100th B channel. Therefore, a dummy flag bit indicating that the next information signal is dummy data is set in the dummy information immediately before the B channel in the 100th frame row, and this dummy flag bit is detected by the dummy flag bit detection circuit 13. , an inhibition instruction signal WINM is output. In Figures 4 and 5, the time when the dummy flag bit is detected is j
It is indicated by +(ta, tz). Prohibition instruction signal W1
By outputting □, writing of the B channel information signal (dummy data in this case) for -1 frame is stopped. However, reading is performed in synchronization with the read clock signal RCK having the same frequency f.

That is, during this period, the clock is not controlled. As a result, the interval between the read frame memory and the write frame memory becomes close, and when writing is resumed, the read frame memory is in a state where it is the next frame of the write frame memory. Even in this state, writing to the frame memories MF, . . . MP, . . . is performed sequentially. During this period, the read clock frequency control circuit 19 determines when the first frame memory MF is written for the first time after detecting the dummy flag bit (time jz, ty),
? The frequency f0 of the clock signal R0 read from is the frequency f.

The frequency is sequentially lowered from 1 to 3, and is temporarily maintained at frequency f. In FIG. 4, the time when the frequency of the read clock signal RCK matches the frequency f3 is 1.
．． ．． 1. It is shown by .

On the other hand, in the period in which the frequency f0 of the read clock signal RCK is decreased from the frequency f to the frequency f, and in the period in which the frequency f0 is maintained at the frequency f, after the write frame memory becomes the first frame memory MF. ,
During the period until the read frame memory becomes the first frame memory MF, the output frequency (fW/N
) and determines whether the counted value has reached a value equivalent to 2 frame memory or not.1 read/write relative address detection circuit 2
It is determined by 0. As a result of this determination, when the count value becomes a value corresponding to 2 frame memories (time t4, t
, ), the frequency of the read clock signal RCK is gradually returned from the frequency f3 to the frequency f1. In this state, the frequency f0 of the read clock signal RCK is
, (time js, j+), the frequency f
, and wait for the next dummy flag bit to be detected. 5(d-1) and (d-2) are part of the state shown in FIG. 4.
).

To explain the above operation in other words, assuming that the write frame memory is fixed, as shown in FIG. When a bit is detected, writing is stopped for one frame period. At the same time, during this period, the read clock signal is in a non-clock controlled state, and only the read frame memory approaches the write frame memory as shown by the arrow X, and when writing is performed again, , the offset between the write frame memory and the read frame memory is one frame. The state where the offset is one frame continues until the information signal is written into the selected specific frame memory (the first frame memory MP in the previous memory). Next, the frequency f0 of the read clock signal RCK decreases from the start of writing to the specific frame memory (MFI), and the offset between the write frame memory and the read frame memory becomes 2 frames sequentially as shown by arrow Y. Moving. When the offset between the write frame memory and the read frame memory becomes two frames, the frequency f0 of the read clock signal RCK increases and returns to the original frequency. Incidentally, in reality, the period t4 to tS% in FIG. 4 is t9 to t.

The interval between the write frame memory and the read frame memory is increased by an amount corresponding to the above, and the offset between the write frame memory and the read frame memory becomes a value slightly larger than one frame.

Note that here, the frequency f of the read clock signal RCK,
The reason for gradually decreasing or increasing the frequency is to avoid sudden frequency changes.
This is to reduce deterioration in sound quality, particularly deterioration due to sampling frequency fluctuations, when demodulating into an analog audio signal in the case of an M audio signal or the like. Therefore, it is desirable that the read clock signal frequency control be performed with minute frequency changes for as long as possible within the dummy data transmission period. For this purpose, the lower limit frequency f3 of the read clock signal RCK may be reduced.

Note that in FIG. 4, frequency f2 indicates the original transmission lock signal frequency before time division multiplexing on the transmitting side.

Next, an example of the read clock frequency control circuit 19 and the read/write relative address detection circuit 20 will be explained with reference to FIGS. 2 and 3.

On the read clock frequency side, the external circuit 19 is ROM 1
Divide the frequency of the write clock signal wcK by a variable frequency divider 19-2 using a frequency division ratio stored in 9-1;
The write clock signal frequency-divided by the variable frequency divider 19-2 is counted by the address counter 19-3 and sent to the ROM1.
Specify the read address of 9-4. ROM19-4
The data of the sine wave signal at each point in time when one period of the sine wave signal is divided is stored in the address counter 1.
The read data is read by address designation by the D/A converter 9-3 and converted into an analog signal by the D/A converter 19-5. Therefore, the signal output from the D/A converter 19-5 is a sine wave signal, and its frequency depends on the division ratio in the variable frequency divider 19-2, that is, the division ratio data stored in the ROM 19-1. ing.

The output of the frequency dividing circuit 18 and the output of the D/A converter 19-5 are frequency synthesized in a frequency synthesizer 19-6.

Frequency synthesis in the frequency synthesizer 19-6 converts the input into 5i
When nx, 5iny, the output signal frequency is configured to be the input signal frequency as sin (x Y), and the output signal frequency from the frequency synthesizer 19-6 is determined by the frequency division stored in the ROM 19-1. It can be changed little by little depending on the ratio data.

On the other hand, read clock frequency control logic circuit 19-
7, receives the detection output D□ of the dummy flag bit detection circuit 13 and outputs the read/write relative address detection circuit 2.
Address designation of the ROM 19-1 is started from the time when the signals W and FI, which start writing from 0 to the first frame memory MF, are received, and variable frequency division is performed. Furthermore, when the output signal frequency of the frequency synthesizer 19-6 reaches f3, R
Maintain the addressing of OM19-1 in that state.

Therefore, the frequency fo of the read clock signal RcK
is gradually decreased from frequency f to f3,
It is kept constant at frequency f3. Further, a carry output W is supplied from the read/write relative address detection circuit 20. After receiving F, addressing of the ROM 19-1 is started again, and the output signal frequency is increased little by little from frequency f3 to frequency f.

The read/write relative address detection circuit 2o receives the frame memory number signal WF output from the write address counter 16 and uses the write frame detector 20-1 to detect the first frame memory MF.

The start of writing is detected, and the flip-flop 20-3 is set based on this detection output. Further, in response to the frame memory number signal RF output from the read address counter 21, the read frame detector 20-
2 detects that reading from the first frame memory MFI has started, and this detection output resets the flip-flop 20-3. The gate of the AND gate 20-4 is controlled to be open by the Q output of the flip-flop 20-3, and the output fw/N from the frequency dividing circuit 18 is
is supplied to the force counter 20-5 for 2 frames and counted.
A carry output W6f of the frame counter 20-5 is obtained.

Therefore, the first frame memory MF is written.

The fourth test determines whether there is an offset of two frames between the writing state and the reading state.
The carry output W is checked many times between times t2 and t4 in the figure, and when an offset of two frames exists. F occurs. This carry output W. From the time point F occurs, the frequency of the read clock signal RCK is increased as described above.

In the embodiment of the present invention described above, the frequency f0 of the read clock signal Re is controlled in a trapezoidal shape, but it is not limited to a trapezoidal shape, and may be controlled in a stepwise or triangular shape. .

In the case of Twin > T, where the memory block 17 includes four frame memories and the control of the frequency f0 of the read clock signal ReK is completed after detecting the dummy flag bit and before detecting the next dummy flag bit. In this case, memory block 1
7 with a minimum of three frame memories.

Further, by further increasing the number of frame memories, the frequency control period T can be set to extend over a plurality of dummy flag bit detection periods so that x-Twin >T (here, X≧2 or more integer). For example, when the number of frame memories is "6", it is possible to control the frequency of the read clock signal Rcx in a frequency control period T such that 4XTmin>T, and it is possible to further reduce changes in the frequency of the read clock signal.

In Fig. 7(b), 4 X Tm1n > T > 3 X
The case of Twin will be schematically illustrated.

Note that FIG. 7(a) shows the timing of detection of the dummy flag bit, and FIG. 7(C) is a re-illustration of the case described above in one embodiment of the present invention for comparison.

In addition, in this case where the number of frame memories is 6'', the read clock signal frequency f is as shown in FIG.
. If the change in is made the same as in the case of FIG. 7(C), the frequency fluctuation width of the read clock signal frequency f0 can be reduced.

(Effects of the Invention) As explained above, according to the present invention, after detecting the dummy flag bit, writing to the frame buffer memory is stopped during the dummy data reception period, and then the read clock signal frequency is lowered, and the frame buffer memory When the read/write relative address returns to its original value by the amount shortened during the dummy data reception period, the read clock signal frequency is returned to the original frequency to ensure stable writing and writing.
A read operation becomes possible, and continuous data before time division multiplexing on the transmitting side can be obtained. In addition, by increasing the capacity of the frame buffer memory, the fall and rise of the read clock signal frequency can be made more gradual or the range of fluctuation can be made smaller, which reduces the quality deterioration of demodulated audio (sampling frequency fluctuation). . Furthermore, since the read clock signal frequency is controlled by the amount of delay from data writing to data reading, stable operation can be achieved against fluctuations in the four wave numbers for transmission lock signals and drifts of frequency control circuit elements.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 shows a readout clock 7 used in an embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration example of a frequency control circuit. FIG. 3 is a block diagram showing an example of the configuration of a read/write relative address detection circuit used in an embodiment of the present invention. FIG. 4 is a diagram showing frequency changes of a read clock signal in an embodiment of the present invention. FIGS. 5 and 6 are schematic diagrams showing the timing of writing to and reading from the frame memory in an embodiment of the present invention. FIG. 7 is a diagram showing changes in the frequency of the read clock signal for explaining a modification of one embodiment of the present invention. FIG. 8 is a schematic diagram showing an example of a frame configuration after time division multiplexing. 1--Frame synchronization signal detection circuit, 12--Write clock signal regeneration circuit, 13--Dummy flag bit detection circuit, 14--Channel selection instruction switch, 1
5--System timing generation circuit, 16--Write address counter, 17--Memory block, 17
-1-・Framebazza memory, 17-2.17-4
- Frame memory selection switch, 17-3 - Manual selection switch, 18- Frequency dividing circuit, 19- Read clock frequency control circuit, 19-1.19-4... ROM,
19-2-variable frequency divider, 19-3--address counter, 19-5-=D/A converter, 19-6'--frequency synthesizer, 19-7--read clock frequency control logic circuit , 20-Read/Write relative address detection circuit, 20-1~・Write frame detector, 20-2・−
・Lead frame detector, 20-total 1・Flip-flop, 20-4...AND gate, 20-5-2 frame counter, 2t-read address counter, M・
-・Time division multiplex signal separation device main unit (decoder), MF
I~MF.・−・−Frame memory.

Claims (3)

[Claims] (1) N-channel information signals having mutually different sampling frequencies or clock signal frequencies are time-division multiplexed using a reference clock signal obtained by multiplying the highest frequency or a frequency higher than the highest frequency by N among the sampling frequencies or clock signal frequencies. , a time division multiplex signal separation method that separates the time division multiplex signal into the original signal by inserting a dummy signal and a dummy flag bit in pairs in the part where the information signal is insufficient, and the information signal write frame and read frame. The amount of delay between is (α+βx) frames [real number of α≧0, x≧1
, β is a value whose unit is the amount of information transmitted in one frame, and is a real number with β>0), and when a dummy flag bit is detected, the frame buffer memory is The read clock stops writing to the frame buffer memory for β frames, then lowers the read clock signal frequency, and returns the read clock signal frequency to the original frequency when the difference between the write frame and the read frame returns to β frames or more. A time division multiplex signal separation method characterized by controlling and restoring information signals before continuous time division multiplexing. (2) Claim 1, characterized in that the difference between the write frame and the read frame at the start of returning the read clock signal frequency to the original frequency is a preset constant value equal to or larger than β frame. The time division multiplexing signal separation method described. (3) A patent characterized in that when the read clock signal frequency is lowered to a predetermined frequency and the difference between the write frame and the read frame returns to a β frame or more, the read clock signal frequency is sequentially increased from the predetermined frequency. A time division multiplex signal separation system according to claim 1 or 2.