JPS61280674A - Semiconductor device - Google Patents

Abstract

PURPOSE:To increase an operation speed and reduce a noise by laminating the N-type third semiconductor layer and the P-type fourth semiconductor layer successively. CONSTITUTION:The N-type first semiconductor layer 12, the high-purity or P-type second semiconductor layer 13 which has larger electron affinity than the first semiconductor layer 12, the N-type third semiconductor layer 14 and the P-type fourth semiconductor layer 15 are successively laminated on a semi- insulating substrate 11. A gate electrode region 17 which controls the conductivity of an electron channel 16 formed at the boundary between the first semiconductor layer 12 and the second semiconductor layer 13, a source electrode region 18 and a drain electrode region 19 are provided. In a semiconductor device with the composition like this, if the acceptor concentration of the fourth semiconductor layer 15 is much higher than the donor concentration of the third semiconductor layer 14, the built-in voltage Vbi of the third semiconductor layer 14 is larger than that in the case of a conventional Schottky gate electrode where the fourth semiconductor layer 15 is not formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device using high-speed carriers at a semiconductor heterojunction interface.

[Prior art and its problems]

Schematic cross-sectional view of a conventional field effect transistor (hereinafter referred to as FET) using heterojunctions with different electron affinities (Applied Physics Vol. 50, No. 12, 1981, 1316
page) is shown in Figure 5. In FIG. 5, 31 is a semi-insulating substrate, for example GaAs, and 32 is a first semiconductor layer with a low impurity density, for example non-doped GaAs.
A second semiconductor layer 33 has a high donor impurity density and has an electron affinity smaller than that of the first semiconductor layer 32, for example, n-type Al1.3G ao, tA.
s, 34 is a source electrode region, 35 is a gate electrode region, 36 is a drain electrode region, and 37 is a current path (hereinafter referred to as an electron channel) consisting of a two-dimensional electron layer. This semiconductor device controls the impedance of the electron channel 37 formed between the source electrode region 34 and the drain electrode region 36 by controlling the electron concentration of the electron channel 37 by the gate voltage applied to the gate electrode region 35. This is an FET based on this basic principle.

FIG. 6 shows the gate electrode region 35 of the FET shown in FIG. 5, for example, in a normally-on type thermal equilibrium state.
It shows the energy band diagram directly below . Here E
C is the energy level at the lower end of conduction, EP is the Fermi level,
qφ8 represents the height of the Schottky barrier, and ■ represents the ionized donor impurity.

In the case of this FET, as is well known, the first and second semiconductor layers 3
The two-dimensional electrons accumulated near the heterojunction interface between 2 and 33 have extremely high electron mobility because they are less affected by impurity scattering. Excellent effects can be expected.

However, in FETs with such conventional structures, it has been difficult to reduce parasitic resistance, which is important for ultra-high speed and low noise. That is, in FIG. 5, the second semiconductor layer 33
The source resistance in the electron channel 37 is R+, the source resistance due to the electron channel 37 is R2, the electron channel 37 and the second semiconductor layer 33
Assuming that the resistance in the direction perpendicular to the heterointerface is R)l, the overall source resistance R5 is approximately given by the following equation.

Normally, the group <RH is quite large in the tunneling current, and it is considered that R+ < R2 << Ru, so the formula (1
) becomes R, # R2 (2), and it can be seen that R3 is almost physically limited by the two-dimensional electron concentration. Such a result not only causes a significant decrease in mutual conductance, which indicates the performance of the FET, and impairs ultrahigh speed performance, but also significantly reduces the excellent low noise characteristic of the FET due to the generation of thermal noise due to parasitic resistance. It will cause it to deteriorate.

Furthermore, Japanese Patent Laid-Open No. 57-26472 discloses that the first semiconductor layer 32 and the second semiconductor layer 33 in FIG. A similar semiconductor device using a semiconductor layer serving as an electron blocking layer between the semiconductor layer 32 and the gate electrode 35 of FIG. 1 is shown. However, the concentration of the electron blocking layer is limited from the viewpoint of gate breakdown voltage, and it is difficult to reduce the source resistance. Moreover, the film thickness of the channel layer shown in the above-mentioned patent publication is 2.
000, a large intrinsic mutual conductance cannot be expected.

As described above, it is clear that semiconductor devices according to the prior art have drawbacks that impair ultra-high speed and low noise performance.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art and to provide a heterojunction semiconductor device that is extremely excellent in high speed and low noise.

[Structure of the invention]

A first aspect of the present invention provides a second semiconductor layer having a higher electron affinity than the first semiconductor layer and having a high purity or p-type, and a third n-type semiconductor layer on the first n-type semiconductor layer. and a p-type fourth semiconductor layer are sequentially stacked, an electrode for controlling the conductivity of an electron channel formed at the interface between the first semiconductor layer and the second semiconductor layer, and at least two ohmic conductors. It is characterized by being equipped with electrodes.

The second aspect of the present invention provides a p-type first semiconductor layer, a high-purity or n-type second semiconductor layer having a smaller sum of electron affinity and forbidden band width than the first semiconductor layer, and a p-type second semiconductor layer. A third semiconductor layer of n-type and a fourth semiconductor layer of n-type are sequentially stacked, and an electrode for controlling the conductivity of a hole channel formed at the interface between the first semiconductor layer and the second semiconductor layer. The device is characterized by having at least two ohmic electrodes.

[Principle and operation of the invention]

The principle and operation of the present invention will be explained below.

The basic principle of the present invention is to significantly reduce parasitic resistance such as source resistance by introducing the third semiconductor layer, to prevent deterioration of gate reverse breakdown voltage by introducing the fourth semiconductor layer, and to further reduce gate threshold voltage. It is based on improving voltage controllability. A detailed description will be given below with reference to the drawings.

FIG. 1(a) is a schematic structural sectional view showing an example of the basic structure of the semiconductor device of the first invention, FIG. 1(b) and (C
) are energy band diagrams below the gate electrode and between the source and gate electrodes in the thermal equilibrium state of the semiconductor device in FIG. 1(a), where EC is the energy level at the bottom of the conduction band, and EF is the Fermi level. , ■ represent ionized donor impurities.

This semiconductor device has an n-type first
and a high purity or p-type second semiconductor layer 1 that has a higher electron affinity than the first semiconductor layer 12.
3, an n-type third semiconductor layer 14, and a p-type fourth semiconductor layer 15 are sequentially stacked, and the first semiconductor layer 12
An electron channel (two-dimensional electron layer>1 (comprising a gate electrode region 17 for controlling the conductivity of li, a source electrode region 18, and a drain electrode region 19) formed at the interface between ing.

In a semiconductor device having such a structure, if the acceptor concentration of the fourth semiconductor layer 15 is sufficiently higher than the donor concentration of the third semiconductor layer 14, the built-in voltage (1) of the third semiconductor layer 14 will be equal to that of the fourth semiconductor layer 14. This is larger than in the case of a normal Schottky gate electrode in which the semiconductor layer 15 is not formed. Therefore, considering that the surface potential of the third semiconductor layer 14 is approximately equal to the height of the Schottky barrier of the gate, the width of the depletion layer of the third semiconductor layer I4 is the same as that of the source.
It can be seen that it is small under the gap between the gate electrodes [FIG. 1(C)] and becomes large under the L gate electrode [FIG. 1(b)]. the result,
For example, it is possible to completely deplete the area under the gate electrode, and leave a neutral region under the source and gate electrodes. That is, the number of conduction carriers between the source and gate electrodes can be significantly increased, and parasitic resistance can be reduced. Now, the second
In the figure (Figure 2 shows the same semiconductor device as Figure 1)
, the source resistance due to the electron channel is R4, the source resistance in the third semiconductor layer 14 is R3, and the second and third semiconductor layers 1
If the resistance in the direction perpendicular to the interface between 3 and 14 is R5, the overall source resistance R, is approximately expressed as. In a state close to homozygous, R5 0
(Ω), so it becomes . Equation (4) shows that if R5 is made sufficiently small, R5 can be significantly improved even if R4 is subject to physical constraints. In other words, the resistance RH in the direction perpendicular to the hetero interface, which was a problem in the conventional structure shown in FIG.
It turns out that it can be reduced to almost zero.

Here, the conditions required to reduce R3 are to increase the film thickness of the third semiconductor layer 14 and to increase the donor concentration, but a significant increase in film thickness reduces the mutual conductance g.
, resulting in a significant decrease in , it is essential to increase the donor concentration. The conventional FET structure shown in FIG. Since the fourth semiconductor layer 15 is provided, the reverse breakdown voltage of the gate hardly deteriorates even if the donor concentration of the third semiconductor layer 14 is increased. Since the threshold voltage (2) of the gate is determined by the p-n junction between the two, there is almost no variation in the manufacturing process, and the controllability of the threshold voltage (2) is extremely excellent. From the above results, as shown by the broken line arrow (-→-) in FIG.
It can be seen that a smooth flow of electrons with little influence from the junction interface with the semiconductor layer 14 can be realized.

Furthermore, since the donor concentration of the third semiconductor layer 14 can be increased, the thickness of the second semiconductor layer 13, which is essentially a channel layer, can be reduced, and as a result, a significant improvement in g can be realized.

Note that the third semiconductor layer 14 does not necessarily need to be completely depleted under the gate electrode in a thermal equilibrium state, and can be designed depending on the purpose of use.

The first invention described above is a case where the carrier is an electron, but when the carrier is a hole, the hole is accumulated in the valence band, which is slightly different from the case of an electron. A similar principle can be applied. The second invention relates to a case where the carrier is a hole.

FIG. 3(a) is a schematic cross-sectional view showing an example of the basic structure of a semiconductor device having a hole channel according to the present invention, and FIG. 3(b) and (C) are gates in a thermal equilibrium state, respectively. This is an energy band diagram below the electrode and between the source and gate electrodes, where E is the energy level at the top of the valence band.

represents the Fermi level, and e represents the ionized acceptor impurity.

This semiconductor device has a p-type first semiconductor layer on a semi-insulating substrate 21.
a high purity or n-type second semiconductor layer 23 that has a smaller sum of electron affinity and forbidden band width than the first semiconductor layer 22; and a p-type third semiconductor layer 24. n
The fourth semiconductor layer 25 of the mold is stacked sequentially, and the first
A gate electrode region 27 that controls the conductivity of a hole channel (two-dimensional hole layer) 26 formed at the interface between the semiconductor layer 22 and the second semiconductor layer 23, a source electrode region 28, and a drain electrode region. It is equipped with 29.

It goes without saying that the semiconductor device having the above structure basically has the same principle and operation as the case where electrons are used as carriers.

〔Example〕

An embodiment of the first invention will be described below.

This embodiment relates to a normally-on planar FET whose structure is the same as that shown in FIG. 1(a), so it will be explained using FIG. 1(a).

In this embodiment, GaAS is applied to the semi-insulating substrate 11.
The donor impurity density in the first semiconductor layer 12 is 2XIO”c
A lxG a +-, A s with a film thickness of 500A at m-'
Then, a semiconductor layer in which X gradually changes from zero to 0.3 from the substrate 11 side to the surface is formed into a non-doped second semiconductor layer 13 with an impurity density of IXIO"cm" or less and a film thickness of 500 cm. GaAs is used in the third semiconductor layer 14 with a donor impurity density of 2XIO"cm-' and a film thickness of 300cm.
GaAs with an acceptor impurity density of 3×10 19 cm −3 and a film thickness of 200 μm is applied to the fourth semiconductor layer 15 , a Schottky electrode made of AR is applied to the gate electrode region 17 , and AuGe/Ge is applied to the source electrode region 18 and drain electrode region 19 .
An ohmic electrode made of N1 is used. Furthermore, AuGe/
The depth distribution of the Ni alloy layer is not necessarily as shown in Figure 1 (
It does not have to be like a), for example, the first semiconductor layer 1
Even if it does not touch 2, it is permissible for operation.

In this example, the third and fourth
The semiconductor layers 14 and 15 are almost completely depleted under thermal equilibrium conditions. On the other hand, under the source-gate electrode, if the surface potential φ, = 0.7e■, approximately 100 portions of the third semiconductor layer 14 remain as a neutral region; Electron mobility μm”4
000c/■·sec, the sheet resistance that provides R3 in equation (4) is approximately 780Ω/sec. In addition, the areal density n of two-dimensional electrons is lXl012cm-2, and the mobility μ
. =8000 cd/■.SeC, the sheet resistance giving R1 is also about 780 Ω/hole, and the overall source resistance Rs is significantly small, half of R1, about 390 Ω/hole. Furthermore, the overall thickness between the fourth semiconductor layer 15 and the two-dimensional electronic layer 16 is approximately 80.0 mm, which is significantly reduced compared to the conventional one, and as a result, the mutual conductance g becomes extremely large.

In this embodiment, a normally-on planar FET is shown, but a normally-off FET can also be realized by reducing the thickness and impurity density of the third semiconductor layer 14, for example. Furthermore, it is clear that a high-performance device with even smaller R3 can be realized by further forming an n-type semiconductor layer in a region other than the gate electrode 17 by, for example, vapor phase growth.

Next, another embodiment of the first invention will be described. FIG. 4 shows a schematic cross-sectional view of the structure of the FET in this example. In principle, the same components as those shown in FIG. 1(a) are designated by the same numbers as in FIG. 1(a).

In this embodiment, a buffer layer is provided between the semi-insulating substrate 11 and the first semiconductor layer 12 in the embodiment shown in FIG. 41, the first semiconductor layer 12 and the second semiconductor layer 13
A spacer layer 42 is provided between the two to mainly increase the mobility of two-dimensional electrons. In this embodiment, a semi-insulating substrate 11 is made of GaAs, and a buffer layer 4 is made of GaAs.
1, the impurity density is less than lXl0"cm-3 and the film thickness is 0.5
μm of A 1xG a +-xA S, where X is the substrate 11
A semiconductor layer whose thickness gradually changes from zero to 0.3 from the side to the surface is formed into the first semiconductor layer 12 by A1..
3G a,..., As, and a film thickness of 50A with an impurity density of iXIO" cm-3 or less and
, 3Ga0. , As, the second semiconductor layer 13 is made of undoped GaAs with an impurity density of IXIO"am-' or less and a film thickness of 500 nm, and the third semiconductor layer 14 is made of undoped GaAs with a donor impurity density of 2X10"cm-3 and a film thickness of 400 people A (lvG
a, yA s, a semiconductor layer in which Y gradually changes from zero to 0.5 from the substrate 11 side toward the surface is formed into the fourth semiconductor layer 15 with an acceptor impurity density of 3X10"cm-
3 with a film thickness of 20OA! o, 5Gao, sAs, a Schottky electrode made of W in the gate electrode region 17, and AuGe/A in the source electrode region 18 and drain electrode region 19.
Ohmic electrodes are used.

The main feature of this embodiment is that Aj! has a large forbidden band width in order to further reduce the overall source resistance R1. o,5Gao,
5AS is used for the fourth semiconductor layer 15, and the third semiconductor layer 1
It is at the point where the film thickness of 4 is expanded. Furthermore, for the purpose of improving surface stability, the p-type semiconductor layer 15 is left extremely thin in areas other than the gate electrode within the range of surface depletion.

Note that the introduction of the buffer layer 41 and the spacer layer 42 is already known and is not the essence of this embodiment, so a detailed explanation will be omitted.

In this embodiment, as in the previous embodiment, the overall source resistance R
In addition to reducing s and improving mutual conductance g,
It has the advantage of increasing logic amplitude.

Next, an embodiment of the second invention using a hole channel will be described. The schematic structural cross-sectional view of the FET in this example is the same as that in FIG. 3(a), so the description will be made using FIG. 3(a). In this embodiment, the semi-insulating substrate 2
1 is made of GaAs, and the first semiconductor layer 22 is made of Ga with an acceptor impurity density of 2Xl018cm'' and a film thickness of 600A.
As is added to the second semiconductor layer 23 at an impurity density of lXl0''
cm-' or less to a film thickness of 500, the third
The acceptor impurity density in the semiconductor layer 24 of 2XIOI
The fourth semiconductor layer 2 is made of Ge with a film thickness of 400 nm and 8 am-'.
Ge with a donor impurity density of 2Xl019crn-3 and a film thickness of 200 nm is used for the gate electrode region 27, a Schottky electrode made of AA is used for the gate electrode region 27, and ohmic electrodes made of AuZn are used for the source electrode region 28 and the drain electrode region 29.

In this example as well, the source resistance R5s was reduced to less than half, and the mutual conductance g1 was also significantly improved, as in the case where the conduction carriers were electrons. Note that the planar type, the type in which an n-type semiconductor layer is formed in the area other than the gate electrode region 27, the normally-on type, the normally-off type, and other types due to the shape design are all similar to the case where the conductive carriers are electrons. It is clear that this will be achieved.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to realize a high-performance ultra-high frequency, ultra-high speed, ultra-low noise FET that makes full use of the high speed properties of two-dimensional conduction carriers and has a large mutual conductance due to a significant reduction in parasitic resistance. Furthermore, since the design flexibility and controllability of the threshold voltage are extremely excellent, the productivity is also excellent. Furthermore, the present invention provides excellent semiconductor devices such as high-performance and highly reliable microwave and millimeter wave devices and ultra-high-speed ICs, and the effects of the present invention are extremely large.

[Brief explanation of drawings]

1 and 2 are diagrams for explaining the first invention; FIG. 3 is a diagram for explaining the second invention; and FIG. 4 is an embodiment of the first invention. 5 is a schematic cross-sectional view of a semiconductor device; FIG. 5 is a schematic cross-sectional view showing the structure of an example of a conventional semiconductor device; FIG. 6 is an energy band diagram of the semiconductor device of FIG. 11, 21... Semi-insulating substrate, 12, 22... First semiconductor layer, 13, 23... Second semiconductor layer, 14, 24... Third semiconductor device 15, 25. ...Fourth semiconductor layer, 16...Electron channels 17, 27...Gate electrode regions 18, 28...Source electrode regions 19, 29...Drain electrode region 41...Buffer layer 42...・Spacer layer agent Yoshiyuki Iwasa (a) (b) (c) 1st floor 2nd fm Figure 4 (a) (b) (C) Figure 3

Claims (2)

[Claims] (1) On an n-type first semiconductor layer, a high-purity or p-type second semiconductor layer that has a higher electron affinity than the first semiconductor layer, an n-type third semiconductor layer, and a p-type second semiconductor layer. A fourth semiconductor layer is stacked in sequence, and includes an electrode for controlling the conductivity of an electron channel formed at the interface between the first semiconductor layer and the second semiconductor layer, and at least two ohmic electrodes. A semiconductor device characterized by: (2) On the p-type first semiconductor layer, the sum of electron affinity and forbidden band width is smaller than that of the first semiconductor layer, and high purity or n
A type second semiconductor layer, a p-type third semiconductor layer, and an n-type fourth semiconductor layer are sequentially stacked and formed at the interface between the first semiconductor layer and the second semiconductor layer. A semiconductor device comprising an electrode for controlling conductivity of a hole channel and at least two ohmic electrodes.