JPS61280609A - Hetero junction structure - Google Patents

Hetero junction structure

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Publication number
JPS61280609A
JPS61280609A JP12222285A JP12222285A JPS61280609A JP S61280609 A JPS61280609 A JP S61280609A JP 12222285 A JP12222285 A JP 12222285A JP 12222285 A JP12222285 A JP 12222285A JP S61280609 A JPS61280609 A JP S61280609A
Authority
JP
Japan
Prior art keywords
crystal
group
gaas
intermediate layer
doped
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12222285A
Other languages
Japanese (ja)
Inventor
Toru Suzuki
徹 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP12222285A priority Critical patent/JPS61280609A/en
Publication of JPS61280609A publication Critical patent/JPS61280609A/en
Pending legal-status Critical Current

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  • Junction Field-Effect Transistors (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To facilitate the formation of single crystal of groups III-V and II-VI with excellent quantity IV crystal such as Si, Ge, etc. by a method wherein a specific intermediate layer is laid in a hetero junction structure bonding IV semiconductor crystal to III-V or II-VI compound semiconductor crystal. CONSTITUTION:An intermediate layer of Ge doped with V group atom As in a thin film at high concentration is provided between Ge in V group crystal and GaAs in III-V semiconductor crystal. Numerous As atoms are exposed to the surface of intermediate layer doped with As at high concentration to be chemically bonded to Ge atoms. In such a state, when GaAs begins to grow, the probability of Ga adhesion to As exposed to the surface being overwhelmingly superior to that of As, the growing probability of one domain out of two possible domains overwhilmingly exceeds the other growing probability. Resultantly two opposing domains can be prevented from growing here and there, thus facilitating the formation of GaAs comprising single crystal.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は半導体工業分野に用いられるヘテロ接合構造に
関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a heterojunction structure used in the semiconductor industry.

(従来技術とその問題点) 一般に、m−viおよび■−■族の化合物半導体は、電
子デバイス、光デバイス用結晶として広い用途をもつ材
料でおるが、これらは■−■族またan−■sバルク結
晶の形で、あるいはそれらの間のエピタキシャル結晶の
形で使用されるのが常であった。しかし、これらがIV
族結晶の上に成長することが可能であれば、例えはシリ
コンまたはゲルマニウム結晶上に高品質のGaAs又は
InPなどのm−vi半導体を成長することができるな
らば、電子デバイス、光デバイスの設計上大きな自由度
があるため大変有利である。しかし、用途の広い(10
0)シリコy(Si)上にGa A s等を成長しよう
とするとき、(100)表面に露出した8i原子の上に
Gaがつくか、Aaがつくかは自由であるため、こうし
て形成されたGaAs (100)はアンタイドメイン
を所々にもつ結晶となシ、その電気工学的特性は必ずし
も良好ではなかった。
(Prior art and its problems) In general, m-vi and ■-■ group compound semiconductors are materials that have a wide range of uses as crystals for electronic devices and optical devices; It was customary to use them in the form of bulk crystals or in the form of epitaxial crystals between them. However, these are IV
If it is possible to grow high-quality m-vi semiconductors such as GaAs or InP on silicon or germanium crystals, the design of electronic and optical devices can be improved. It is very advantageous because it has a large degree of freedom. However, it is versatile (10
0) When trying to grow GaAs etc. on silicon y (Si), it is free to choose whether Ga or Aa is attached to the 8i atoms exposed on the (100) surface, so GaAs (100) is a crystal with untied domains here and there, and its electrical properties are not necessarily good.

第2図は従来の■族半導体結晶の上に■−■−■導体結
晶を直接成長させた場合の構造図の一例である。この場
合、■族結晶としてゲルマニウム(Ge)、  l1l
−V族半導体として砒化ガリウム(GaAs)i例とし
て採用した。このようにGe上にGaAs結晶が成長す
る場合、Ge上KAs がまず付着する場合とGaがま
ず付着する場合とがめる。
FIG. 2 is an example of a structural diagram when a ■-■-■ conductor crystal is directly grown on a conventional group II semiconductor crystal. In this case, germanium (Ge), l1l as the group ■ crystal
- Gallium arsenide (GaAs) was used as an example of the V group semiconductor. When a GaAs crystal grows on Ge in this way, two cases are distinguished: KAs on Ge is deposited first, and Ga is deposited first.

このGe上に単結晶GaAsを成長する場合はGa又は
A8めどちらかが一方的にGe単結晶の表面に化学結合
される必要がおるが、Ge上へはGaもAsも有限の結
合確率を有するために単一の相においてGaAsが成長
することができない。勿論、アンタイフェーズの領域の
数が多くなる程、相と相との界面の過剰エネルギが蓄積
されるので、領域の数が無制限に増えるのを押える機構
は働くが、しかし、零にすることはできない。
When growing single-crystal GaAs on this Ge, either Ga or A8 needs to be unilaterally chemically bonded to the surface of the Ge single crystal, but both Ga and As have a finite bonding probability on Ge. GaAs cannot be grown in a single phase because of this. Of course, as the number of untied phase regions increases, excess energy is accumulated at the interface between phases, so a mechanism works to prevent the number of regions from increasing indefinitely, but it is impossible to reduce the number to zero. Can not.

その結果、一定の大きさを有する領域に分割される。こ
の図では、相■、相■と示した領域、が互いにアンタイ
フェーズの領域を構成している。この相領域の境界は一
種の結晶欠陥であるため、デバイス等をこの結晶で製作
する際の障害となる。
As a result, it is divided into regions having a certain size. In this figure, the regions indicated by phase (2) and phase (2) constitute mutually anti-phase regions. The boundary between these phase regions is a type of crystal defect, and thus becomes an obstacle when manufacturing devices and the like using this crystal.

(発明の目的) 本発明の目的は、このようなアンタイドメイン構造をも
たない完全な単結晶の■−V族またはII−■族結晶を
■族結晶上に成長させることを可能とするペテロ結合構
造を提供することにある。
(Objective of the Invention) The object of the present invention is to develop Peter's method that makes it possible to grow a complete single-crystal ■-V group or II-■ group crystal without such an untied domain structure on a group ■ crystal. The purpose is to provide a bonding structure.

(発明の構成) 本発明の構成は、■族半導体結晶と■−V族またはII
−■族の化合物半導体結晶とを結合するペテロ接合構造
において、これら両結晶界面に、前記■辰結晶と前記■
−■族結高結晶へテロ接合さ中間層として設け、前記■
族結晶と前記n−■s結晶とかへテロ接合される場合は
、高濃度の■または■族がドーピングされた単原子層以
上の膜厚の薄膜■族結晶を中間層として設けることを特
徴とする。
(Structure of the Invention) The structure of the present invention includes a group ■ semiconductor crystal and a group ■-V or II group semiconductor crystal.
- In a petrojunction structure that combines a compound semiconductor crystal of the ■group, the above-mentioned
−■ Group high crystal heterojunction is provided as an intermediate layer, and the above-mentioned ■
When a heterojunction is made between a group crystal and the n-■s crystal, a thin film group III crystal doped with a high concentration of a group III or group III and having a thickness of at least a monoatomic layer is provided as an intermediate layer. do.

(実施例) 次に本発明を図面によシ詳細に説明する。(Example) Next, the present invention will be explained in detail with reference to the drawings.

第1図は本発明の一実施例の接合構造図である。FIG. 1 is a diagram of a joining structure of an embodiment of the present invention.

本実施例は、■族結晶のGeとm−va半導体結晶のG
aAsとの間に、薄膜の■族原子Ast高濃度にドープ
し九Geの中間層がはさまっていることを示している。
In this example, Ge of the group II crystal and G of the m-va semiconductor crystal are used.
It is shown that an intermediate layer of 9Ge doped with a thin film of Ast, a group II atom, is sandwiched between the aAs and the aAs.

この中間層の中には高濃度のAsがドープされているた
めに、中間層表面では多数のAsが露出しており、かつ
このAsはGe原子と化学結合している。この状態でG
 a A sの成長を開始すれば、表面に顔を出してい
るAsにはGaが付着する確率が、Asが付着する確率
より圧倒的に大きいため、2つの可能なドメインのうち
の一方のドメインの成長確率が圧倒的に大きく  4な
る。従って、2つの相反対のドメインが所々に成長する
ことは阻害され、単一の相よシなるGaAsの形成が容
易になる。
Since this intermediate layer is doped with a high concentration of As, a large amount of As is exposed on the surface of the intermediate layer, and this As is chemically bonded to Ge atoms. G in this state
Once the growth of a A s starts, the probability that Ga will adhere to As exposed on the surface is overwhelmingly greater than the probability that As will adhere, so one of the two possible domains The growth probability is overwhelmingly large, reaching 4. Therefore, the growth of two opposing domains here and there is inhibited and the formation of a single coherent GaAs is facilitated.

なお、本発明は、第1図におけるAs  ドーグ−の代
シにGaドープGeを用いても同様の原理から単一のG
aAs層を得ることができる。また、GaAsの代シに
InP、 AsドープGeの代りにPドープまたはIn
ドープGe、を用いればGe上のInPの単結晶の存在
が可能となる。この場合、l−V族は混晶でめりてもか
まわず、又■−■族の代シに■−■族の単結晶成長も同
様の原理によって可能である。
Note that the present invention can be applied to a single G based on the same principle even if Ga-doped Ge is used instead of As in FIG.
An aAs layer can be obtained. In addition, InP is used instead of GaAs, and P-doped or In is used instead of As-doped Ge.
Doped Ge allows the existence of a single crystal of InP on Ge. In this case, the l-V group may be a mixed crystal, and the single crystal growth of the ■-■ group instead of the ■-■ group is also possible based on the same principle.

(発明の効果) 以上説明したように、本発明によれば、Si。(Effect of the invention) As explained above, according to the present invention, Si.

Ge等の■族結晶上に、QaAs、  Ink、  I
nAs。
On group II crystals such as Ge, QaAs, Ink, I
nAs.

GaInP、  Zn5e、  ZnS、  Zn5e
8等の■−■族。
GaInP, Zn5e, ZnS, Zn5e
8th class ■-■ group.

■−■族の良質単結晶を容易に形成することが可能とな
る。
It becomes possible to easily form a high-quality single crystal of the ■-■ group.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例のへテロ接合構造の原子配列
図で、Ge単結晶上にAsを高濃度にドープしたGeの
薄膜中間層を介して単結晶GaAsが存在する様子を示
し、第2図は従来のへテロ接合構造の一例の原子配列図
で、Ge単結晶上で2相に分離したGaAsを示してい
る。
FIG. 1 is an atomic arrangement diagram of a heterojunction structure according to an embodiment of the present invention, showing the presence of single crystal GaAs on a Ge single crystal via a thin interlayer of Ge doped with a high concentration of As. , FIG. 2 is an atomic arrangement diagram of an example of a conventional heterojunction structure, showing GaAs separated into two phases on a Ge single crystal.

Claims (1)

【特許請求の範囲】[Claims] IV族半導体結晶とIII−V族またはII−VI族の化合物半
導体結晶とを結合するヘテロ接合構造において、これら
両結晶界面に、前記IV族結晶と前記III−V族結晶とが
ヘテロ接合される場合は、高濃度のIII族またはV族元
素がドーピングされた単原子層以上の膜厚の薄膜IV族結
晶を中間層として設け、前記IV族結晶と前記II−VI族結
晶とがヘテロ接合される場合は、高濃度のIIまたはVI族
がドーピングされた単原子層以上の膜厚の薄膜IV族結晶
を中間層として設けることを特徴とするヘテロ接合構造
In a heterojunction structure that combines a group IV semiconductor crystal and a group III-V or group II-VI compound semiconductor crystal, the group IV crystal and the group III-V crystal are heterojunctioned at the interface between these two crystals. In this case, a thin film group IV crystal doped with a group III or V element at a high concentration and having a thickness of at least a monoatomic layer is provided as an intermediate layer, and the group IV crystal and the group II-VI crystal are heterojunctioned. In this case, a heterojunction structure characterized in that a thin film group IV crystal doped with a high concentration of group II or VI and having a thickness of at least a monoatomic layer is provided as an intermediate layer.
JP12222285A 1985-06-05 1985-06-05 Hetero junction structure Pending JPS61280609A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12222285A JPS61280609A (en) 1985-06-05 1985-06-05 Hetero junction structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12222285A JPS61280609A (en) 1985-06-05 1985-06-05 Hetero junction structure

Publications (1)

Publication Number Publication Date
JPS61280609A true JPS61280609A (en) 1986-12-11

Family

ID=14830577

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12222285A Pending JPS61280609A (en) 1985-06-05 1985-06-05 Hetero junction structure

Country Status (1)

Country Link
JP (1) JPS61280609A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5981986A (en) * 1992-05-11 1999-11-09 Fujitsu Limited Semiconductor device having a heterojunction

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5981986A (en) * 1992-05-11 1999-11-09 Fujitsu Limited Semiconductor device having a heterojunction

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