JPS6127936B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a time division multiplex communication system suitable for communication with a spacecraft. In particular, the present invention relates to a multiplex signal demodulation method at the receiving end, in which data signals having various highest frequency components are transmitted using a time division multiplex transmission method at a sampling rate corresponding to each signal.

In general, in telemeter communication for spacecraft, etc., there are many types of data to be transmitted, and each data has various frequency components.
Time division multiplex communication is performed in which the sampling period is changed depending on the highest frequency component of each data. For example, when the PCM method is used as the modulation method, each data is sampled and then AD converted.
Data is transmitted in the form of words made up of multiple bits, and the words that transmit each data are generally divided into unit intervals on the time axis called frames or subframes at appropriate intervals according to the sampling period. Placed. In this case, a frame is made up of a certain number of words, and a subframe is made up of a certain number of frames. Data with the highest frequency content is transmitted using multiple words per frame (so-called supercommunication), and data with average frequency content is transmitted using one word per frame. (normal communication). Data with a frequency response slower than the average is 1
The data that is transmitted by a specific word in several frames with a specific time interval in a subframe, and has the slowest frequency response, is transmitted once per subframe by a specific word in a specific frame. Transmitted (sub-communication).

In a demodulator that extracts and outputs each data from a time division multiplexed data signal having a multiplexed format that combines several types of communication methods as necessary, bit synchronization, frame synchronization, subframe synchronization, etc. By this means, timing address signals such as a word count signal and a frame count signal are obtained from the input data series, and a channel identification signal synchronized with each data channel in the input data series is synthesized using these signals. Conventionally, the following two methods are well known as methods for synthesizing these signals.
In other words, the first method is suitable for a device that demodulates only a data series having a specific multiplexed format, and uses a specific logic circuit with fixed wiring (hardwired logic) to determine the timing address. This method uses a signal as input and performs logical operations to obtain a channel identification signal. The second method is suitable for versatile devices that can use the same demodulator even if the multiplexing format of the input data series changes. This method logically combines various timing signals obtained from the signals as necessary to obtain a channel identification signal.

However, with these methods, the equipment becomes complicated when the number of data channels to be multiplexed in the input data series, the number of data channels to be extracted and output from among them is large, or when the multiplexing format is complex. There are drawbacks to it. In other words, in the first method, the configuration of the logic circuit becomes enormous.
In the second method, mechanical contacts are used for signal connections, and electrical connections are made manually using patch cords, etc., so the structure and operation of the patch board are complicated, and a large amount of space is required for signal connections. The problem was that the wiring would get confused.

The present invention aims to eliminate these drawbacks and to provide a system that is compact, easy to operate, and has the flexibility to change logic.

The present invention uses, as an input signal, a signal in which a plurality of data signals are temporally multiplexed and transmitted at a sampling interval corresponding to the highest frequency component of each data signal, and the timing obtained from the data sequence of the input signal. a channel identification signal generation circuit that receives an address signal as input and outputs an identification signal for each data channel synchronized with the input data series; and means for extracting desired data from the input data series in synchronization with the identification signal of the data channel. In the multiplexed signal demodulation method, the channel identification signal generation circuit includes a storage circuit that receives the timing address signal as an address input, and the address of the storage circuit contains the identification signal of the data channel corresponding to the value of the address. is characterized in that it is encoded and stored in advance.

Preferably, the storage circuit is a read-only memory.

In the present invention, a timing address signal of an input data series is input to a channel identification signal generation circuit, and an encoded channel identification signal (for example, a channel number expressed in pure binary code) is synchronized with the input data series. If an electrical storage device is provided with an output function and the multiplexing format of the input data series is not constant, either the electrical storage device is replaced or multiple electrical storage devices are used by switching. Alternatively, the stored contents of the electrical storage device can be rewritten and used.

Next, a multiple signal demodulation method according to the present invention will be explained with reference to the drawings.

FIG. 1 is a configuration diagram of an embodiment of the present invention. 1st
In the figure, 1 indicates the input terminal, from which the time division multiplexed data series a based on the PCM method is transmitted to the bit synchronization circuit 2.
is input. Here, clock signals b and c synchronized with the input data series are extracted by means such as a known phase-locked loop and supplied to the frame and subframe synchronization circuit 3 together with the signal-adjusted input data series d. The frame and subframe synchronization circuit 3 performs serial-to-parallel conversion on the signal-adjusted input data series d, and outputs it as parallel PCM data e and strobe pulses, as well as internal frame synchronization pattern detection circuit and frame identification signal detection circuit. A word counter and a frame counter coupled to these outputs respectively extract a word count signal g and a frame count signal h synchronized with the PCM data e and supply them to the channel identification signal generation circuit 4 as timing address signals.

FIG. 2 shows an operational waveform diagram of each part of this embodiment circuit. 2A to 2I are waveform diagrams of points indicated by corresponding symbols marked with an x mark in FIG. 1.

The configuration of the channel identification signal generation circuit 4 differs depending on the multiplexing format of the input data series.
Here, an example of a multiplexing format is shown in FIG. In FIG. 3, the numbers in the figure indicate data channel numbers, data channels 1 to 23 are normal communication channels, 24 is a super communication channel having a sampling rate four times that of normal communication, and 25 to 23 are normal communication channels.
32 is a sub-community channel having a sampling rate of 1/8 of that of normal communication, and 33 to 64 are sub-community channels having a sampling rate of 1/32 of that of normal communication.

Setting up the example in Figure 3, circuit 4 has 0 to 31
A 5-bit word count signal g for counting word numbers from 0 to 31 and a 5-bit frame count signal h for counting frame numbers from 0 to 31 are supplied.

Among the traditional methods of channel identification signal generation,
For example, in a method using a patch board and a patch cord, signals g and h are first decoded and then parallel
Words W ₀ to W ₃₁ of PCM data e, frames F ₀ to
A channel identification signal was obtained by obtaining 32 word pulses and 32 frame pulses synchronized with _F31 , and combining these 64 types of signals using a logic circuit on a patch board. In this case, for example, for the normal communication channel, the word pulse can be used as it is as the channel identification signal, but for channels 25 to 32, the signal of the logical sum of each of the four types of frame pulses,
Requires the operation of ANDing W ₁₀ word pulses. As described above, the system using a patch board and a patch cord generally has the disadvantage that the structure of the channel identification signal is quite complicated, and therefore a large amount of space is required for signal connection. If a similar connection were to be made using fixed hard-wired logic, the circuit configuration for this part would be enormous.

The feature of the present invention lies in the use of a fixed memory device (read-only memory device) integrated into the circuit 4. Its configuration is shown in FIG. Figure 4 shows the channel identification signal generation circuit 4.
It is a figure showing an example of composition. word count signal g
is used as an address signal for the fixed storage circuit 5. As shown in FIG. 5, the fixed memory circuit 5 stores 8-bit channel identification signals corresponding to the values 0 to 31 of the word count signal.
The most significant bit of each channel identification signal stores 1 if the channel using the corresponding word is a sub-communication channel, and stores 0 if it is a super or normal communication channel. ing. In the lower 7 bits of each channel identification signal, if the corresponding channel is a super or normal communication channel, the channel number is stored as is, and if it is a sub-communication channel, the word identification code (in this example In this case, W ₁₀ is 0 and W ₂₀ is 1). The rightmost column in the figure shows the decimal representation of the lower seven bits of each channel identification signal.

In this way, the output of the fixed memory circuit 5 is
A channel identification signal corresponding to the value of the input word count signal g is output, and its lower 7 bits j are supplied to the signal input A of the signal switching circuit 6. On the other hand, the most significant bit k of the signal is connected to the signal selection input A' of the circuit 6 via the inverter 7. The signal switching circuit 6 outputs the input signal i of the input A as the final channel identification signal i when the signal k is 0, that is, in the case of a super or normal communication channel. i is the channel number of the channel that uses the corresponding word. i changes in synchronization with word count signal g, but in parallel with signal g
Since it is synchronized with the PCM data e, the channel number of the data e can be known using the signal i.

On the other hand, when the signal k is 1, that is, in the case of a sub-communication channel, it is necessary to identify the frame number in addition to the word number. fixed memory circuits 8 and 9 are used. That is, when signal k is 1, the least significant bit output l of signal j at that time is 0.
In the case of , that is, in the case of W ₁₀ , the output m of the gate 10 becomes 1, the fixed memory circuit 8 becomes active, and its output is supplied to the signal input B of the circuit 6 . Similarly, when the signal l is 1, that is, when W ₂₀ , the output n of the gate 11 becomes 1, and the output of the fixed storage circuit 9 is supplied to the signal input B of the circuit 6. A frame count signal h is used as an address signal for fixed memory circuits 8 and 9, and the memory contents of each are channels corresponding to frame numbers at _W10 and _W20 , as shown in FIGS. 6 and 7. The number is memorized.

On the other hand, the signal k is the signal selection input of the signal switching circuit 6.
Since it is connected to B', when its value is 1, the input signal P is finally output as the channel identification signal i. At this time, the content of signal i is the channel number of the channel using the corresponding word and frame.

In this way, the 7 encoded channel identification signals for all data channels are
A parallel bit signal i of bits can be obtained.

Parallel PCM data e, strobe pulse f, and channel identification signal i, which are the outputs of the circuit in Figure 1.
FIG. 8 shows an example of a circuit that extracts data from an arbitrary data channel using the .

FIG. 8 is a diagram showing an example of the configuration of the data extraction circuit. The channel identification signal i is input to a comparator circuit 13 capable of comparing parallel bits simultaneously, and is compared with the other parallel bit input q. The input q indicates the channel number of the data to be extracted, and this is arbitrarily set by manual operation of the digital switch 14, such as a thumbwheel switch, according to the operator's request. When the contents of i (channel identification signal) match the set signal q, a match signal r is outputted from the circuit 13 to the gate 15, and the signal s, which is ANDed with the strobe signal f, is used in parallel in the latch circuit 16. PCM data e is sampled,
Data t of the desired channel is extracted.

Note that the gate 10 in FIG. 4 of this embodiment,
11 is not essentially necessary due to the operation of the circuit 6, and the signal l is used as the signal n, and its inversion is used as the signal m.
It can also be used as

In this embodiment, a case has been described in which the multiplexing format of the input data series is shown in FIG. Just change the content. Therefore, by making the fixed memory circuits 5, 8, and 9 replaceable, it is possible to demodulate a data series having an arbitrary multiplexed format by replacing the fixed memory circuits. However, if the number of words in one frame used as a sub-communication channel exceeds two words, it is necessary to increase the number of fixed memory circuits 8 and 9 according to the number of words.

Note that if the multiplexing format of the input data series is not constant, instead of replacing the fixed memory circuit, it is also possible to switch and use a plurality of fixed memory circuits. There is also a method that does not use a fixed memory circuit, but uses a memory circuit whose memory contents can be electrically rewritten, and rewrites the memory contents as necessary.

Furthermore, although the above example describes the case where the modulation method is the PCM method, the present invention can be similarly implemented in the case of a time division multiplex data transmission method using other methods such as PDM or PAM.

As explained below, in the present invention, since a memory circuit is used in the channel identification signal generation circuit, the device configuration is extremely simplified and the device can be made compact. In addition, if there is a change in the signal arrangement logic in the transmitter, by replacing this memory circuit or changing its contents,
It has the advantage of being flexible. Furthermore, when a read-only memory is used for the storage circuit, there are advantages such as it is easy to write the memory contents, it is possible to create a large number of them at low cost, and the memory contents are not lost. .

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of an embodiment of the present invention. Figure 2 is a time chart of its operation. FIG. 3 shows an example of the configuration of input data multiplexing format. FIG. 4 is a configuration example diagram of a channel identification signal generation circuit. FIG. 5 shows an example of the memory contents of the fixed memory circuit 5. Figure 6 shows fixed memory circuit 8.
Example of memory contents. FIG. 7 shows an example of the memory contents of the fixed memory circuit 9. FIG. 8 is a configuration example diagram of a data extraction circuit connected to the output of the circuit of FIG. 1. 1...Input terminal, 2...Bit synchronization circuit, 3...
...Frame and subframe synchronization circuit, 4...
Channel identification signal generation circuit, 5, 8, 9... Fixed memory circuit, 6... Switching circuit, 13... Coincidence detection circuit, 16... Latch circuit.

Claims (1)

[Claims] 1. A plurality of data signals are arranged at appropriate time intervals in a frame composed of a plurality of words and a subframe composed of a plurality of said frames according to the highest frequency component of each data signal. A channel identification system that uses a time division multiplexed data transmission signal to be transmitted as an input signal, receives word and frame timing address signals obtained from a data sequence of this input signal, and outputs an identification signal for each data channel synchronized with the input data sequence. In a multiple signal demodulation method comprising a signal generation circuit and means for extracting desired data from an input data series in synchronization with an identification signal of the data channel, the channel identification signal generation circuit addresses the word timing address signal. a data channel identification signal for a data signal which is input and is arranged at least once within one frame; and a data channel identification signal for a data signal arranged at one of N specific word timings within one frame and arranged at least once within one subframe. a first storage circuit that stores an intra-frame word timing identification signal in the form of encoded identification data for a data signal that is transmitted and is not transmitted for each frame; 2nd to N+1th storage circuits storing data channel identification signals of at least one data signal arranged in a subframe and not transmitted for each frame in the form of encoded identification data; the first in-frame word timing identification signal obtained from a storage circuit;
A multiplex signal demodulation system comprising: a switching circuit that switches the outputs of the N+1th storage circuits to output the channel identification signal generation circuits.