JPS61278939A - Data processor - Google Patents

Abstract

PURPOSE:To generate a new data packet at a high speed and to prevent a dead lock due to the wrong exchange of data by detecting data to be paired when data is transmitted on a transmission line, and regulating a pair of data detecting section to the transmission line. CONSTITUTION:Plural data packet pair detecting sections 28a1-28an and 34a are set to the 1st and 2nd data transmission lines 28 and 34. Identification data from identification data detecting circuits 521-52n relating to the transmission line 28 are given to corresponding comparator circuits 561-56n. On the other hand, idenfitication data from the identification data detecting circuit 54 of the transmission line 34 is given to the comparator circuits 561-56n in common. When the comparator circuits 561-56n detect the coincidence of the identification data, they give a control signal to a new data packet generating circuit 50, which generates one new data packet from two coincident data packets.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a data processing device, and particularly to a data processing device that generates one new data packet from two data packets, such as a firing section of a data-driven data processing device. The present invention relates to a data processing device.

(Prior Art) Neumann type data processing apparatuses have drawbacks such as slow speed and difficulty in parallel processing due to sequential processing. Therefore, recently, data driven type (data flow type) data processing apparatuses have been proposed and implemented. An example of such a data-driven data processing device is disclosed, for example, in Nikkei Electronics, published on April 9, 1980, pages 181 to 218.

In conventional systems, in order to detect firing, data packets from the data bus are stored in a matching memory, and the identifier or identification data of the data packet stored in the matching memory is searched to find the data packet of the other party to be paired. I'm trying to find it.

(Problems to be Solved by the Invention) In the conventional system, it takes a very long time to store data in the queue memory and search for identification data therein, and as a result, the speed of the entire data processing device decreases. It was getting late.

Therefore, the main object of the present invention is to provide a data processing device that can more quickly find a data packet to be paired with.

(Means for Solving the Problems) Simply put, the present invention provides first and second data transmission paths for transmitting data packets including identification data and configured using shift registers; Single or multiple data packet pair detection sections defined in one of the first and second data transmission paths; a plurality of data packet pair detection sections defined in the other of the first and second data transmission paths; identification data detection means for detecting identification data included in the data packet from the packet pair detection section; The data processing apparatus includes pair discrimination means for discriminating a data packet to become a data packet, and new data packet generation means for generating one new data packet from two data packets discriminated by the pair discrimination means.

(Operation) Data packets are transmitted individually on the first data transmission path and the second data transmission path. The identification data detection means extracts identification data from the data packets transmitted on each data transmission path from the data packet pair detection section. The pair determining means compares both pieces of identification data thus extracted and finds data packets that are to be paired and are being transmitted on the two data transmission paths. When a data packet of the other party to be paired is detected, the data packet is provided to the new data and packet generation means from the first and second data transmission paths. The new data packet generation means processes the two supplied data packets in a predetermined manner to generate one new data packet. This new data packet is then brought to the main data transmission path for later processing, such as arithmetic processing.

(Effects of the Invention) According to the present invention, data packets to be paired are detected while data is being transmitted on the first and second data transmission paths, so that it is possible to detect data packets that are to be a pair while data is being transmitted on the first and second data transmission paths. In comparison, new data packets can be generated faster. Therefore, the data processing apparatus as a whole can be configured as a faster system.

Furthermore, in the present invention, since a plurality of data packet pair detection sections are defined in at least one of the first and second data transmission paths, "deadlock" caused by miscommunication on the two data transmission paths can be avoided. ” never occurs.

Furthermore, if a self-propelled shift register is used as such a data transmission path, it will be easy to connect it to the asynchronous main data transmission path, making its benefits even more effective when configured as a data-driven data processing device. It can be demonstrated.

The above objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

(Embodiment) FIG. 1 is a conceptual system diagram showing an example of a data processing device in which the present invention can be implemented. The system 10 includes an asynchronous delay line ring 12 as a data transmission path, a data packet to be processed is provided to the asynchronous delay line ring 12 through a merging section 14, and the processed data is sent to a branching section 16. is output through. The data packet provided from the merging section 14 passes through the asynchronous delay line ring 12, is branched by the branching section 18, and is provided to the function storage section 20. The data read from the function storage section 20 is given to the asynchronous delay line ring 12 again through the merging section 22.

For example, as shown in FIG. 3(A), the data packet given from the function storage unit 20 includes a header HD and a plurality of data words DW following the header HD.

~DWn included. The header HD includes a processing code PC and a control code CC, and the processing code PC includes a code indicating a packet structure and a code indicating processing contents. As a code indicating the packet structure, an order code indicating that it is a header or the last data word is given, for example, by the 17th and 16th two bits. Codes that indicate processing content are especially called F codes, such as r+J, r-J, ・
...or used to specify the type of processing, such as data replacement or insertion. The control code CC includes logical information such as physical optical information, node information resulting from the program structure, and color information.

The data packets as described above transmitted by the asynchronous delay line ring 12 are provided to the first loop-shaped data transmission line 2 constituting the firing section 27, for example, through the branching section 24 and the merging section 26. Different data packets are taken into a second loop-shaped data transmission path 34 forming the firing section 27 through different branching sections 30 and merging sections 32 . The data packets given to the first and second loop-shaped data transmission paths 2 and 34 are transmitted through the respective loops in opposite directions to each other, and are sent to the ignition detection section 36 that constitutes the ignition section 27 together with these transmission paths. Given. The firing detection unit 36 compares the control codes included in each data packet between the two data packets, thereby distinguishing between the data packet existing on the first loop-shaped data transmission path 28 and the second data packet. It is determined whether or not the data packets 7) existing on the loop-shaped data transmission path 34 form a pair, and one new data packet is generated based on the specific data packet detected as a data packet pair. The new data packet generated in this manner is placed, for example, on the first loop-shaped data transmission path 28 and is brought onto the asynchronous delay line ring 12 again through the branching section 38 and the merging section 40.

A new data packet transferred on the asynchronous delay line ring 12 is transferred to the arithmetic processing unit 44 through the branching unit 42, for example.
and then processes the data to be processed contained in that data packet according to the processing code contained in the header of that data packet. The data processed by the arithmetic processing unit 44 is merged into the asynchronous delay line ring 12 again through the merge unit 46. This processing result is given again to the function storage section 20 or output through the branching section 16.

Note that the system 10 is further provided with a control command processing section and a color management section.

This invention is suitable as the firing section 27 of the system 10 shown in FIG. However, the present invention is generally applicable to all data processing devices that need to find the data of the other party to form a pair and generate one piece of new data from that pair of data. Please point this out in advance.

FIG. 2 is a schematic block diagram illustrating the principle of a data processing device that is the background of this invention. The first and second loop-shaped data transmission lines 28 and 34 are constituted by shift registers, preferably self-running shift registers.

As will be explained in detail later, a self-propelled shift register is capable of independently and simultaneously pushing in and popping out data, and furthermore, it is capable of pushing in and popping out data while the next register is empty. It is automatically shifted to the output direction under the condition that
Therefore, in this and the following examples, these first
The second data transmission paths 28 and 34 are configured as asynchronous data transmission paths.

Note that the two data transmission paths 28 and 34 have been described as forming a loop in the system of FIG.

However, these do not necessarily have to be loop-shaped. However, as will be explained in detail later, it is desirable that at least one of them, and more preferably both, be configured as a loop.

Such first and second data transmission paths 28 and 3
4, data packets having the structure shown in FIG. 3 are transmitted in the same direction or in mutually opposite directions. What is shown in FIG. 3(A) is one data word per data word.
Figure 3 (B
) indicates that one data word includes a plurality of (two in this example) data to be processed.

A firing detection section 36 is connected to the first and second data transmission paths 28 and 34, and the firing detection section 36 includes a data packet pair detection circuit 48 and a new data packet generation circuit 50. Data packet pair detection circuit 48
is the control code CC (FIG. 3) from the data packet transmitted through the first and second data transmission paths 28 and 34.
By extracting the identification data included in the data packet and comparing the two extracted identification data, the data packet of the other party to be paired is detected. When a data packet pair is detected, this data packet pair detection circuit 4
8, a signal is given to the new data packet generation circuit 50. Accordingly, the new data packet generation circuit 50
Then, each data packet containing the detected identification data is captured. Then, one new data packet is generated from the two captured data packets and output.

To explain in more detail, as shown in FIG.
Data word 1 with the configuration shown in A) - DP 1 and DP
2 are transmitted on the first and second data transmission paths 28 and 34, respectively. From these data transmission paths 28 and 34, identification data iD1 and I
Data including D2 is provided to data packet pair detection circuit 48. Then, these two identification data IDI and ID2 are extracted and compared. If these two identification data IDI and ID2 have a certain relationship, for example, if the node information in the program structure matches, then this fact is detected by the comparison circuit. In this way, the data packet pair detection circuit 48 identifies data packets DPI and DP2 as being paired with each other. New data packet generation circuit 5
0, the data packet DP thus identified
I and DP2 are read from the first and second data transmission paths 28 and 34, respectively, to generate one new data packet DP. This new data packet has a data packet structure as shown in FIG. 3(A).

Further, as shown in FIG. 5, data packets DPI and DP2 having structures as shown in FIG. 3(B) are transmitted on the first and second data transmission paths 28 and 34, respectively. shall be.

In the same way as in Figure 4, the data packet DPI
and identification data IDI and ID2 included in DP2
are compared and when a certain relationship is detected, the new data packet generation circuit 50 generates a new data packet as shown in FIG.
one data packet DP is generated. In the example shown in FIG. 5, the new data transmission line DP has the structure shown in FIG. 3(B).

FIG. 6 is a block diagram showing an example of a data processing device that is the background of the present invention. In this example, both the first and second data transmission lines 28 and 34 are configured as self-running shift registers. The self-running shift register constituting the first data transmission path 2 includes a plurality of cascade-connected parallel data buffers B, ~B, and C elements ( Co
incident Element) Contains Cl=C5. Similarly, the self-running shift register constituting the second data transmission path 34 includes cascade-connected parallel data buffers Bll-B15 and C elements C11'''CI5 corresponding to each of them.

Here, with reference to FIGS. 7 and 8, the C element constituting the asynchronous self-propelled shift register will be described. C
Element C includes six terminals T, ~T6, and terminal T receives a signal TRI (Transfer
In ) is given, and from terminal T2, a signal A KO (Acknowledge Ou
t) is output. A signal T RO (Transfer 0ut) is output from the terminal T3 to the C element in the previous stage, and a signal AK I from the C element in the previous stage is output from the terminal T4.
(Acknowledgement In) is given. Signal TPO is further given to its corresponding parallel data buffer as a transfer command signal. And signal A
KI is given as an empty signal of the preceding stage parallel data buffer.

Note that a reset signal RESET is applied to the terminal T5, and a stop signal 5TOP is applied to the terminal T6.

In the circuit shown in FIG. 7, the reset signal RE is sent from the terminal T5.
When SET is given, it is inverted by an inverter and this signal is given to four Nant gates G,,
G4. The outputs of G, and G14 both become high level. Nant Gate c,, c4. The outputs of c, I and G, 4 are at high level, so the outputs of Nant gates G3 and GI3 that receive them are both at low level. Nando game) G4's high level output is signal AK
0, and is given as a signal AKI from the terminal T2 to the C element in the subsequent stage. This is a signal representing the empty state of the preceding stage parallel data valve. At this time, if data has not yet arrived, the signal TRI to the terminal T is at a low level. Reset signal RESET to terminal T5
When is released, the output of the inverter becomes high level, while the signal AK' from NAND gate CI4 is also high level, and this state is the initial state.

In the initial state, therefore, the two inputs of each of the Nant gates Gl and G, I are at high level, and one input of OR gates G2 and G12 is at high level. Therefore, 2 of Nant Gate G3 and G13
Both inputs are at high level, so the outputs of these Nant gates G3 and GI3 are both at low level. That is, signal TR' and terminal T3
The signal TRO from is at low level. Nantes Gate G
The inputs of gates G4 and G14 are at low level, high level, and high level, respectively, and the outputs of these Nant gates G4 and G14 are at high level, respectively.

When the data is transferred and the signal TRI applied to the terminal T1 from the C element in the subsequent stage changes to high level as shown in FIG.

All three inputs of will be high level, and its output will be low level. Then, the output of the Nant gate G3, that is, the signal TR' becomes high level as shown in FIG. 8, and the output of the Nant gate G4 becomes low level. When the signal TR' becomes high level, the output of Nant gate C++ becomes low level, and the output T of Nant gate G13 becomes low level.
PO becomes high level, and output AK' of Nant gate G14 becomes low level. The outputs of Nands gates G4 and G,4 are returned to the inputs of Nands gates G3 and G13, respectively, and the outputs of these Nands games 1-G3 and G,3 are locked at a high level.

In this way, as shown in FIG. 8, the signal AKO from the terminal T2 becomes low level, indicating that data has been transferred to the corresponding parallel data buffer of this C element C. In other words, in that state, data transfer is no longer possible. The fact that no Uke is to be added is communicated to the subsequent C element. Also, Nantes Gate G1
3 is at high level, and from terminal T3, the previous stage C
A high level signal TPO is applied to the element. This high level signal TPO is given as a transfer command to the corresponding parallel data buffer, and the data in the parallel data buffer is sent to the previous stage.

When the signal AKO becomes low level, the signal TRI becomes low level as shown in FIG. 8, and therefore the output TR' of the Nant gate Gl returns to high level. Furthermore, as described above, by changing the output AK' of the Nando gate G14 to low level, the output AKO of the Nando gate G4 returns to high level, and the output T of the Nando gate G3 changes to the low level.
R' returns to low level.

When the signal AKO from the C element in the previous stage, that is, the signal AKI applied from the terminal T4, changes from high level to low level as shown in FIG. 8, that is, when the empty space in the parallel data buffer in the previous stage is extracted, Or Gate G, 2
Since the input of the OR gate GI2 is at a low level and the signal TR' is also at a low level, the output of the OR gate GI2 is also at a low level. At this time, Nant Gate G3 and G.

Since the outputs of gates 3 and 4 are both at high level, the outputs of gates G and 4 change to high level. Therefore,
The input of the Nant gate GI3 becomes high level, and the output of this Nant gate GI3 changes to low level. In this way, the state returns to the same state as the initial state.

If the signal AKO from the previous stage C element, that is, the signal AKI from the terminal T4, remains at a low level, that is, if the parallel data buffer corresponding to the previous stage C element is not yet empty, then the Nant gate Nant gate G8 ．． Since one input of the terminal T remains at a low level, even if the signal TRI from the terminal T is given as a high level and the signal TR' changes to a high level, the Nant gate G remains at a low level.
11 does not operate and the signal TPO does not go high, thereby refusing to accept data from the subsequent stage, and therefore data cannot be transferred to the parallel data buffer corresponding to this C element in this state.

In addition, a stop signal 5TOP is applied to this C element C from the terminal T6.
is given, the high level signal is the OR gate G
5 to the Nantes gate G13. Therefore, this Nando game-1-G.

3 becomes low level, and in this state, the signal TPO from terminal T3 becomes low level, is transmitted to the C element in the previous stage, and data transfer is stopped.In this way, as shown in FIG. Parallel data buffers B1 to B5 and C
Elements C1-C5 and parallel data buffers Bll-B!
5 and C elements C51 to CI5 constitute asynchronous self-running shift registers of data transmission lines 28 and 34, respectively.

Returning to FIG. 6, the respective parallel data buffers B4 constituting the first and second data transmission paths 28 and 34
and BI4 to parallel data buffers B3 and B13
A data line extends from the data transmission path to the data packet pair detection circuit 48, and each data is supplied from the data line to identification data detection circuits 52 and 54 included in the data packet pair detection circuit 48. The identification data detection circuits 52 and 54
Now, the identification data is extracted from the header of the data packet (FIG. 3) and provided to the comparison circuit 56. The comparison circuit 56 compares the two pieces of identification data provided and determines whether they match or do not match. When the comparison circuit 56 detects a match between the two identification data, the data packet to be paired is determined, and a control signal notifying this is sent to the new data packet generation circuit 50.
given to.

A transmission path extends from the transmission path from the parallel data buffers B3 and BI3 that constitute the first and second data transmission paths 28 and 34 to the parallel data buffers B2 and BI2 to the new data packet generation circuit 50. Based on the match signal or control signal from the comparison circuit 56, the new data packet generation circuit 50 takes in the determined specific data packet to be a pair through the data packet line. Then, in the new data packet generation circuit 50,
The two data packets are combined to create one new data packet. The new data packet D generated by the new data packet generation circuit 50 in this way
P (FIG. 4 or 5) is transmitted through the new data packet line to the main data transmission path 12 for later processing.
(FIG. 1) and sent to other processing circuits.

In the example shown in FIG. 6, identification data detection circuits 52 and 5
4 detects the identification data within a relatively short time that the data packets are sent from parallel data buffers B4 and BI4 to parallel data buffers B3 and B13, and comparator circuit 5
6, you have to compare it within that time. However, depending on the data transmission speed in the data transmission lines 28 and 34, a detection error may occur.

Therefore, it is conceivable to adopt a configuration in which the identification data detection circuits 52 and 54 hold the identification data of the data packet for a certain period of time.

FIG. 9 is a schematic block diagram showing another example of a data processing device which is the background of the present invention. The firing section 27 in this example is
As in the previous example of FIG. 6, it includes an firing detection section 36 connected to the first and second data transmission paths 28 and 34. The firing detection section 36 includes a data packet pair detection circuit 48 and a new data packet generation circuit 50. The data packet pair detection circuit 48 is connected to the first data transmission line 28.
an identification data detection circuit 52 for detecting identification data from a data packet transmitted on the second data transmission path 34; and an identification data detection circuit 54 for detecting identification data from a data packet transmitted on the second data transmission path 34. including. The two identification data detected in this way are sent to the comparison circuit 56.
compared by. The comparison circuit 56 provides a control signal to the new data packet generation circuit 50 when the two match or are in a certain relationship.

In this example, the first and second data transmission paths 28 and 3
4, data packet pair detection sections 28a and 34a of a certain length are defined, and the same identification data is taken out from these data packet pair detection sections 28a and 34a for a relatively long time, thereby making comparison in the comparison circuit 56 easier. It was designed to be.

FIG. 10 is a block diagram showing an example of an identification data detection circuit applicable to FIG. 9. In FIG. 10, only the first identification data detection circuit 52 that detects identification data from the first data transmission path 28 is illustrated and explained, but the second
It should be noted that the identification data detection circuit 54 that detects identification data from the data transmission line 34 has a similar configuration.

The free-running shift registers constituting the first data transmission line 28 are cascade-connected parallel data buffers B. l l
BO""B4 and their associated C elements C8I l
Contains coxCa. Each parallel data buffer B. The header signal line H3L is connected to the 17th bit of I+B O"" B4, and the tail signal line TSL is connected to the 16th bit. Parallel data buffers BOI and B.

Header signal line H3L++ between 0 and 0 is applied to the D terminal of D flip-flop 60, and header signal line H3L between parallel data buffers B3 and B4.

2 is the D flip-flop 64 through the OR gate 62.
is given to the D input of The tail signal line TSL, □ between the parallel data buffers B3 and B4 is an OR gate 66
is given to D input on 0797170716 through.

The clock input of the D flip-flop 60 is C.
Signal TPO from element C8I is provided. An OR gate 70 is connected to the reset input of this D flip-flop 60.
An initial reset signal is applied through the circuit, and its own output Q is applied thereto. The output Q of D flip-flop 60 is further provided through OR gates 72 and 74 to the respective reset inputs of D flip-flops 64 and 68, along with an initial reset signal.

The output Q of the D flip-flop 64 is applied to the other input of the above-mentioned OR gate 62 whose output is applied to its own D input, and also applied to one input of the AND gate 76 . The output Q of the D flip-flop 68 is given to the other input of this AND gate 76, and this output Q is
Further, the output thereof is applied to the other input of the OR gate 66, which is applied to its own D input.

A header signal line is taken out from the transmission line from parallel data buffer B4 to parallel data buffer B3, and this header signal line is applied to register 78. This register 7
The output Q of the aforementioned D flip-flop 64 is applied to the clock input of 8. The output of this register 78 is then used as the detected identification data by the comparator circuit 56 (sixth
Figure) is given.

In the initial state, a high level initial reset signal is applied. This initial reset signal is the OR gate 70.
Through 72 and 74, D flip-flop 60.6
In response, these D flip-flops 60, 64 and 68 are reset, and their respective data Q becomes low level. This state is the initial state.

When the parallel data buffer B3 is detected to be empty by the associated C element C3, data packets begin to be transferred from the parallel data buffer B4 to this parallel data buffer B3. When a data packet, that is, its header is transferred from the parallel data buffer B4 to the parallel data buffer B3, the header signal lines H3L and □ between them become high level. With the start of such data packet transfer, the signal TPO from the C element C3 changes from low level to high level. Then, this high level signal is given to each clock input of the D flip-flop 64 and 68, and the high level of the header signal line H5L, □ given to the D input of the D flip-flop 64 is applied to the D flip-flop 64. is written, and the output Q of the D flip-flop 64 changes from low level to high level. The high level output from this D flip-flop 64 is given as an enable signal to the register 78, and the identification data included in the header output from the parallel data buffer B4 is latched into the register 78 accordingly. Then, the header is also transmitted to the parallel data buffer B3.

Thereafter, the D input of the D flip-flop 64 is fixed at a high level by the OR gate 62, and its output Q is held at a high level until the next reset signal R arrives.

After that, data transfer between parallel data buffers proceeds,
The last data word DW (FIG. 3) of the data packet begins to be transferred from parallel data buffer B4 to parallel data buffer B3. At this time, the tail signal line TSL changes to a high level, and the C element C3 soon becomes a high level signal T.
Output RO. This high level signal is applied to the clock inputs of D flip-flops 64 and 68, and at this time, the high level of tail signal line TSL is applied to the D input of D flip-flop 68 through OR gate 66. Therefore, at the timing when the signal TRO of the C element C3 becomes high level, the output Q of the D flip-flop 68 becomes high level, and the last data word is provided to the parallel data buffer B3. Further, since the high level of its output Q is applied to the D input of the D flip-flop 68, this D flip-flop 68 is held at a high level until the next reset signal is applied.

At the moment when the outputs Q of the D flip-flops 64 and 68 both become high level, the output of the AND gate 76 becomes high level, and the stop signal 5TOP is sent to the C element C3.
(Figure 7) is given. Therefore, the next data packet cannot be transferred from the parallel data buffer B4 to the parallel data buffer B3 until the next stop signal, that is, the output of the AND gate 76 returns to low level. Once transferred to data buffer B0, the associated header signal 1JtHsL
++ becomes high level. And signal T of C element Co1
When RO becomes high level, the output Q of the D flip-flop 60 changes from low level to high level, and its header is transferred to parallel data buffer B in the previous stage. transferred to l.

When the output Q of the D flip-flop 60 becomes high level, a high level reset signal is applied to the D flip-flop 64 through the OR gates 72 and 74, so that both of its outputs Q become low level, and the output of the AND gate 76, i.e. The stop signal for C element C3 also becomes low level. Therefore, at this point, the transfer of a new data packet to the parallel data buffer B3 is allowed, and the D flip-flop 60 itself also
The next moment it is reset through the OR gate 70 and the circuit 48 returns to its initial state.

The identification data previously latched in the register 78 remains on the header signal line H3L until the header of the next data packet is output from the parallel data buffer B4 toward the parallel data buffer B3.

2 is held until it becomes high level again. Therefore, in the example of FIG. 10, the identification data given to the comparison circuit 56 (FIG. 9) is held until the data is transferred between the four stages of parallel data buffers, and the identification data given to the comparison circuit 56 (FIG.
This makes it easier to compare identification data.

FIG. 11 is a block diagram showing another example of the identification data detection circuit applicable to FIG. 9. Also in FIG. 11, like FIG. 10, only the first identification data detection circuit 52 for extracting identification data from the first data transmission path 28 is illustrated and explained.

In FIG. 11, the identification data detection circuit 52 includes a parallel data buffer B2 included in the first data transmission path 28.
r B3+ includes a multiplexer 58 that receives data from Ba and B5. That is, multiplexer 58
When a data packet is transferred from the subsequent parallel data buffer to the previous parallel data buffer, the outputs of the four parallel data buffers B2 to B5 are input.

A header signal line H3L is connected to the 17th bit of each of the parallel data buffers B, .about.B, that is, 1 bit of the order code. A header signal line H3L between parallel data buffers B and B2 is applied to multiplexer 58, inverted by an inverter, and applied to one input of AND gate GI. Header signal line HSL2 connected between parallel data buffers B2 and B3 is applied to the other input of AND gate G. The output of AND gate G is applied to multiplexer 58, inverted by an inverter, and applied to one input of AND gate G2. Header signal line H3L3 connected between parallel data buffers B3 and B4 is applied to the other input of AND gate G2. The output of the AND gate G2 is applied to the multiplexer 58, inverted by an inverter, and applied to one input of the two-man AND gate G3.

The other input of this AND gate G3 is connected to a header signal line H3 connected between parallel data buffers B4 and B5.
The output of L4 is given and the output is sent to multiplexer 58.
given to.

These header signal lines H3L and AND gates G, ~
The output of G3 is provided as an enable signal to a corresponding latch circuit (not shown) included in multiplexer 52.

In the initial state, the identification data extracted from the first data transmission path 28 is supplied from the multiplexer 58 to the comparison circuit 56 (FIG. 6) through the identification data line.
All header signal lines H3LI to H3L are at low level. When the header of the data packet is transferred from the subsequent parallel data buffer to the parallel data buffer B5, the header signal line H3L4 becomes high level. On the other hand, header signal line H3L between parallel data buffers B4 and B3
3 is still low level and therefore the AND gate G
The output of No. 2 is low level. Since this low level is inverted and given to AND gate G3, at this point,
A high level is output from this AND gate G3.

When the output of AND gate G3 goes high, the corresponding latch circuit included in multiplexer 58 is enabled, and the identification data from the separate hh data line between parallel data buffers B5 and B4 is latched into the launch circuit.

Thereafter, when the C element C6 detects that the parallel data buffer B4 is empty, the header of the data packet is transferred from the parallel data buffer B5 to this parallel data buffer B4. In response, header signal line H3L3 goes high, and the output of AND gate G2 goes high in the same way as AND gate G3. This anime game-1
``The high level output of G2 is inverted and the AND gate G
3, so the AND gate G3. The output of turns to low level. On the other hand, the AND gate G2 acts as an enable signal for the corresponding latch circuit included in the multiplexer 58, and at that timing, the parallel data buffer B4
The identification data included in the header transferred from the data buffer B3 to the parallel data buffer B3 is taken in.

By repeating this process, parallel data buffer B2
When the header of the data packet is transferred from the parallel data buffer B3, the header signal line H3L becomes high level. Therefore, the output of AND gate G becomes low level like AND gates G2 and G3. Hella! When the signal %H5L+ goes high, the corresponding latch circuit included in multiplexer 58 is enabled, and the identification data included in the data packet from parallel data buffer B2 is written into the latch circuit.

That is, the same identification data is sequentially written into the four latch circuits (not shown) of the multiplexer 58 while the data packet is transferred in the four registers. Therefore, during that period, the multiplexer 58 continues to output the same identification data. In this way, multiplexer 58 can be used to hold identification data for a certain period of time. In this way, in this case, when any one of the header signal lines HS, L, to H5L4 is at a high level, the identification data existing at the earliest stage among them is selected.

When the header of the data packet is transferred from the parallel data buffer B2 to the first-stage parallel data buffer B, and the subsequent data word other than the header is transferred to the parallel data buffer B2, the header signal line H5L becomes low level again. , Therefore, if any of the header signal lines H3LI to H3L4 is at a high level due to the header of the subsequent data packet, the circuit configuration described above will cause the header signal lines H3L to be set to the first stage among the header signal lines H3L to H3L4. Existing identification data will be selected.

In the example of FIG. 10, while the identification data detection circuit holds the identification data in the data packet, data transfer of other data packets in the data packet pair detection section of the corresponding data transmission path is stopped. Although time is wasted, the example shown in FIG. 11 is efficient because data shifting on the data transmission path is not stopped.

In the example of FIG. 11, the number of stages of parallel data buffers through which the multiplexer 58 receives data can be arbitrarily set depending on the required time.

FIG. 12 is a block diagram showing another example of a data processing device that is the background of the present invention. The firing section 27 in this example includes a data packet pair detection circuit 48 and a new data packet generation circuit 50, and in particular, the new data packet generation circuit 50.
It has the following characteristics. The new data packet generation circuit 50 includes a stop circuit 80° merging circuit 82 and a packet recombination circuit 8.
Contains 4. Stop circuit 80 is supplied with a match signal from comparison circuit 56 (FIG. 6) included in data packet pair detection circuit 48. The stop circuit 80 further includes header signal lines H3L2 . and a header signal line H3 between the parallel data buffers BI3 and B14 of the self-running shift register that constitutes the second data transmission line 34.
A header signal from L2□ is given. Furthermore, C corresponding to parallel and column data buffers B3 and BI3, respectively.
Signals TRO'' from elements C3 and CI3 are provided. From the stop circuit 80, the previous stage C elements C2 and CI
A stop signal 5TOP (FIG. 6) is applied to the merging circuit 82, and a merging control signal is applied to the merging circuit 82. The packet recombination circuit 84 is inserted into the first data transmission path 28 and is connected to the first data transmission path 28 and the second data transmission path 28 .
The data packet pair provided from the data transmission path 34 is reassembled into one new data packet, and the recombined new data packet is sent onto the first data transmission path 28.

The merging circuit 82 controls the merging of new data packets into the first data transmission path 28 by the packet recombination circuit 84 .

Referring to FIG. 14, the stop circuit 80 includes an OR gate 86
and one input comparison circuit 5 of this OR gate 86.
6 (Fig. 6) and its output is 2
It is applied to one input of each of two AND gates 88 and 90. The other input of the AND gate 88 has the 13th
The header signal line H3L2. shown in the figure. The header signal from the header signal line H3L2□ is applied to the other input of the AND gate 90. The outputs of AND gates 88 and 90 are provided together through OR gates 92 and 94 as the D inputs of D flip-flops 96 and 9, respectively. The clock input of this D flip-flop 96 is given the signal TRO from the C element C3 associated with the first data transmission line 28, and similarly, the clock input of the D flip-flop 98 is given the signal TRO from the C element C3 associated with the first data transmission line 28. Signal TRO from C element CI3 of transmission line 34 is applied. The outputs Q of D flip-flops 96 and 98, respectively, are connected to OR gates 92 and 9.
4 as its own D input and as the remainder input of OR gate 86.

The output Q of D flip-flop 96 is applied as is to one input of each of AND gates 100 and 102, and is inverted by an inverter and applied to one input of AND gate 104. In addition, the output Q of the D flip-flop 98 is directly connected to the AND gate 100.
and 104, is inverted by an inverter, and is applied to the other input of AND gate 102. The output of the antogenide 102 is given as a stop signal to the C element C2 of the first data transmission line 28,
The output of the AND gate 104 is applied to the C element CI2 of the second data transmission path 34 as a stop signal 5TOP. Furthermore, the output of the AND gate 100 is given to the merging circuit 82 as a merging control signal.

The D flip-flop 98 is connected to the first data transmission path 28
The signal AKI applied to the above-mentioned C element C2 included in is applied to the reset inputs of D flip-flops 96 and 98 as a stop release signal.

The merging circuit 82 receives the merging control signal from the stop circuit 80, and the merging control signal is inverted and sent to the AND gates 106,1.
08 and 116, and directly to one input of AND gate 114. The other input of the AND gate 106 is given the signal TPO from the C element C2 included in the first data transmission path 28. Further, the other input of the AND gate 108 receives a signal T from the C element CI2 included in the second data transmission path 34.
R○ is given. The output of the AND gate 106 is given to one input of the OR gate 112, and the other input of the OR gate 112 is given to the C element C2 and the C element CI.
The output of an AND gate 110 to which the signal TPO from □ and the merging control signal are applied. or gate 1
The output of C.12 is sent to the C.
given to the element. Similarly, the output of the AND gate 108 is also given to the C element in the previous stage included in the second data transmission path 34. The signal AK○ from the C element included in the first data transmission path 28 is applied to the other input of the AND gate 114, and the signal AKO from the C element in the previous stage of the second data transmission path 34 is applied. . The outputs of these two AND gates 114 and 116 are both passed through an OR gate 118 to the second data transmission line 3.
It is given to C element CI2 included in 4.

When the header of the data packet is transferred to the parallel data buffer B4 of the first data transmission path 28, the header signal line H
8L21 becomes high level, and at this time, when a high level coincidence signal is obtained from the comparison circuit 56 (FIG. 6) included in the data packet pair detection circuit 48, the stop circuit 80 outputs "
ANDGATE 88's two-person strength has reached a high level,
The D input of the D flip-flop 96 becomes high level.

Then, when the signal TRO from the C element C3 corresponding to the parallel data buffer B3 goes high, that is, when this header is transferred to the parallel data buffer B3, the D flip-flop 96 is sent and its output Q goes high. level. Further, when the header is transferred to the parallel data buffer BI4 included in the second data transmission path 34, the header signal line H8L2□ becomes high level, and if the above-mentioned match signal is obtained at this time, the signal from the C element CI3 is In response to signal TPO, D flip-flop 98 is turned on. That is, D flip-flops 96 and 98
is the parallel data buffer B3 on the second day of the first data transmission path.
and parallel data buffer B of the second data transmission line 34
13, when the headers of the data packets to be paired arrive, they are set, starting from whichever is faster. The D flip-flops that are not set are always sent when the header arrives. That is, D flip-flops 96 and 98 will hold the match signal from comparison circuit 56 of data packet pair detection circuit 48.

If one D flip-flop 96 is set and the other D flip-flop 98 is not yet set, that is, the corresponding header has not arrived at the parallel data buffer BI3 of the second data transmission path 34, The two inputs of gate 102 both go high, and therefore the stop signal 5TOP to terminal T6 (FIG. 7) of C element C2 goes high. Then,
This C element C2 is in a stopped state.

Conversely, when the D flip-flop 98 is set and the D flip-flop 96 is not set, that is, the first
When the corresponding header has not arrived on the second data transmission path 28, the AND gate 104 outputs a stop signal 5TOP, and therefore, the data transmission on the second data transmission path 34 is stopped.

In this way, the stop circuit 80 synchronizes the packets to be paired.

Next, when the two D flip-flops 96 and 98 are both sent, that is, when the corresponding headers have arrived at both parallel data buffers B3 and B13,
One input of both AND gates 102 and 104 becomes low level, and stop signal 5TOP becomes low level. Then, both of the two inputs of the AND gate 100 become high level, and a high level merging control signal is output to the merging circuit 82. Therefore, the merging circuit 8
One input of an AND gate 114 included in the second circuit becomes a high level, and conversely, one input of an AND gate 116 becomes a low level. Therefore, the data from the OR gate 118 is not transmitted from the C element of the second data transmission path 34, but from the first
The signal AKO from the C element included in the data transmission line 28 of
is output, and this signal is given as the signal AKI of the C element CI2 of the second data transmission line 34. At the same time, one input of the AND gate 108 becomes a low level, and the (7) signal %TRo from the C element CI2 to the previous stage Cffi becomes a low level. Furthermore, since the merging control signal is at a high level, the output of the AND gate 110 is enabled as an input to the OR gate 112. Therefore, when both the signals TRO of the C element C2 of the first data transmission path 28 and the C element CI2 of the second data transmission path 34 are at high level, the OR gate 112
A high-level signal TRO is applied to the C element in the preceding stage of the data transmission line 28. Therefore, after that, the second
The data packets on the data transmission path 34 are given to the packet recombination circuit 84 provided in the first data transmission path 28 and disappear from the second data transmission path 34.

In the data packet recombination circuit 84, the packets are recombined and a new data packet is output as the first data packet.
on the data transmission path 28, the stop circuit 80
A high level deactivation signal is applied to D flip-flops 96 and 9, both of which are reset, thereby disabling new data packet generation circuit 50.

In this way, a match between data packets to be paired is detected, and one new data packet is generated.

(The following is a blank space.) FIG. 15 is a block diagram showing an embodiment of the present invention. This embodiment in FIG. 15 is caused by a so-called "deadlock" in which a data packet to be paired with is forever not found.
To explain in detail, it is effective in preventing
In both the examples of FIG. 9 and FIG. 9, as shown in FIG.

For each of the two data transmission paths 28 and 34, only one data packet pair detection section 28a and 34a is defined. When each data packet pair detection section has only one data packet pair detection section, as shown in FIG. When data packets are circulated at the same transfer rate and in the order shown, it is impossible for the same identification data, eg, "A," to be detected simultaneously in the respective data packet pair detection sections 28a and 34a.

Therefore, in such a case, a "deadlock" occurs.

On the other hand, as shown in FIG. 17, if a plurality of data packet pair detection sections 28a+, 28a2, . be avoided. This is because even if data is transferred in opposite directions at the same transfer rate and in the order shown in both data transmission paths 28 and 34, the data packet pair detection section 34 of the data transmission path 34
When identification data such as "A2" exists in a, the other data packet pair detection section 28a and 28a2
This is because there is always a chance that the same identification data “A;” exists in any of the two. Therefore, "deadlock" can be avoided by defining a plurality of data packet pair detection sections on either one of the data transmission paths.

In FIG. 15, the first data transmission path 28 includes a plurality of data packet pair detection sections zsal.

2sa2. ..., 23an is provided, and the second
One data packet pair detection section 34a is defined in the data transmission path 34. Corresponding to the data packet pair detection sections 28a to 28an of the first data transmission path 28,
A plurality of identification data detection circuits 52, to 52n are provided,
On the other hand, one identification data detection circuit 54 is provided corresponding to the data packet pair detection section 34a of the second data transmission path 34.

The identification data from the identification data detection circuits 521 to 52n associated with the first data transmission path 28 are individually applied to one input of the corresponding comparison circuits 561 to 56n. The other input of these comparison circuits 56I to 56n is connected to the identification data detection circuit 54 of the second data transmission path 34.
Identification data from is commonly given. When a match of the identification data is detected in each of the comparison circuits 561 to 56n, a control signal is given to the new data packet generation circuit 50 from the corresponding comparison circuit. In response to the coincidence signal, the new data packet generation circuit 50
From the two matching data packets, one new data packet is created, for example, in the same manner as in the example shown in FIG. 12 above.

In the embodiment shown in FIG. 15, the two data transmission paths 28 and 34 are illustrated and described as transmitting data in the same direction, but they are configured as reverse loops as shown in FIG. 17. Of course, this is a good thing.

FIG. 18 is a block diagram showing the embodiment of FIG. 15, that is, a concrete example of FIG. 17. In the embodiment shown in FIG. 18, one identification data detection circuit 52 is provided in connection with one data transmission path 28, and two identification data detection circuits 541 and 54□ are provided in connection with the other data transmission path 34. provided.

That is, the identification data detection circuit 52 is connected to the data transmission line 28.
4 parallel data buffers B.

~Identification data detection circuit 54 that extracts identification data from input data to B4. and 54□ are ``parallel data buffers Bll~'' constituting the data transmission path 34, respectively.
Identification data is extracted from the input data to B14 and the input data to B21"'B24. The identification data detected by the identification data detection circuit 52 is sent to the two comparison circuits 5.
6. and 562 in common. The identification data detected by identification data detection circuits 54 and 54□ are individually provided to corresponding comparison circuits 561 and 56□, respectively.

The two comparing circuits 561 and 56□ compare whether the two applied identification data match, and the matching signals are applied to the stop circuit 80', respectively. Stop circuit 80
' is used to synchronize paired data packets transmitted on the two data transmission paths 28 and 34, and is very similar to the embodiment shown in FIG. and,
A control signal is provided from the stop circuit 80' to the merge circuit 82, which cooperates with the bucket recombination circuit 84 to send a new data packet onto the data transmission path 28.

The stop circuit 80' receives the header signal from the header signal line H3L between the parallel data buffers B3 and 84 which constitute the first data transmission line 28, and the parallel data buffer B23 which constitutes the second data transmission line 34. and B24
A header signal from the header signal line H8L2 between the two is given. Furthermore, signals T from C elements C3 and C23 corresponding to parallel data buffers B3 and B23, respectively.
RO3 and TRO□ are given.

From the stop circuit 80', the preceding stage C elements C4 and C24
stop signals 5TOP and 5TOP2 respectively for
is provided, and a merging control signal is also provided to the merging circuit 82.

The stop circuit 80' includes an OR gate 86', as shown in FIG. 19, and two inputs of the OR gate 86' are connected to respective comparison circuits 56. Coincidence signal 1 and coincidence signal 2 from 56□ and 56□ are applied, and the output thereof is applied to one input of AND gate 88. The other input of AND gate 88 is given a header signal from header signal line H3L. Two inputs of AND gate 90 are supplied with match signal 1 and a header signal from header signal line H8L2. The outputs of AND gates 88 and 90 are provided through OR gates 92 and 94 as the D inputs of D flipflops 96 and 98, respectively. A clock input of this D Frisopfromp 96 receives a signal TR from a C element C3 associated with the first data transmission line 28.
0I is given, similarly, D flip-flop 98
A signal TPO□ from the C element C23 of the second data transmission path 34 is applied to the clock input of the . The output Q of each D flip-flop 96 and 98 is provided as its own D input through an OR gate 92 and 94.

The output Q of D flip-flop 96 is applied as is to one input of each of AND gates 100 and 102, and is inverted by an inverter and applied to one input of AND gate 104. In addition, the output Q of the D flip-flop 98 is directly connected to the AND gate 100.
and 104 , and is inverted by an inverter and applied to the other input of AND gate 102 . The output of the AND gate 102 is the stop signal 5
TOPI is given to the C element C4 of the first data transmission line 28, and the output of the AND gate 104 is the stop signal 5TO.
The signal P2 is applied to the C element C24 of the second data transmission path 34. Furthermore, the output of the AND gate 100 is given to the merging circuit 82 as a merging control signal.

Furthermore, a stop release signal is applied to the reset inputs of D flip-flops 96 and 98.

The merging circuit 82 and the data packet recombination circuit 84 are the same as those shown in FIG. 14 and later.

When the header of the data packet is transferred to the parallel data buffer B3 of the first data transmission path 28, the header signal line H
3L, becomes high level, and at this time, comparison circuit 56.3L included in data packet pair detection circuit 48. Or when a high level match signal is obtained from 56□, the stop circuit 80'
The two outputs of the AND gate 88 both become high level, and the D input of the D flip-flop 96 becomes high level. At this time, the signal TR0I from the C element C3 becomes high level, and the D flip-flop 96 is set. , its output Q becomes a high level.Furthermore, when the header is transferred to the parallel data buffer B23 included in the second data transmission path 34, the header signal 1JIH3L2 becomes a high level, and at this time a match is detected from the comparison circuit 56□. When the signal is obtained, the D flip-flop 98 is set in response to the signal TRO2 from the C element C23.
When headers of data packets to be paired arrive in parallel data buffer B3 of 8 and parallel data buffer B23 of second data transmission path 34, whichever is faster is set. The D flip-flops that are not set are always sent when the header arrives.

That is, D flip-flops 96 and 98 are connected to comparator circuits 56 . and 56
The match signal from □ will be held.

If one D flip-flop 96 is set and the other D flip-flop 98 is not yet set, that is, the corresponding node has not arrived at the parallel data buffer B23 of the second data transmission path 34. Then, the two inputs of the AND gate 102 of the stop circuit 80' are both at a high level, and therefore the stop signal 5TOP to the terminal T6 (FIG. 7) of the C element C4 is at a high level. Then, this C element C2 will be in a stopped state.

Conversely, when the D flip-flop 98 is set and the D flip-flop 96 is not set, that is, the corresponding header has not arrived at the first data transmission path 28, the stop signal S T OP is sent from the AND gate 104.
2 is output, and therefore data transmission on the second data transmission path 34 is stopped.

The state in which the two D flip-flops 96 and 98 are both set, that is, the parallel data buffers B3 and B
23, one of the inputs of AND gates 102 and 104 becomes low level, and the stop signals 5TOPI and STOP
2 are both at low level. In response, both of the two inputs of the AND gate 100 become high level, and a high level merging control signal is output to the merging circuit 82.

Therefore, the AND gate 11 included in the confluence circuit 82
4 (FIG. 14) are both at high level, and conversely, one input of AND gate 116 is at low level. Therefore, from the OR game 1-118 (FIG. 14), the signal AKO is output not from the C element of the second data transmission path 34 but from the C element included in the first data transmission path 28, and this signal is the second data transmission path 3
It is given as the signal AKI of the C element C24 of No. 4. At the same time, one input of the AND gate 108 (FIG. 14) both becomes low level, and the signal TRO from the C element C24 to the preceding C element becomes low level. Furthermore, since the merging control signal is at a high level, the merging circuit 82
(FIG. 14) As an input to the OR gate 112, the output of the AND gate 110 is enabled. Therefore, the first
The signals TRO and T
When both RO2 are at high level, a high level signal TPO is applied from the OR gate 112 to the C element at the further preceding stage of the first data transmission path 28. Therefore, from then on, the data packets on the data transmission line 34 of tube 2 are
A packet recombination circuit 8 provided in the data transmission line 28 of
4 and disappears from the second data transmission path 34.

In the data packet recombination circuit 84, the packets are recombined and a new data packet is output as the first data packet.
on the data transmission line 28, the stop circuit 80
A high level deactivation signal is applied to ', D flip-flops 96 and 98 are both reset, and new data packet generation circuit 50 is therefore disabled. In this way, a match between data packets to be paired is detected, and one new data packet is generated.

FIG. 20 is a modification of the embodiment shown in FIG. 18, and is also a concrete example of the embodiment shown in FIG. 15, that is, FIG. 17.

This embodiment consists of a plurality of basic modules M, , M2 . M3
+... are connected in cascade. The basic module M is shown in FIG. Basic module M is the 18th
Since the circuit is very similar to the circuit shown in the figure, a detailed explanation thereof will be omitted here, but identification data is extracted from two different data packet pair detection sections of the second data transmission path 34 by two identification data detection circuits. It is made possible.

Focusing on one basic module M2, the comparison circuit 56□ (FIG. 21) finds a match when two data packets to form a pair are both transferred to that module M2.

On the other hand, the comparison circuit 56. The reason why there is a match is that among the two data packets to be paired, the data packet on the first data transmission path (the upper data transmission path in the figure) is in the module M2, but the second data packet is in the module M2. The data packet on the channel (lower data transmission channel in the figure) is in the next adjacent module M, which is on the left side in the figure. In other words, the data packets existing in the four parallel data buffers that make up the upper data transmission path are transferred to the 8-stage parallel data buffer that includes the adjacent module. If the other party's data packet is sent to the module M2, the other party's data packet is waited for until it arrives at the module M2. Conversely, data packets existing on the lower data transmission path are forced to wait until the other party's data packet arrives at module M2 only when the other party's data packet is transferred into the same module M2. In this way, according to the embodiment in FIG. 20, by simply connecting a plurality of basic modules in cascade, two data bucket detection sections on the lower data transmission path and one data pair on the upper data transmission path can be obtained. The packets will be compared with the detection period, and the 18th
As shown in the figure, "deadlock" caused by data miscommunication can be completely eliminated.

[Brief explanation of the drawing]

FIG. 1 is a conceptual system diagram showing an example of a data processing device in which the present invention can be implemented. FIG. 2 is a schematic block diagram showing the principle of a data processing device which is the background of this invention. FIG. 3 is a diagram showing an example of a data packet, and FIG. 3(A) and FIG. 3(B) each show a different example. Figures 4 and 5 are paired, respectively. FIG. 2 is a conceptual diagram illustrating generation of one new data packet from a previous data packet. FIG. 6 is a block diagram showing an example of a data processing device that is the background of the present invention. FIG. 7 is a circuit diagram showing an example of the C element. FIG. 8 is a timing diagram for explaining the circuit of FIG. 7. FIG. 9 is a block diagram showing another example of a data processing device which is the background of the present invention. FIG. 10 is a block diagram showing an example of an identification data detection circuit applicable to FIG. 9. FIG. 11 is a block diagram showing another example of the identification data detection circuit that can be used in FIG. 9. FIG. 12 is a block diagram showing still another example of a data processing device which is the background of the present invention. FIG. 13 is a circuit diagram showing an example of the stop circuit shown in FIG. 12. FIG. 14 is a circuit diagram showing an example of the merging circuit shown in FIG. 12. FIG. 15 is a block diagram showing one embodiment of the present invention. - FIGS. 16 and 17 are schematic diagrams showing the flow of data for explaining the concept of the embodiment shown in FIG. 15. FIG. 18 is a block diagram showing an example of the embodiment shown in FIG. 15, that is, an embodiment of FIG. 17. FIG. 19 is a circuit diagram showing the stop circuit of FIG. 18. FIG. 20 is a block diagram showing another embodiment of the embodiment shown in FIG. 15, that is, FIG. 17. . FIG. 21 is a block diagram showing one basic module of FIG. 20. In the figure, 27 is a firing section, 28 is a first data transmission path, 28a, 28a+ to 28an, 34a, 34a+,
34a2 is a data packet pair detection section, 34 is a second data transmission path, 36 is an firing detection section, 48 is a data packet pair detection circuit, 50 is a new data packet generation circuit, 52,
54.521-52n are identification data detection circuits, 56,5
61 to 56n are comparison circuits, 80.80' is a stop circuit, 8
Reference numeral 2 indicates a merging circuit, and reference numeral 84 indicates a recombination circuit. Patent applicant Sanyo Electric Co., Ltd. (3 idiots) Agent Patent attorney Yama 1) Yoshito (1 idiot) Figure 1 Figure 2 7R Figure 3 (B) Figure 5 Figure 8

Claims (1)

[Claims] 1. A first data transmission line for transmitting a data packet containing identification data and configured using a shift register; A first data transmission line for transmitting a data packet containing identification data and configured using a shift register; a second data transmission path configured using one of the first and second data transmission paths, a single or plural data packet pair detection section defined in one of the first and second data transmission paths, and the other of the first and second data Identification data detection means for detecting the identification data included in a data packet from a plurality of data packet pair detection sections defined in a transmission path, and comparing the identification data detected by the identification data detection means. pair determining means for determining data packets to be paired to be transmitted on the first and second data transmission paths; and generating one new data packet from the two data packets determined by the pair determining means. A data processing device comprising new data packet generation means for generating new data packets. 2. The data processing device according to claim 1, wherein the pair discrimination means includes a plurality of comparison means for comparing the identification data corresponding to the plurality of data packet pair detection sections. 3. The data processing device according to claim 1 or 2, wherein the data packet pair detection period is defined as a single stage of a shift register. 4. The data processing device according to claim 1 or 2, wherein the data packet pair detection period is defined as a plurality of stages of a shift register. 5. At least one of the first and second data transmission paths is formed in a loop shape, and the data packet is circulated around the loop-shaped transmission path.
5. The data processing device according to any one of Items 4 to 4. 6. In response to the identification data detecting means detecting specific identification data transmitted through one of the first and second data transmission paths, 6. A data processing device according to claim 1, further comprising means for waiting for a data packet to arrive. 7. The data processing apparatus according to claim 6, wherein the waiting means includes stopping means for stopping shifting of the one data transmission path. 8. The data processing device according to claim 1, wherein the data packets are transmitted in opposite directions on the first and second data transmission paths. 9. The data processing device according to any one of claims 1 to 8, wherein each of the shift registers forming the first and second data transmission paths is configured as a self-propelled shift register. .