JPS61278937A - Data processor - Google Patents

Abstract

PURPOSE:To generate more quickly a new data packet and to prevent a detecting error by detecting data to be paired when data is transmitted on a data transmission line and keeping the detection during the prescribed period. CONSTITUTION:Identification data detecting circuits 52 and 54 detect two types of identification data from the data packet transmitted on the 1st and 2nd data transmission lines 28, and a comparator circuit 56 compares two detected identification data. When they are equal or in the certain relationship, the comparator circuit 56 supplies a control signal to a new data packet generating circuit 50. In such a case, the data packet detection sections 28a and 34a of a certain length are set to the data transmission lines 28 and 34 to prevent the detecting error. The generating circuit 50 fetches the data packets including the detected identification data, and generates and outputs new one data packet.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a data processing device, and particularly to a data processing device that generates one new data packet from two data packets, such as a firing section of a data-driven data processing device. The present invention relates to a data processing device.

(Prior Art) Neumann type data processing apparatuses have drawbacks such as slow speed due to sequential processing and inability to perform parallel processing. Therefore, recently, data driven type (data flow type) data processing apparatuses have been proposed and implemented. An example of such a data-driven data processing device is disclosed, for example, in Nikkei Electronics, published on April 9, 1980, pages 181 to 218.

In conventional systems, in order to detect firing, data packets from the data bus are stored in a matching memory, and the identifier or identification data of the data packet stored in the matching memory is searched to find the data packet of the other party to be paired. I'm trying to find it. In this conventional system, it takes a very long time to search for identification data in the rendezvous memory, resulting in a slowdown of the entire data processing device.

Therefore, in a concurrently pending patent application, the present inventors proposed a new data processing device that can more quickly find the data packet of the other party.

To put it simply, the novel data processing device that forms the background of this invention includes first and second output transmission paths, which are configured using shift registers, for transmitting data packets including identification data. identification data detection means connected to the first and second data transmission paths for detecting identification data included in data packets transmitted respectively; A pair determining means for determining data packets to be transmitted on a second data transmission path and to form a pair, and a new data packet generation for generating one new data packet from two data packets determined by the pair determining means. A data processing device comprising means.

(Problem to be Solved by the Invention) However, in the above data processing device, identification data must be detected while transmitting data packets on the data transmission path, and pair discrimination must be performed based on the identification data. However, depending on the data transfer speed, the time required for this may become too short, which may result in detection errors.

Therefore, the main object of the present invention is to provide a data processing device that can secure sufficient time for comparison of identification data.

(Means for Solving the Problems) Simply put, the present invention provides first and second data transmission paths for transmitting data packets including identification data and configured using shift registers; first and second identification data extraction means for extracting identification data transmitted on the first and second data transmission paths;
A holding means for holding the identification data extracted by the identification data extraction means for a predetermined period of time, a comparison means for comparing two pieces of identification data held by the holding means, and a corresponding response depending on the output of the comparison means. The data processing apparatus includes new data packet generation means for generating one new data packet from data packets on first and second data transmission paths.

(Operation) Data packets are transmitted individually on the first data transmission path and the second data transmission path. The first and second identification data extraction means extract identification data from the data packets transmitted on the respective data transmission paths. The holding means holds the identification data thus extracted for a predetermined period of time. The comparison means compares the two held identification data. The signal data packet generating means processes the paired data packets transmitted on the two data transmission paths in a predetermined manner to generate one new data packet. This new data packet is then used for later processing, such as arithmetic processing.
is provided to the main data transmission path.

(Effects of the Invention) According to the present invention, data packets to be paired are detected while data is being transmitted on the first and second data transmission paths, so that it is possible to detect data packets that are to be a pair while data is being transmitted on the first and second data transmission paths. In comparison, new data packets can be generated faster. Therefore, the data processing apparatus as a whole can be configured as a faster system.

Furthermore, according to this invention, since the extracted identification data is retained for a predetermined period of time, even if the transmission speed of the data transmission path is high, sufficient time can be secured for comparison, and therefore detection errors can occur. There is almost no possibility that this will occur.

Furthermore, if a self-propelled shift register is used as a data transmission path, it will be easy to connect it to an asynchronous main data transmission path, and when configured as a data-driven data processing device,
The advantages can be brought out even more effectively.

The above objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

(Embodiment) FIG. 1 is a conceptual system diagram showing an example of a data processing device in which the present invention can be implemented. The system 10 includes an asynchronous delay line ring 12 as a data transmission path, a data packet to be processed is given to the asynchronous delay line ring 12 through a merging section 14, and the processed data is outputted through a branching section 16. 0 confluence 1
The data packet given from 4 passes through the asynchronous delay line ring 12, is branched by the branching section 18, and is given to the function storage section 20. The data read from the function storage section 20 is given to the asynchronous delay line ring 12 again through the merging section 22.

For example, as shown in FIG. 3(A), the data packet given from the function storage unit 20 includes a header HD and a plurality of data words DW following the header HD.

~DWn included. Header) (D includes a processing code PC and a control code CC, and this processing code PC includes a code indicating a packet structure and a code indicating processing contents. As a code indicating a packet structure, for example, the header For example, an order code indicating that the data word is the last data word, etc. is given by the 17th and 16th two bits.The code indicating the processing content is as follows.
In particular, it is called the F code, such as "+J, r-J,
...or used to specify the type of processing, such as data replacement or insertion. In the control code CC,
It includes logical information such as physical optical information, node information resulting from the program structure, and color information.

The data packets as described above transmitted by the asynchronous delay line ring 12 are provided to a first loop-shaped data transmission line 28 forming a firing section 27, for example, through a branching section 24 and a merging section 26. Different data packets are taken into a second loop-shaped data transmission path 34 forming the firing section 27 through different branching sections 30 and merging sections 32 . The data packets applied to the first and second loop-shaped data transmission paths 28 and 34 are transmitted through the respective loops in opposite directions, and are applied to the firing detection section 36 that constitutes the firing section 27 together with these transmission paths. The zero firing detection unit 36 compares the control codes included in each data packet between two data packets, thereby distinguishing between the data packet existing on the first loop-shaped data transmission path 28 and the first data packet. It is determined whether or not the data packets existing on the two loop-shaped data transmission paths 34 form a pair, and one new data packet is generated based on the specific data packet detected as the data packet pair. The new data packet generated in this manner is placed, for example, on the first loop-shaped data transmission path 28 and is brought onto the asynchronous delay line ring 12 again through the branching section 38 and the merging section 40.

A new data packet transferred on the asynchronous delay line ring 12 is transferred to the arithmetic processing unit 44 through the branching unit 42, for example.
and then processes the data to be processed included in the data packet according to the processing code included in the header of the data packet. The data processed by the arithmetic processing unit 44 is merged into the asynchronous delay line ring 12 again through the merge unit 46. This processing result is given again to the function storage section 20 or the branching section 16
It is output through.

Note that the system 10 is further provided with a control command processing section and a color management section.

This invention is suitable as the firing section 27 of the system 10 shown in FIG. However, the present invention is generally applicable to all data processing devices that need to find the data of the other party to form a pair and generate one piece of new data from the data of that pair. Let me point this out in advance.

FIG. 2 is a schematic block diagram illustrating the principle of a novel data processing device that forms the background of this invention. The first and second loop-shaped data transmission lines 28 and 34 are constituted by shift registers, preferably self-running shift registers. As will be explained in detail later, a self-propelled shift register is capable of independently and simultaneously pushing in and popping out data, and furthermore, it is capable of pushing in and popping out data while the next register is empty. Therefore, in this example and the embodiments described later, these first and second data transmission lines 28 and 34 are
It is configured as an asynchronous data transmission path.

Note that the two data transmission paths 28 and 34 have been described as forming a loop in the system of FIG.

However, these do not necessarily have to be loop-shaped. However, as will be explained in detail later, it is desirable that at least one of them, and more preferably both, be configured as a loop.

Such first and second data transmission paths 28 and 3
4, data packets having the structure shown in FIG. 3 are transmitted in the same direction or in mutually opposite directions. What is shown in FIG. 3(A) is one data word per data word.
Figure 3 CB
) indicates that one data word includes a plurality of (two in this example) data to be processed.

A firing detection section 36 is connected to the first and second data transmission paths 28 and 34, and the firing detection section 36 includes a data bucket pair calibration circuit 48 and a new data packet generation circuit 50. Data packet pair detection circuit 48
is the control code CC (FIG. 3) from the data packet transmitted through the first and second data transmission paths 28 and 34.
By extracting the identification data included in the data packet and comparing the two extracted identification data, the data packet of the other party to be paired is detected. When a data packet pair is detected, this data packet pair detection circuit 4
8, a signal is given to the new data packet generation circuit 50. Accordingly, the new data packet generation circuit 50
Then, each data packet containing the detected identification data is captured, one new data packet is generated from the two captured data packets, and it is output.

To explain in more detail, as shown in FIG.
It is assumed that data packets DPI and DP2 having the configuration shown in A) are being transmitted on the first and second data transmission paths 28 and 34, respectively. From these data transmission lines 28 and 34, identification data IDI and ID2 are transmitted.
is applied to the data packet pair detection circuit 48, and the two identification data IDI and I
D2 is extracted and compared. These two identification data IDs
If I and ID2 have a certain relationship,
For example, if the node information in the program structure matches, this is detected by the comparison circuit. In this way, the data packet pair detection circuit 48 identifies data packets DPI and DP2 as being paired with each other. In the new data packet generation circuit 50, the thus specified data packet 7) DP I
and DP2 are read from the first and second data transmission paths 28 and 34, respectively, to generate one new data packet DP. This new data packet is
It has a data packet structure as shown in FIG. 3(A).

Further, as shown in FIG. 5, data packets DPI and DP2 having structures as shown in FIG. 3(B) are transmitted on the first and second data transmission paths 28 and 34, respectively. shall be.

In the same way as in Figure 4, the data packet DPI
and identification data IDI and ID2 included in DP2
are compared and when a certain relationship is detected, the new data packet generation circuit 50 generates a new data packet as shown in FIG.
one data packet DP is generated. In the example shown in FIG. 5, the new data packet DP has the structure shown in FIG. 3(B).

FIG. 6 is a block diagram showing an example of a data processing device that is the background of the present invention. In this example, both the first and second data transmission lines 28 and 34 are configured as self-running shift registers. The self-running shift register constituting the first data transmission path 28 includes a plurality of cascade-connected parallel data buffers B, -85 and C elements (Co) corresponding to the respective parallel data buffers B, ~B5.
Similarly, the free-running shift register constituting the second data transmission line 34 includes cascade-connected parallel data buffers Bll to BIS and their respective corresponding C elements CIl. - Contains CI5.

Here, with reference to FIGS. 7 and 8, the C element constituting the asynchronous self-propelled shift register will be described. C
Element C includes six terminals T, ~T6, and terminal T1 receives a signal TRI (Transfer
In ) is given, and from terminal T2, a signal A KO (Acknowledge Ou
t) is output. A signal T RO (Transfer 0ut) is output from the terminal T3 to the C element in the previous stage, and a signal AK I from the C element in the previous stage is output from the terminal T4.
(Acknowledgement In) is given.

Signal TRO is further given to its corresponding parallel data buffer as a transfer command signal. And signal AK
I is given as an empty signal of the preceding stage parallel data buffer.

Note that a recent signal RESET is applied to the terminal T5, and a stop signal 5TOP is applied to the terminal T6.

In the circuit of FIG. 7, terminal T, Karacent signal RE
When SET is given, it is inverted by an inverter and this signal is given to four Nant gates GI
*The outputs of c, l c, I and GI4 all become high level. Nantes Gate G,,G4. G, and G
, 4 are at high level, and therefore the outputs of NAND gates G3 and G13 that receive them are both at low level. The high level output of the Nandt gate Ga becomes the signal AKO, which is given as the signal AKI from the terminal T2 to the C element at the subsequent stage. This is a signal representing the empty state of the preceding stage parallel data buffer. At this time, if the data has not arrived yet, the signal T to the terminal T
RI is at low level. Reset signal R to terminal T,
When ESET is released, the output of the inverter becomes high level, while the signal AK' from NAND gate G+a is also high level, and this state is the initial state.

In the initial state, therefore, the two inputs of each of the Nant gates GI and Go are at a high level, and one input of the OR gates G2 and G1° is at a high level. Therefore, 2 of Nant Gate G3 and CI3
The two inputs are both at high level, so the outputs of these Nant gates G3 and G13 are both at low level. That is, signal TR' and terminal T3
The signal TRO from is at low level. Nantes Gate G
The inputs of 4 and G14 are low level, high level, and high level, respectively, and these Nant gate G
The outputs of 4 and G, 4 are each at high level.

When the data is transferred and the signal TRI applied to terminal 1' from the C element in the subsequent stage changes to a high level as shown in FIG.

All three human powers become high level, and their output becomes low level. Then, the output of the Nant gate G3, that is, the signal TR' becomes high level as shown in FIG. 8, and the output of the Nant gate G4 becomes low level. When the signal TR' becomes high level, the outputs of Nant gates G and I become low level, and the output T of Nant gate CI3 becomes low level.
RO is at high level, and the output AK' of Nant gate G, 4 is at low level. The outputs of Nando game 1, G4 and CI4 are returned to the inputs of Nande gates G3 and CI3, respectively, and the outputs of these Nande gates G3 and G,3 are locked at a high level.

In this way, as shown in FIG. 8, the signal AK○ from the terminal T2 becomes low level, indicating that data has been transferred to the corresponding parallel data buffer of this C element C. In other words, in that state, data transfer is no longer possible. This is communicated to the subsequent C element that the message is not accepted. Also, Nantes Gate CI
3 is at high level, and from terminal T3, the previous stage C
A high level signal TPO is applied to the element. This high level signal TRO is given as a transfer command to the corresponding parallel data buffer, and the data in the parallel data buffer is sent to the previous stage.

When the signal AKO becomes low level, the signal TRI becomes low level as shown in FIG. 8, and therefore the output TR' of the Nant gate G returns to high level. Furthermore, as described above, as the output AK' of the Nandgate CI4 changes to low level, the output AKO of the Nandgate G4 returns to high level, and the output T of the Nandgate gate G3 changes to low level.
R' returns to low level.

When the signal AKO from the C element in the previous stage, that is, the signal AKI applied from the terminal T4, changes from high level to low level as shown in FIG. 8, that is, when the empty space in the parallel data buffer in the previous stage is extracted, Or Gate G12
Since the input of the OR gate G1 is at a low level and the signal TR' is also at a low level, the output of the OR gate G1° is also at a low level. At this time, the output of Nandgate Gl3 is at a high level, so Nandgate G1.G.

4 output changes to high level. Therefore, Nando game
The input of 1-G+3 becomes high level, and the output of this Nant gate G13 changes to low level. In this way, the state returns to the same state as the initial state.

If the signals A and KO from the previous stage C element, that is, the signal AKI from the terminal T4, remain at low level, that is, if the parallel data buffer corresponding to the previous stage C element is not yet empty, then the Nant gate Nantes Gate G1. Since one input of G0 . does not work and the signal TRO does not go high, thereby refusing to accept data from the subsequent stage, and therefore data cannot be transferred to the parallel data buffer corresponding to this C element in this state.

In addition, a stop signal 5TOP is applied to this C element C from the terminal T6.
is given, the high level signal is the OR gate G
5 to Nantes Gate GI3. Therefore, the output of this Nant gate G+3 becomes a low level, and in this state, the signal TPO from the terminal T3 becomes a low level and is transmitted to the C element in the previous stage, and data transfer is stopped. As shown in the figure, parallel data buffers B, ~B, and C elements C8-C5 and parallel data pants 1Bll-BIB and C elements C8, ~C15
The asynchronous free-running shift registers of the data transmission lines 28 and 34 are configured by the above.

(Left below) Returning to FIG. 6, each of the parallel data buffers B4 constituting the first and second data transmission paths 28 and 34
and BI4 to parallel data buffers B3 and BI3
A data line extends from the data transmission path to the data packet pair detection circuit 48, and each data is supplied from the data line to identification data detection circuits 52 and 54 included in the data packet pair detection circuit 48. The identification data detection circuits 52 and 54
Now, the identification data is extracted from the header of the data packet (FIG. 3) and provided to the comparison circuit 56. The comparison circuit 56 compares the two pieces of identification data provided and determines whether they match or do not match. When the comparison circuit 56 detects a match between the two pieces of identification data, the data packet to be paired is determined, and the
A control signal that informs the new data packet generation circuit 5
given to 0.

A transmission line extends from the parallel data buffers B3 and B13 forming the first and second data transmission lines 2 and 34 to the parallel data buffers B2 and B, □ to the new data packet generation circuit 50. In the new data packet generation circuit 50, based on the coincidence signal or control signal from the comparison circuit 56, a specific data packet that is determined to be a pair is taken in through the data packet line, and the new data packet generation circuit 50 So,
The two data packets are combined to create one new data packet. The new data packet D generated by the new data packet generation circuit 50 in this way
P (FIG. 4 or 5) is transmitted through the new data packet line to the main data transmission path 12 for later processing.
(FIG. 1) and sent to other processing circuits.

In the embodiment shown in FIG. 6, identification data detection circuits 52 and 54 detect and compare identification data within a relatively short time that data packets are sent from parallel data buffers B4 and BI4 to parallel data buffers B3 and BI3. In circuit 56 it must be compared within that time. Therefore, depending on the data transmission speed in the data transmission lines 28 and 34, a detection error may occur.

Therefore, it is conceivable to adopt a configuration in which the identification data detection circuits 52 and 54 hold the identification data of the data packet for a certain period of time.

FIG. 9 is a schematic block diagram showing another embodiment of the invention. The ignition section 27 of this embodiment includes an ignition detection section 36 connected to the first and second data transmission paths 28 and 34, as in the previous embodiment of FIG. The firing detection section 36 includes a data packet pair detection circuit 48 and a new data packet generation circuit 50. The data packet pair detection circuit 48 includes an identification data detection circuit 52 for detecting identification data from data packets transmitted on the first data transmission path 28 and a data packet transmitted on the second data transmission path 34. It includes an identification data detection circuit 54 for detecting identification data from. The two identification data thus detected are compared by a comparison circuit 56. In the comparison circuit 56, when the two match or there is a certain relationship, the new data packet generation circuit 50
Give a control signal to.

In this embodiment, the first and second data transmission paths 2 and 34 have data packets of a certain length in the detection interval 2 and 34, respectively.
8a and 34a are defined, and the same identification data is extracted from these data packet pair detection sections 28a and 34a for a relatively long period of time, thereby making the comparison in the comparison circuit 56 easier.

FIG. 10 is a block diagram showing an example of an identification data detection circuit applicable to the embodiment of FIG. 9. In this Figure 10,
A first device that detects identification data from the first data transmission path 28.
Although only the identification data detection circuit 52 of FIG.

The free-running shift registers constituting the first data transmission line 28 are cascade-connected parallel data buffers B. I+BO
~B4 and their related C elements C6l l c
o""Includes C4. Each parallel data buffer BO
The 17th bit of BO to B4 is connected to the header signal line H3L, and the 16th bit is connected to the tail signal line TS.
L are connected respectively. Parallel data buffer B. 1
and B.

Header signal line H3L+ between parallel data buffers B3 and B4 is applied to the D terminal of D flip-flop 60, and header signal line H3L+ between parallel data buffers B3 and B4.

2 is the D flip-flop 64 through the OR gate 62.
is given to the D input of The tail signal line TSL12 between parallel data buffers B3 and B4 is connected to an OR gate 66.
to the D input of the D flip-flop 68.

The clock input of the D flip-flop 60 is C.
A signal TRO from element C8 is provided. An OR gate 70 is connected to the reset input of this D flip-flop 60.
An initial reset signal is applied through the circuit, and its own output Q is applied thereto. The output Q of D flip-flop 60 is further provided, along with an initial reset signal, through OR gates 72 and 74 to the respective reset inputs of D flip-flops 64 and 68. It is applied to the other input of the above-mentioned OR gate 62 which is applied to the D input of , and also applied to one input of the AND gate 76 . The output Q of the D flip-flop 68 is given to the other input of this AND gate 76, and this output Q is further applied to the OR gate 66 whose output is given to its own D input.
is given to the other input of

A header signal line is taken out from the transmission path from parallel data buffer B4 to parallel data buffer 7B3, and this header signal line is applied to register 78. This register 7
The output Q of the aforementioned D flip-flop 64 is applied to the clock input of 8. The output of this register 78 is then used as the detected identification data by the comparator circuit 56 (sixth
Figure) is given.

In the initial state, a high level initial reset signal is applied. This initial reset signal is
．． Through 72 and 74, D flip-flop 60.
64 and 68, and accordingly, these D flip-flops 60, 64 and 68 are reset, and their respective data Q becomes low level. This state is the initial state.

When the parallel data buffer B3 is detected to be empty by the associated C element C3, data packets begin to be transferred from the parallel data buffer B4 to this parallel data buffer B3. When a data packet, that is, its header is transferred from the parallel data buffer B4 to the parallel data buffer B3, the header signal lines H3L and □ between them become high level. With the start of such data packet transfer, the signal TPO from the C element C3 goes from low level to high level. Then, this high level signal is given to each clock input of the D flip-flop 64 and 6th, and the high level of the header signal line HSL, 2 given to the D input of the D flip-flop 64 is applied to the D flip-flop 64. 64, and the output Q of the D flip-flop 64 changes from low level to high level. The high level output from this D flip-flop 64 is given as an enable signal to the register 78, and the identification data included in the header output from the parallel data buffer B4 is latched into the register 78 accordingly. Then, the header is also transmitted to the parallel data buffer B3.

Thereafter, the D input of the D flip-flop 64 is fixed at 1 and at a high level by the OR gate 62, and its output Q is held at a high level until the next reset signal R arrives.

After that, data transfer between parallel data buffers proceeds,
The last data word DW (FIG. 3) of the data packet begins to be transferred from parallel data buffer B4 to parallel data buffer B3. At this time, the tail signal line TSL changes to a high level, and the C element C3 soon becomes a high level signal T.
Output RO. This high level signal is applied to the clock inputs of the D flip-flop processors 4 and 68, and at this time, the high level of the tail signal line TSL is applied to the D input of the D flip-flop 68 through the OR gate 66. Therefore, at the timing when the signal TRO of the C element C3 goes high, the output Q of the D flip-flop 68 goes high, and the last data word is applied to the parallel data buffer B3. Further, since the high level of its output Q is applied to the D input of the D flip-flop 68, this D flip-flop 68 is held at a high level until the next reset signal is applied.

At the moment when the outputs Q of the D flip-flops 64 and 68 both become high level, the output of the AND gate 76 becomes high level, and a stop signal 5TOP is sent to the C element C3.
(Figure 7) is given. Therefore, the next data packet cannot be transferred from parallel data buffer B4 to parallel data buffer B3 until this stop signal, ie, the output of AND gate 76, returns to a low level.

After that, the previous header is parallel data buffer B.

, the associated header signal line HS
L, becomes high level. When the signal TRO of the C element co becomes high level, the D flip-flop 6
The output Q of 0 changes from low level to high level, and its header is sent to the parallel data buffer B in the previous stage. Transferred to I.

When the output Q of the D flip-flop 60 becomes high level, a high level reset signal is applied to the D flip-flop 64 through the OR gates 72 and 74, so that both of its outputs Q become low level, and the output of the AND gate 76, i.e. The stop signal for C element C3 also becomes low level. Therefore, at this point, the transfer of a new data packet to the parallel data buffer B3 is allowed, and the D flip-flop 60 itself also
The next moment it is reset through the OR gate 70 and the circuit 48 returns to its initial state.

The identification data previously latched in the register 78 remains on the header signal line H3L until the header of the next data packet is output from the parallel data buffer B4 toward the parallel data buffer B3.

2 is held until it becomes high level again. Therefore, in the embodiment of FIG. 10, the identification data given to the comparison circuit 56 (FIG. 9) is held until the data is transferred between the four stages of parallel data buffers, and the identification data in the comparison circuit 56 is This makes it easier to compare.

FIG. 11 is a block diagram showing another example of the identification data detection circuit that can be applied to the embodiment of FIG. 9. Also in FIG. 11, like FIG. 10, only the first identification data detection circuit 52 for extracting identification data from the first data transmission path 28 is illustrated and explained.

In FIG. 11, the identification data detection circuit 52 includes a parallel data buffer 1B2 included in the first data transmission path 28.
* B3 t Includes a multiplexer 58 that receives data from B4 and B5. That is, multiplexer 5
8 receives the outputs of the four parallel data buffers 82 to B5 when the data packet i is transferred from the subsequent parallel data buffer to the preceding parallel data buffer.

A header signal line H3L is connected to the 17th bit of each of the parallel data buffers B and B5, that is, one bit of the order code. The header signal line H3L between the parallel data buffers B and B2 is applied to the multiplexer 58, and is inverted by an inverter and applied to one input of the analog signal line H3L. Header signal line H8L2 connected between parallel data buffers B2 and B3 is applied to the other input of AND gate Gl. The output of AND gate G1 is applied to multiplexer 58, inverted by an inverter, and applied to one input of AND gate G2. A header signal line H3L3 connected between parallel data buffers B3 and B4 is applied to the other input of the parallel data buffer G2. The output of AND gate G2 is applied to multiplexer 58, inverted by an inverter, and applied to one input of two-person AND gate G3.

The other input of this AND gate G3 is connected to a header signal line H8 connected between parallel data buffers B4 and B.
The output of L4 is given and the output is sent to multiplexer 58.
given to.

These header signal lines H3L and AND gates 01~
The output of G3 is provided as an enable signal to a corresponding latch circuit (not shown) included in multiplexer 52.

In the initial state, the identification data extracted from the first data transmission path 28 is supplied from the multiplexer 58 to the comparison circuit 56 (FIG. 6) through the identification data line.
All header signal lines H3L, -H3L4 are at low level. When the header of the data packet is transferred from the subsequent parallel data buffer to the parallel data pan and Fa B5,
Header signal line H3L4 becomes high level. On the other hand, header signal line H3 between parallel data buffers B4 and B3
L3 is still at a low level, so the output of AND gate G2 is at a low level. Since this low level is inverted and applied to AND gate G3, at this point, a high level is output from AND gate G3.

When the output of AND gate G3 goes high, the corresponding launch circuit included in multiplexer 58 is enabled and the identification data from the identification data line between parallel data buffers B5 and B4 is latched into its latch circuit.

Thereafter, when the C element C5 detects that the parallel data buffer B4 is empty, the header of the data packet is transferred from the parallel data buffer B5 to this parallel data buffer B4. In response, header signal line H3L3 goes high, and the output of AND gate G2 goes high in the same way as AND gate G3. The high level output of this AND gate G2 is inverted and the AND gate G3
Therefore, the output of AND gate G3 changes to low level. On the other hand, the AND gate G2 acts as an enable signal for the corresponding latch circuit included in the multiplexer 58, and at that timing, the parallel 11 data buffer B4
The identification data included in the header transferred from the data buffer B3 to the parallel data buffer B3 is taken in.

By repeating this process, parallel data buffer B2
When the header of a data packet is transferred from the parallel data buffer B3, the header signal line H5L becomes high level. Therefore, the output of AND gate G becomes low level like AND gates G2 and G3. When header signal H3L goes high, a corresponding latch circuit included in multiplexer 58 is enabled, and the identification data included in the data packet from parallel data buffer B2 is written into the latch circuit. That is, the same identification data is sequentially written into the four latch circuits (not shown) of the multiplexer 58 while the data packet is transferred in the four registers. Therefore, during that period, the multiplexer 58 continues to output the same identification data. In this way, multiplexer 58 can be used to hold identification data for a fixed period of time. In this manner, in this embodiment, when any of the header signal lines H3L to HSL4 is at a high level, the identification data existing at the earliest stage among them is selected.

When the header of the data packet is transferred from the parallel data buffer B2 to the first stage parallel data buffer B1, and the subsequent data word other than the header is transferred to the parallel data buffer B2, the header signal line H3LI becomes low level again. , if any of the header signal lines H3L, ~H5L4 is at a high level due to the header of the subsequent data packet, the circuit configuration described so far will cause the header signal lines H3LI~f (the first stage of SL4 to Existing identification data will be selected.

In the example of FIG. 10, while the identification data detection circuit holds the identification data in the data packet, data transfer of other data packets in the data packet pair detection section of the corresponding data transmission path is stopped. Although time is wasted, the example shown in FIG. 11 is efficient because data shifting on the data transmission path is not stopped.

In the example of FIG. 11, the number of stages of parallel data buffers through which the multiplexer 58 receives data can be arbitrarily set depending on the required time.

FIG. 12 is a block diagram showing another embodiment of the invention. The firing section 27 of this embodiment includes a data packet pair detection circuit 48 and a new data packet generation circuit 50,
In particular, the new data packet generation circuit 50 has a feature. The new data packet generation circuit 50 of this embodiment includes a stop circuit 80. It includes a merging circuit 82 and a packet recombination circuit 84. The stop circuit 80 includes a data packet pair detection and output circuit 4.
A match signal from a comparator circuit 56 (FIG. 6) included in 8 is provided. The stop circuit 80 further includes header signal lines H3L2 . and the header signal line H8L2 between the parallel data buffers B13 and B14 of the self-running shift register that constitutes the second data transmission path 34.
A header signal from □ is given. Furthermore, C elements C corresponding to parallel data buffers B3 and BI3, respectively.
A signal TRO from CI3 and CI3 is provided. The stop circuit 80 provides a stop signal 5TOP (FIG. 6) to the preceding C elements C2 and CI2, and also provides a merging control signal to the merging circuit 82. The packet recombination circuit 84 is inserted into the first data transmission path 28 and reassembles a pair of data packets provided from the first data transmission path 28 and the second data transmission path 34 into one new data packet. The rearranged new data packet is sent onto the first data transmission path 28. The merging circuit 82 controls the merging of new data packets into the first data transmission path 28 by the packet recombination circuit 84 .

Referring to FIG. 14, the stop circuit 80 includes an OR gate 86
and one input comparison circuit 5 of this OR gate 86.
6 (Fig. 6) and its output is 2
It is applied to one input of each of two AND gates 88 and 90. The other input of the AND gate 88 has the 13th
Header signal line H5L2. shown in the figure. The header signal from the header signal line H8L2□ is applied to the other input of the AND gate 90. The outputs of AND gates 88 and 90 are both provided through OR gates 92 and 94 as D inputs of D flip-flops 96 and 98, respectively. The clock input of this D flip-flop 96 is given the signal TRO from the C element C3 associated with the first data transmission line 28, and similarly, the clock input of the D flip-flop 98 is given the signal TRO from the C element C3 associated with the first data transmission line 28. Signal TRO from C element CI3 of transmission line 34 is applied. The outputs Q of D flip-flops 96 and 98, respectively, are connected to OR gates 92 and 9.
4 as its own D input and as the remainder input of OR gate 86.

The output Q of D flip-flop 96 is applied as is to one input of each of AND gates 100 and 102, and is inverted by an inverter and applied to one input of AND gate 104. In addition, the output Q of the D flip-flop 98 is directly connected to the AND gate 100.
and 104, is inverted by an inverter, and is applied to the other input of AND gate 102. The output of the AND gate 102 is given as a stop signal to the C element C2 of the first data transmission line 28,
The output of the AND gate 104 is applied to the C element CI2 of the second data transmission path 34 as a stop signal 5TOP. Furthermore, the output of the AND gate 100 is given to the merging circuit 82 as a merging control signal.

The D flip-flop 98 is connected to the first data transmission path 28
The signal AKI applied to the above-mentioned C element C2 included in is applied to the reset inputs of D flip-flops 96 and 98 as a stop release signal.

The merging circuit 82 receives the merging control signal from the stop circuit 80, and the merging control signal is inverted and sent to the AND gates 106,1.
08 and 116, and directly to one input of AND gate 114. The other input of the AND gate 106 is given the signal TPO from the C element C2 included in the first data transmission path 28. Further, the other input of the AND gate 108 receives a signal T from the C element CI2 included in the second data transmission path 34.
RO is given. The output of the AND gate 106 is given to one input of the OR gate 112, and the other input of the OR gate 112 is given to the C element C2 and the C element CI.
The output of an AND gate 110 to which the signal TR○ from □ and the merging control signal are applied. orgate,
The output of 112 is given to the C element further upstream of the first data transmission path 28. Similarly, and gate 108
The output of is also given to the C element in the previous stage included in the second data transmission path 34. The signal AKO from the C element included in the first data transmission path 28 is
4, and the second data transmission line 34
The signal AKO from the C element in the previous stage is applied.

The outputs of these two AND gates 114 and 116 are both applied to the C element C1° included in the second data transmission path 34 through an OR gate 118.

When the header of the data packet is transferred to the parallel data buffer B4 of the first data transmission line 28, the header signal line H
3L2. becomes high level, and at this time, when a high level coincidence signal is obtained from the comparison circuit 56 (FIG. 6) included in the data packet pair detection circuit 48, the two outputs of the AND gate 88 of the stop circuit 80 both become high level. ,D
The D input of the flip-flop 96 becomes high level. Then, when the signal TRO from the C element C3 corresponding to the parallel data buffer B3 becomes high level, that is, when this header is transferred to the parallel data buffer B3,
D flip-flop 96 is set and its output Q goes high. Further, when the header is transferred to the parallel data buffer BI4 included in the second data transmission path 34, the header signal line H8L2□ becomes high level, and if the above-mentioned match signal is obtained at this time, the signal from the C element CI3 is D flip-flop 98 is set in response to signal TPO. That is, the D flip-flops 96 and 98 are connected to the parallel data buffer B3 of the first data transmission path 28 and the parallel data buffer BI of the second data transmission path 34.
3 is set when the headers of data packets to be paired arrive, and the faster one is sent first. The D flip-flops that are not set are always set when the header arrives. That is, D flip-flops 96 and 98 will hold the match signal from comparison circuit 56 of data packet pair detection circuit 48.

If one D flip-flop 96 is set and the other D flip-flop 98 has not yet been sent, that is, the corresponding header has not arrived at the parallel data buffer B13 of the second data transmission path 34, then the -) 102 both become high level, and therefore the stop signal 5TOP to the terminal Tb (FIG. 7) of C element C2 becomes high level. Then, this C element C2 will be in a stopped state.

Conversely, when the D flip-flop 98 is set and the D flip-flop 96 is not sent, that is, when the corresponding header has not arrived at the first data transmission path 28, the AND gate 104 outputs the stop signal 5TOP. , Therefore, data transmission on the second data transmission path 34 is stopped.

In this way, the stop circuit 80 synchronizes the packets to be paired.

Next, the two D flip-flops 96 and 98 are both set, that is, the parallel data buffer B3
When the corresponding headers have arrived at both AND gates 102 and 104, one input of both AND gates 102 and 104 becomes low level, and the stop signal 5TOP becomes low level. Then, both of the two inputs of the AND gate 100 become high level, and a high level merging control signal is output to the merging circuit 82. Therefore, one input of AND gate 114 included in confluence circuit 82 becomes high level, and conversely, one input of AND gate 116 becomes low level. Therefore, from the OR gate 118, the signal AK is not sent from the C element of the second data transmission path 34, but from the C element included in the first data transmission path 28.
O is output, and this signal is transmitted to C of the second data transmission line 34.
It is given as signal AKI of element CI2. At the same time, one input of the AND gate 108 becomes low level, and the signal TR is transmitted from the C element CI2 to the C element in the previous stage.
O becomes low level. Furthermore, since the merging control signal is at a high level, the output of the AND gate 11o is enabled as an input to the OR gate 112. Therefore, when both the signals TPO of the C element C2 of the first data transmission path 28 and the C element CI2 of the second data transmission path 34 are at high level, the OR gate 112 A high-level signal TRO is applied to the C element at the previous stage. Therefore, from then on, the data packets on the second data transmission path 34 are provided to the packet recombination circuit 84 provided in the first data transmission path 28 and disappear from the second data transmission path 34.

In the data packet recombination circuit 84, the packets are recombined and a new data packet is output as the first data packet.
on the data transmission path 28, the stop circuit 80
A high level deactivation signal is applied to reset both D flip-flops 96 and 98, thus disabling new data packet generation circuit 50.

In this way, a match between data packets to be paired is detected, and one new data packet is generated.

[Brief explanation of drawings]

FIG. 1 is a conceptual system diagram showing an example of a data processing device in which the present invention can be implemented. FIG. 2 is a schematic block diagram showing the principle of a novel data processing device that forms the background of this invention. FIG. 3 is a diagram showing an example of a data packet, and FIG. 3(A) and FIG. 3(B) each show a different example. FIG. 4 and FIG. 5 are conceptual diagrams each illustrating the generation of one new data packet from data packets to be paired. FIG. 6 is a block diagram showing an example of a data processing device that is the background of the present invention. FIG. 7 is a circuit diagram showing an example of the C element. FIG. 8 is a timing diagram for explaining the circuit of FIG. 7. FIG. 9 is a block diagram showing one embodiment of the present invention. FIG. 10 is a block diagram showing an example of an identification data detection circuit applicable to the embodiment of FIG. 9. FIG. 11 is a block diagram showing another example of the identification data detection circuit applicable to the embodiment of FIG. 9. FIG. 12 is a block diagram showing another embodiment of the invention. FIG. 13 is a circuit diagram showing an example of the stop circuit of the embodiment shown in FIG. 12. FIG. 14 is a circuit diagram showing an example of the merging circuit of the embodiment shown in FIG. 12. In the figure, 27 is a firing section, 28 is a first data transmission path, 34 is a second data transmission path, 36 is a firing detection section, 48
50 is a data packet pair detection circuit, 50 is a new data packet generation circuit, 52.54, 52, ~52n are identification data detection circuits, 56.56, ~56n are comparison circuits, 58 is a multiplexer, and 64.68 is a D fliptub. A flop 78 indicates a latch register. Patent applicant Sanyo Electric Co., Ltd. (3 others) Agent Patent attorney Yama 1) Yoshito (1 idiot) Figure 1 Figure 2 Mouse Figure 3 (B) Figure 5

Claims (1)

[Scope of Claims] 1. A first data transmission line for transmitting data packets including identification data and configured using a shift register; a second data transmission path configured by: a first identification data extraction means for extracting the identification data of the data packet transmitted on the first data transmission path; second identification data extracting means for extracting the identification data of the data packet, holding means for holding the identification data extracted by the first and second identification data extracting means for a predetermined time; a comparison means for comparing two pieces of held identification data; and a data packet on the first data transmission path and a corresponding data packet on the second data transmission path according to the output of the comparison means. A data processing device comprising new data packet generation means for generating one new data packet. 2. The data processing device according to claim 1, wherein the holding means holds the identification data while the identification data is transmitted in multiple stages on the first and second data transmission paths. 3. The holding means includes means for outputting a signal while the identification data is transmitted in multiple stages and means for latching the extracted identification data during the duration of the signal. 2. The data processing device according to item 2. 4. The data processing device according to claim 2, wherein the holding means includes a multiplexer for outputting only the identification data that exists in the first stage among the plurality of stages. 5. At least one of the first and second data transmission paths is formed in a loop shape, and the data packet is circulated around the loop-shaped transmission path.
5. The data processing device according to any one of Items 4 to 4. 6. In response to the identification data detecting means detecting specific identification data transmitted through one of the first and second data transmission paths, 6. A data processing device according to claim 1, further comprising means for waiting for a data packet to arrive. 7. The data processing apparatus according to claim 6, wherein the waiting means includes stopping means for stopping shifting of the one data transmission path. 8. The data processing device according to claim 1, wherein the data packets are transmitted in opposite directions on the first and second data transmission paths. 9. The data processing device according to any one of claims 1 to 8, wherein each of the shift registers forming the first and second data transmission paths is configured as a self-propelled shift register. .