JPS61278938A - Data processor - Google Patents

Abstract

PURPOSE:To generate a new data packet at a high speed and to facilitate jointing said packet to asynchronizing data transmission line by detecting data paired when data is transmitted on the transmission line and employing a self- traveling type shift register for the transmission line. CONSTITUTION:The 1st and 2nd loop-like data transmission lines 28 and 34 are provided with parallel data buffers B1-B5 and B11-B15, which comprise the self-traveling type shift register. Identification data detecting circuits 52 and 54 extract identification data from the data on the transmission line, and a comparator circuit 56 detects the coincidence of said data. When the coincidence of two-type of indentification data is detected, the comparator circuit 56 gives a control signal to a new data packet generating circuit 50. It fetches the detected data packet to be paired, and generates one new data packet.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a data processing device, and particularly to a data processing device that generates one new data packet from two data packets, such as a firing section of a data-driven data processing device. The present invention relates to a data processing device.

(Prior Art) Neumann type data processing apparatuses have drawbacks such as slow speed and difficulty in parallel processing due to sequential processing. Therefore, recently, data driven type (data flow type) data processing apparatuses have been proposed and implemented. An example of such a data-driven data processing device is disclosed, for example, in Nikkei Electronics, published on April 9, 1980, pages 181 to 218.

In conventional systems, for firing detection, data packets are waited for from a data bus, stored in memory,
The identifier or identification data of the data packet stored in the waiting memory is searched to find the data packet to be paired with.

(Problems to be Solved by the Invention) In the conventional system, it takes a very long time to store data in the queue memory and search for identification data therein1.2. It was slowing down.

Therefore, the main object of the present invention is to provide a data processing device that can more quickly find a data packet to be paired with.

(Means for Solving the Problems) Simply put, the present invention provides a first method for transmitting data packets including identification data in opposite directions, and configured in a loop using a shift register. and identification data detection means connected to the second data transmission path, the first and second loop-shaped data transmission paths, and for detecting identification data included in data packets transmitted through each of them;
Pairing determining means for comparing the identification data detected by the identifying data detecting means to determine data packets to be transmitted on the first and second loop-shaped data transmission paths and forming a pair; and discrimination by the pairing determining means. The data processing apparatus includes new data packet generation means for generating one new data packet from two data packets that have been processed.

(Operation) Data packets are transmitted individually and in opposite directions on the first loop-shaped data transmission path and the second loop-shaped data transmission path. The identification data detection means is
Identification data is extracted from data packets transmitted on each loop-shaped data transmission path. The pair determining means thus compares the two extracted identification data and finds data packets that are to be paired and are being transmitted on the two loop-shaped data transmission paths. When a data packet of the other party to be paired is detected, the first and second
The data packet is given to the new data packet generation means from the data transmission path. The new data packet generation means processes the two supplied data packets in a predetermined manner to generate one new data packet. This new data packet is then brought to the main data transmission path for later processing, such as arithmetic processing.

(Effects of the Invention) According to the present invention, data packets to be paired are detected while data is transmitted in opposite directions on the first and second loop-shaped data transmission paths. Compared to those that use a waiting memory,
Detection of identification data becomes much faster and new data packets can be generated faster. Therefore, the data processing apparatus as a whole can be configured as a faster system.

Furthermore, if a self-propelled shift register is used as such a data transmission path, it will be easy to connect it to the asynchronous main data transmission path, making its benefits even more effective when configured as a data-driven data processing device. It can be demonstrated.

The above objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

(Embodiment) FIG. 1 is a conceptual system diagram showing an example of a data processing device in which the present invention can be implemented. The system 10 includes an asynchronous delay line ring 12 as a data transmission path, a data packet to be processed is given to the asynchronous delay line ring 12 through a merging section 14, and the processed data is outputted through a branching section 16. be done. Confluence part 1
The data packet given from 4 passes through the asynchronous delay line ring 12, is branched by the branching section 18, and is given to the function storage section 20. The data read from the function storage section 20 is given to the asynchronous delay line ring 12 again through the merging section 22.

For example, as shown in FIG. 3(A), the data packet given from the function storage unit 20 includes a header HD and a plurality of data words DW following the header HD.

~DWn included. The header HD includes a processing code PC and a control code CC, and the processing code PC includes a code indicating a packet structure and a code indicating processing contents. The code indicating the packet structure is, for example, a header. For example, an order code indicating that the data word is the last data word or the last data word is given by the 17th and 16th two bits. The code that shows the processing content is
Especially called F code, such as r+J, r-J,
...or used to specify the type of processing, such as data replacement or insertion. In the control code CC,
It includes logical information such as physical optical information, node information resulting from the program structure, and color information.

The data packets as described above transmitted by the asynchronous delay line ring 12 are provided to a first loop-shaped data transmission line 28 forming a firing section 27, for example, through a branching section 24 and a merging section 26. Different data packets are taken into a second loop-shaped data transmission path 34 forming the firing section 27 through different branching sections 30 and merging sections 32 . The data packets applied to the first and second loop-shaped data transmission paths 28 and 34 are transmitted through the respective loops in opposite directions, and are applied to the firing detection section 36 that constitutes the firing section 27 together with these transmission paths. It will be done. The firing detection unit 36 compares the control codes included in the two data packets, thereby distinguishing between the data packet present on the first loop-shaped data transmission path 28 and the second data packet. A new data packet is generated based on the specific data packet detected as a data packet pair. The new data packet generated in this way is placed, for example, on the first loop-shaped data transmission path 28, and is placed at the branching section 38 and the merging section 40.
through and onto the asynchronous delay line ring 12 again.

A new data packet transferred on the asynchronous delay line ring 12 is transferred to the arithmetic processing unit 44 through the branching unit 42, for example.
and then processes the data to be processed contained in that data packet according to the processing code contained in the header of that data packet. The data processed by the arithmetic processing unit 44 is merged into the asynchronous delay line ring 12 again through the merge unit 46. This processing result is given again to the function storage section 20 or output through the branching section 16.

Note that the system 10 is further provided with a control command processing section and a color management section.

This invention is suitable as the firing section 27 of the system 10 shown in FIG. However, the present invention is generally applicable to all data processing devices that need to find the data of the other party to form a pair and generate one piece of new data from the data of that pair. Let me point this out in advance.

FIG. 2 is a schematic block diagram illustrating the principle of this invention. In FIG. 2, for convenience, the first and second loop-shaped data transmission paths 28 and 34 are shown as transmitting data in the same direction, but as shown in FIG. It is used for data transmission.

First and second loop-shaped data transmission lines 28 and 3
4 is a shift register, preferably a self-propelled shift register. As will be explained in detail later, a self-propelled shift register is capable of independently and simultaneously pushing in and out data, and furthermore, the pushed in data can be transferred to the register in the next stage when it is empty. Therefore, in this and later embodiments, these first and second data transmission lines 28 and 34 are asynchronous loop-shaped data transmission lines. Constructed as.

Such first and second loop-shaped data transmission paths 2
8 and 34, data packets having the structure shown in FIG. 3 are transmitted in opposite directions to each other. Third
What is shown in Figure 3 (A) is that one data word contains one processing target data, and what is shown in Figure 3 (B) is where one data word contains multiple (two in this example) data.
Contains data to be processed.

First and second loop-shaped data transmission lines 28 and 3
4 is connected to an firing detection section 36, and this firing detection section 36 includes a data packet pair detection circuit 48 and a new data packet generation circuit 50. The data packet pair detection circuit 48 detects the control code C from the data packets transmitted through the first and second data transmission paths 28 and 34.
By extracting the identification data included in C (FIG. 3) and comparing the two extracted identification data, the data packet of the other party to be paired is detected.

When a data packet pair is detected, the data packet pair detection circuit 48 provides a signal to the new data packet generation circuit 50. In response, the new data packet generation circuit 50 takes in each data packet containing the detected identification data. Then, one new data packet is generated from the two captured data packets and output.

To explain in more detail, as shown in FIG.
Data packets DP I and DP2 with the configuration shown in A)
are transmitted on the first and second data transmission paths 28 and 34, respectively. From these data transmission lines 28 and 34, identification data IDI and ID
2 is provided to data packet pair detection circuit 48. Then, these two identification data IDI and ID2 are extracted and compared. These two identification data I
If DI and ID2 have a certain relationship, for example, if node information in the program structure matches, this will be detected by the comparison circuit. In this way, the data packet pair detection circuit 48 identifies data packets DPI and DP2 as being paired with each other. The new data packet generation circuit 50 reads out the thus identified data packets DPI and DP2 from the first and second data transmission paths 28 and 34, respectively, and generates one new data packet DP. This new data packet has a data packet structure as shown in FIG. 3(A).

Further, as shown in FIG. 5, data words (DP1 and DP2) having the structure as shown in FIG. 3(B) are transmitted on the first and second data transmission paths 28 and 34, respectively. It is assumed that there is

In the same way as in Figure 4, the data packet DPI
and identification data IDI and ID2 included in DP2
are compared and 5. When the certain association is detected, the new data packet generation circuit 50 generates one new data packet DP as shown in FIG. In the example shown in Fig. 5, the new data transmission path) DP is as shown in Fig. 3 (B).
It has the structure shown in

FIG. 6 is a block diagram showing one embodiment of the present invention.

In this embodiment as well, the first and second data transmission lines 28 and 34 are shown as being in the same direction as in FIG. 2, but of course they are constructed as loops in opposite directions. Further, in this embodiment, both the first and second loop-shaped data transmission paths 28 and 34 are configured as a self-running shift register. The free-running shift register constituting the first data transmission path 28 includes a plurality of parallel data buffers B connected in cascade.

~B, and their respective parallel data buffers B,
~B, corresponding to C element (Coincident El
e++ent) including C1 to C6. Similarly, the second
The self-running shift register constituting the data transmission path 34 includes cascade-connected parallel data buffers Bll-B, 5 and their corresponding C elements C3,-CI5.
including.

Here, with reference to FIGS. 7 and 8, the C element constituting the asynchronous self-propelled shift register will be described. C
Element C includes six terminals T, -76, and terminal T receives a signal TRI (Transfer
In ) is given, and from terminal T2, a signal A KO (Acknowledge Ou
t) is output. A signal T RO (Transfer 0ut) is output from the terminal T3 to the C element in the previous stage, and a signal AK r from the C element in the previous stage is output from the terminal T4.
(Acknowledgement In) is given.

Signal TRO is further given to its corresponding parallel data buffer as a transfer command signal. And signal AK
I is given as an empty signal of the preceding stage parallel data buffer.

Note that a reset signal RESET is applied to the terminal T5, and a stop signal 5TOP is applied to the terminal T6.

In the circuit shown in FIG. 7, the reset signal RE is sent from the terminal T5.
When SET is given, it is inverted by an inverter and this signal is given to four Nant gates GI
, G4 * G l l and G,4, both become high level. Nantes Gate G,,G4. The outputs of G, and CI4 are at high level, and therefore the outputs of G3 and G13 (which receive them) are both at low level. The high level output of the Nandt gate G4 becomes the signal AKO, which is given as the signal AKI from the terminal T2 to the C element at the subsequent stage. This is a signal representing the empty state of the preceding stage parallel data buffer. At this time,
Assuming that the data has not yet arrived, the signal TRI to terminal T is at low level. When the reset signal RESET to terminal T5 is released, the output of the inverter goes to high level, while the signal from NAND gate G14 is at low level. signal AK
' is also at a high level, and this state is the initial state.

In the initial state, therefore, the two inputs of each of Nant gates G and GII are at high level, and one input of OR gates G2 and Gl□ is at high level. Therefore, 2 of Nant Gate G3 and CI3
Both inputs are at high level, so the outputs of Nant gates G3 and CI3 are both at low level. That is, signal TR' and terminal T3
The signal TPO from is at low level. Nantes Gate G
The inputs of 4 and CI4 are low level, high level, and high level, respectively, and these Nant gate G
The outputs of 4 and Cr14 are each at high level.

When the data is transferred and the signal TRI applied to the terminal T from the C element in the subsequent stage changes to high level as shown in FIG. 8, all three inputs of the Nant gate G1 become high level, and its output becomes low level. Then, the output of the Nant gate G3, that is, the signal TR' becomes high level as shown in FIG.
The output of No. 4 becomes low level. When the signal TR' becomes a high level, the outputs of the Nant gates G, , become a low level, the output TRO of the Nant gates G,3 becomes a high level, and the output AK' of the Nant gate G14 becomes a low level. The outputs of the Nant gates G4 and G,4 are returned to the inputs of the Nant gates G3 and CI3, respectively, and the outputs of these Nant gates G3 and G13 are locked at a high level.

In this way, as shown in FIG. 8, the signal AKO from the terminal T2 becomes low level, indicating that data has been transferred to the corresponding parallel data buffer of this C element C. In other words, in that state, data transfer is no longer possible. The fact that no Uke is to be added is communicated to the subsequent C element. Also, Nantes Gate GI
3 is at high level, and from terminal T3, the previous stage C
A high level signal TRO is applied to the element. This high level signal TRO is given as a transfer command to the corresponding parallel data buffer, and the data in the parallel data buffer is sent to the previous stage.

When the signal AKO becomes low level, the signal TRI becomes low level as shown in FIG. 8, and therefore the output TR' of the Nant gate Gr returns to high level. moreover,
As described above, as the output AK' of the Nandgate game hG+4 changes to the low level, the output AKO of the Nandest gate G4 returns to the high level, and the output TR' of the Nandgate gate G3 returns to the low level.

When the signal AKO from the C element in the previous stage, that is, the signal AKI applied from the terminal T4, changes from high level to low level as shown in FIG. 8, that is, when the empty space in the parallel data buffer in the previous stage is extracted, Or game) CI2
Since the input of is at low level and the signal TR' is also at low level, the output of this OR game 1-G, □ is also at low level. At this time, the output of Nant gate GI3 is at high level, so Nant gate G.

4 output changes to high level. Therefore, the input of the Nant gate G13 becomes high level, and the output of this Nant gate G13 changes to low level. In this way, the state returns to the same state as the initial state.

If the signal AKO from the previous-stage C element, that is, the signal AKI from the terminal T4, remains at a low level, that is, if the parallel data buffer corresponding to the previous-stage C element is not yet empty, then the Nant gate Nant gate G11 Since one input of the terminal T1 remains at a low level, even if the signal TRI from the terminal T1 is given as a high level and the signal TR' changes to a high level, the NAND game +-
Since C3 does not function and the signal TPO does not go high, acceptance of data from the subsequent stage is refused, and therefore data cannot be transferred to the parallel data buffer corresponding to this C element in this state.

In addition, a stop signal 5TOP is applied to this C element C from the terminal T6.
is given, the high level signal is the OR gate G
5 to Nantes Gate GI3. Therefore, the output of this Nant gate G13 becomes a low level, and in this state, the signal TPO from the terminal T3 becomes a low level, which is transmitted to the C element in the previous stage, and the data transfer is stopped. As shown in the figure, loop-shaped data transmission paths 28 and 3 are formed by parallel data buffers B, -B5 and C elements C1 to C5, and by parallel data buffers Bll to B+5 and C elements C1 to C15, respectively.
Four asynchronous free-running shift registers are constructed.

(Left below) Returning to FIG. 6, from the data transmission paths from the respective parallel data buffers B4 and BI4, which constitute the first and second loop-shaped data transmission paths 28 and 34, to the parallel data buffers B3 and B13. , and data lines extend from the data lines to supply respective data to identification data detection circuits 52 and 54 included in data packet pair detection circuit 48. This identification data detection circuit 52
At step 54, identification data is extracted from the header of the data packet (FIG. 3) and provided to the comparison circuit 56. The comparison circuit 56 compares the two pieces of identification data provided and determines whether they match or do not match. When the comparison circuit 56 detects a match between the two identification data, the data packet to be paired is determined based on the match, and a control signal notifying this is given to the new data packet generation circuit 50.

First and second loop-shaped data transmission lines 28 and 3
From the transmission path from parallel data buffers B3 and B13 that constitute 4 to parallel data buffers B2 and B1□,
A transmission path extends to the new data packet generation circuit 50. Based on the match signal or control signal from the comparison circuit 56, the new data packet generation circuit 50 takes in the determined specific data packet to be a pair through the data packet line. Then, the new data packet generation circuit 50 combines the two data packets,
Create one new data packet. The new data transmission line I-DP (FIG. 4 or 5) generated in this way by the new data packet generation circuit 50 is used for later processing, for example, main data transmission. In the embodiment shown in FIG. 6, the identification data/event detection circuits 52 and 54 pass data packets from parallel data buffers B4 and B14 to parallel data buffer B3. and BI3 must detect the identification data within a relatively short period of time and compare it in comparison circuit 56 within that time. Therefore, depending on the data transmission speed in the data transmission lines 28 and 34, a detection error may occur.

Therefore, it is conceivable to adopt a configuration in which the identification data detection circuits 52 and 54 hold the identification data of the data packet for a certain period of time.

FIG. 9 is a schematic block diagram showing another embodiment of the invention. The ignition section 27 of this embodiment includes an ignition detection section 36 connected to the first and second data transmission paths 28 and 34, as in the previous embodiment of FIG. The firing detection section 36 includes a data packet pair detection circuit 48 and a new data packet generation circuit 50. The data packet pair detection circuit 48 includes an identification data detection circuit 52 for detecting identification data from data packets transmitted on the first loop data transmission path 28 and a second loop data transmission path 34. includes an identification data detection circuit 54 for detecting identification data from a data packet transmitted. The two identification data thus detected are compared by a comparison circuit 56. The comparison circuit 56 provides a control signal to the new data packet generation circuit 50 when the two match or are in a certain relationship.

In this embodiment, data packet pair detection sections 28a and 34a of a certain length are defined in the first and second loop-shaped data transmission paths 28 and 34, and data packet pair detection sections 28a and 34a are formed from these data packet pair detection sections 28a and 34a. The same identification data is extracted for a relatively long period of time to facilitate comparison in the comparator circuit 56.

FIG. 10 is a block diagram showing an example of an identification data detection circuit applicable to the embodiment of FIG. 9. In this Figure 10,
A first device that detects identification data from the first data transmission path 28.
Although only the identification data detection circuit 52 of FIG.

The self-running shift register constituting the first loop-shaped data transmission path 28 includes cascade-connected parallel data buffers B
OI, BO'''B4 and their related C elements C
8I + co "'C4. Each parallel data buffer B. l + BO""The 17th bit of B4 is the header signal line H3L, and the 16th bit is the tail signal line TSL. The header signal line H3L+1 between parallel data buffers BQ l and B. is given to the D terminal of the D flip-flop 60, and the header signal line H3L, □ between parallel data buffers B3 and B4 is connected to , is applied to the D input of the D flip-flop 64 through the OR gate 62.The tail signal line TSL, 2 between the parallel data buffers B3 and B4
is applied to the D input of a D flip-flop 68 through an OR gate 66.

The clock input of the D flip-flop 60 is C.
A signal TRO from element C6 is provided. An OR gate 70 is connected to the reset input of this D flip-flop 60.
An initial reset signal is applied through the circuit, and its own output Q is applied thereto. The output Q of the D flip-flop processor 0 is also applied through OR gates 72 and 74 to the positive inputs of D flip-flops 64 and 68, respectively, along with an initial reset signal.

The output Q of the D flip-flop 64 is applied to the other input of the above-mentioned OR gate 62 whose output is applied to its own D input, and also applied to one input of the AND gate 76 . The output Q of the D flip-flop 68 is given to the other input of this AND gate 76, and this output Q is
Further, the output thereof is applied to the other input of the OR gate 66, which is applied to its own D input.

A header signal line is taken out from the transmission line from parallel data buffer B4 to parallel data buffer B3, and this header signal line is applied to register 78. This register 7
The output Q of the aforementioned D flip-flop 64 is applied to the clock input of 8. The output of this register 78 is then used as the detected identification data by the comparator circuit 56 (sixth
Figure) is given.

In the initial state, a high level initial reset signal is applied. This initial reset signal is 70.
Through 72 and 74, D flip-flop 60.6
Accordingly, these D flip-flops 60, 64 and 6 are reset, and their respective data Q becomes low level. This state is the initial state.

When the parallel data buffer B3 is detected to be empty by the associated C element C3, data packets begin to be transferred from the parallel data buffer B4 to this parallel data buffer B3. When a data packet or its header is transferred from parallel data buffer B4 to parallel data buffer B3, the header signal line H3L+2 between them goes high. With the start of such data packet transfer, the signal TRO from the C element C3 changes from low level to high level. Then, this high level signal is applied to each clock input of the D flip-flops 64 and 68, and the D flip-flop 64 receives the high level signal.
The high level of the header signal line H5L, □ applied to the input is written to this D flip-flop 64, and the output Q of the D flip-flop 64 changes from low level to high level. The high level output from this D flip-flop 64 is given as an enable signal to the register 78, and the identification data included in the header output from the parallel data buffer B4 is launched into the register 78 accordingly. Then, the header is also transmitted to the parallel data buffer B3.

Thereafter, the D input of the D flip-flop 64 is fixed at a high level by the OR gate 62, and its output Q is held at a high level until the next reset signal R arrives.

After that, data transfer between parallel data buffers proceeds,
The last data word DW (FIG. 3) of the data packet begins to be transferred from parallel data buffer B4 to parallel data buffer B3. At this time, the tail signal line TSL changes to a high level, and the ci2 element C3 quickly outputs a high level signal TRO. This high level signal is applied to the clock inputs of D flip-flops 64 and 68, and at this time, the high level of tail signal line TSL is applied to the D input of D flip-flop 68 through OR gate 66. Therefore, at the timing when the signal TRO of C element C3 becomes high level, the output Q on 0297170716 becomes high level, and the last data word is given to parallel data buffer B3. Further, since the high level of its output Q is applied to the D input of the D flip-flop 68, this D flip-flop 68 is held at a high level until the next reset signal is applied.

At the moment when the outputs Q of the D flip-flops 64 and 68 both become high level, the output of the AND gate 76 becomes high level, and the stop signal 5TOP is sent to the C element C3.
(Figure 7) is given. Therefore, the next data packet cannot be transferred from the parallel data buffer B4 to the parallel data buffer B3 until the next stop signal, that is, the output of the AND gate 76 returns to low level. When the data is transferred to the data buffer B0, the associated header signal line Hst++
becomes high level. and signal TR of C element co l
When O becomes high level, the output Q of D flip-flop processor 0 changes from low level to high level, and its header is transferred to parallel data buffer B in the previous stage. Transferred to I.

When the output Q of the D flip-flop 60 becomes high level, a high level reset signal is applied to the D flip-flop 64 through the OR gates 72 and 74, so that both of its outputs Q become low level, and the output of the AND gate 76, i.e. The stop signal for C element C3 also becomes low level. Therefore, at this point, the transfer of a new data packet to the parallel data buffer B3 is allowed, and the D flip-flop 60 itself also
The next moment it is reset through the OR gate 70 and the circuit 48 returns to its initial state.

The identification data previously latched in the register 78 remains on the header signal line H3L until the header of the next data packet is output from the parallel data buffer B4 toward the parallel data buffer B3.

2 is held until it becomes high level again. Therefore, in this embodiment of FIG.
The identification data given to the comparator circuit 5 is held until the data is transferred between the four stages of parallel data buffers.
This makes it easier to compare the identification data in step 6.

FIG. 11 is a block diagram showing another example of the identification data detection circuit that can be applied to the embodiment of FIG. 9. Also in FIG. 11, like FIG. 10, only the first identification data detection circuit 52 for extracting identification data from the first data transmission path 28 is illustrated and explained.

In FIG. 11, the identification data detection circuit 52 includes parallel data buffers B2.
B3. It includes a multiplexer 58 that receives data from B4 and B5. That is, the multiplexer 58 has
When a data packet is transferred from the subsequent parallel data buffer to the previous parallel data buffer, the outputs of the four parallel data buffers 82 to B5 are input.

A header signal line H3L is connected to the 17th bit of each of the parallel data buffers 81 to B5, that is, one bit of the order code. Header signal line H3L between parallel data buffers B and B2 is applied to multiplexer 58, inverted by an inverter, and applied to one input of AND gate G1. Header signal line H8L2 connected between parallel data buffers B2 and B3 is applied to the other input of AND gate G+. The output of AND gate Gl is applied to multiplexer 58, inverted by an inverter, and applied to one input of AND gate G2. Header signal line H3L3 connected between parallel data buffers B3 and B4 is applied to the other input of AND gate G2.

The output of the two-man AND gate G2 is applied to a multiplexer 58, inverted by an inverter, and applied to one input of the two-man AND gate G3. The other input of AND gate G3 is supplied with the output of header signal line H3L4 connected between parallel data buffers B4 and B5, and the output is supplied to multiplexer 58.

These header signal lines H3L and AND gate G +
The output of ~G3 is provided as an enable signal to a corresponding latch circuit (not shown) included in multiplexer 52.

In the initial state, the identification data extracted from the first data transmission path 28 is supplied from the multiplexer 58 to the comparison circuit 56 (FIG. 6) through the identification data line.
All header signal lines H5L and -H3L4 are at low level. When the header of the data packet is transferred from the subsequent parallel data buffer to the parallel data buffer B5, the header (M line H3L4 becomes high level. On the other hand, the header signal line H3 between the parallel data buffers B4 and B3
L3 is still at a low level, so the output of AND gate G2 is at a low level. Since this low level is inverted and applied to AND gate G3, at this point, a high level is output from AND gate C3.

When the output of AND gate G3 goes high, the corresponding latch circuit included in multiplexer 58 is enabled and the identification data from the identification data line between parallel data buffers B5 and B4 is latched into that latch circuit.

Thereafter, when the C element C5 detects that the parallel data buffer B4 is empty, the header of the data packet is transferred from the parallel data buffer B5 to this parallel data buffer B4. In response, header signal line H3L3 goes high, and the output of AND gate G2 goes high in the same way as AND gate G3. The high level output of this AND gate G2 is inverted and the AND gate G3
Therefore, the output of AND gate G3 changes to low level. On the other hand, the AND gate G2 acts as an enable signal for the corresponding latch circuit included in the multiplexer 58, and at that timing, the identification data included in the header transferred from the parallel data buffer B4 to the parallel data buffer B3 is taken in.

By repeating this process, parallel data buffer B2
When the header of a data packet is transferred from the parallel data buffer B3, the header signal line H3LI becomes high level. Therefore, the output of AND gate Gl becomes low level, similar to AND gates G2 and G3. When the header signal H3L goes high, the corresponding latch circuit included in the multiplexer 58 is enabled, and the identification data included in the data packet from the parallel data buffer B2 is written into the latch circuit.

That is, the same identification data is sequentially written into the four latch circuits (not shown) of the multiplexer 58 while the data packet is transferred in the four registers. Therefore, during that period, the multiplexer 58 continues to output the same identification data. In this way, multiplexer 58 can be used to hold identification data for a certain period of time. In this manner, in this embodiment, when any of the header signal lines H3L to H3L4 is at a high level, the identification data existing at the earliest stage among them is selected.

When the header of the data packet is transferred from the parallel data buffer B2 to the first-stage parallel data buffer B, and the subsequent data word other than the header is transferred to the parallel data buffer B2, the header signal line HSL becomes low level again. , Therefore, if any of the header signal lines H3L and ~H8L4 is at a high level due to the header of the subsequent data packet, the circuit configuration described so far causes the header signal lines H3L and ~H3L4 to be set to a high level. The identification data that exists in will be selected.

In the example shown in FIG. 10, while the identification data detection circuit holds the identification data in the data packet, the data transfer of other data packets in the data packet pair detection section of the corresponding data transmission path is stopped. Although time is wasted, the example shown in FIG. 11 is efficient because data shifting on the data transmission path is not stopped.

In the example of FIG. 11, the number of stages of parallel data buffers through which the multiplexer 58 receives data can be arbitrarily set depending on the required time.

FIG. 12 is a block diagram showing another embodiment of the invention. The firing section 27 of this embodiment includes a data packet pair detection circuit 48 and a new data packet generation circuit 50,
In particular, the new data packet generation circuit 50 has a feature. The new data packet generation circuit 50 of this embodiment includes a stop circuit 80. The stop circuit 80, which includes a merging circuit 82 and a packet recombination circuit 84, includes a data packet pair detection circuit 48.
A match signal is provided from a comparator circuit 56 (FIG. 6) included in the circuit. The stop circuit 80 further receives a header signal from the header signal line H3L21 from the parallel data buffers B3 and B4 included in the self-running shift register constituting the first loop-shaped data transmission path 28, and a second signal from the header signal line H3L21. A header signal from a header signal line H3L2□ between parallel data buffers B13 and B14 of a free-running shift register forming a loop-shaped data transmission path 34 is applied.

Additionally, parallel data buffers B3 and B.

Signals TRO from C elements C3 and C10 respectively corresponding to C.3 are provided. The stop circuit 80 sends a stop signal 5TOP (sixth
) is provided, and a merging control signal is also provided to the merging circuit 82.

The packet recombination circuit 84 is inserted into the first data transmission path 28 and reassembles a pair of data packets provided from the first data transmission path '28 and the second data transmission path 34 into one new data packet. , and sends the rearranged new data packet onto the first data transmission path 28. The merging circuit 82 controls the merging of new data packets into the first data transmission path 28 by the packet recombination circuit 84 .

Referring to FIG. 14, the stop circuit 80 includes an OR gate 86
and one input comparison circuit 5 of this OR gate 86.
6 (Fig. 6) and its output is 2
It is applied to one input of each of two AND gates 88 and 90. The other input of the AND gate 88 has the 13th
A header signal from header signal line H3L21 shown in the figure is applied, and the other input of AND gate 90 is applied with a header signal from header signal line H3L2□. The outputs of AND gates 88 and 90 are both provided through OR gates 92 and 94 as D inputs of D flip-flops 96 and 98, respectively. The clock input of this D flip-flop 96 is given the signal TRO from the C element C3 associated with the first data transmission line 28, and similarly, the clock input of the D flip-flop 98 is given the signal TRO from the C element C3 associated with the first data transmission line 28. Signal TRO from C element CI3 of transmission line 34 is applied. The outputs Q of D flip-flops 96 and 98, respectively, are connected to OR gates 92 and 9.
4 as its own D input and as the remainder input of OR gate 86.

The output Q of D flip-flop 96 is applied as is to one input of each of AND gates 100 and 102, and is inverted by an inverter and applied to one input of AND gate 104. In addition, the output Q of the D flip-flop 98 is directly connected to the AND gate 100.
and 104, is inverted by an inverter, and is applied to the other input of AND gate 102. The output of the AND gate 102 is given as a stop signal to the C element C2 of the first data transmission line 28,
The output of the AND gate 104 is applied to the C element CI2 of the second data transmission line 34 as a stop signal 5TOP. Furthermore, the output of the AND gate 100 is given to the merging circuit 82 as a merging control signal.

The D flip-flop 98 is connected to the first data transmission path 28
The signal AKI applied to the above-mentioned C element C2 included in is applied to the reset inputs of D flip-flops 96 and 98 as a stop release signal.

The merging circuit 82 receives the merging control signal from the stop circuit 80, and the merging control signal is inverted and sent to the AND gates 106,1.
08 and 116, and directly to one input of AND gate 114. The signal TRO from the C element C2 included in the first data transmission path 28 is applied to the other input of the AND gate 1o6. Further, the other input of the AND gate 10B receives a signal T from the C element CI2 included in the second data transmission path 34.
PO is given. The output of the AND gate 106 is given to one input of the OR gate 112, and the other input of the OR gate 112 is given to the C element C2 and the C element CI.
The output of an AND gate 110 to which the signal TRO from □ and the merging control signal are applied. or gate 1
The output of C.12 is sent to the C.
given to the element. Similarly, the output of the AND gate 1.8 is also applied to the C element in the previous stage included in the second data transmission path 34. The signal AKO from the C element included in the first data transmission path 28 is applied to the other input of the AND gate 114, and the signal AKO from the C element in the previous stage of the second data transmission path 34 is applied. The outputs of these two AND gates 114 and 116 are both passed through an OR gate 118 to the second data transmission line 3.
It is given to C element CI2 included in 4.

When the header of the data packet is transferred to the parallel data buffer B4 of the first loop-shaped data transmission line 28, the header signal line HSL2. becomes high level, and at this time, when a high level coincidence signal is obtained from the comparison circuit 56 (FIG. 6) included in the data packet pair detection circuit 48, the two outputs of the AND gate 88 of the stop circuit 80 both become high level. , the D input of the D flip-flop 96 becomes high level. Then, when the signal TRO from the C element C3 corresponding to the parallel data buffer 1B3 goes high, that is, when this header is transferred to the parallel data buffer B3, the D flip-flop 96 is set and its output Q goes high. level. Further, the parallel data buffer BI4 included in the second loop-shaped data transmission path 34
When the header is transferred to , the header signal line H8L2□ becomes high level, and if the above-mentioned match signal is obtained at this time, the D flip-flop 98 is set in response to the signal TRO from the C element CI3. That is, the D flip-flops 96 and 98 are set when the headers of data packets to be paired arrive at the parallel data buffer B3 of the first data transmission path 28 and the parallel data buffer B13 of the second data transmission path 34. , whichever is faster is set. The D flip-flops that are not set are always sent when the header arrives. That is, D flip-flops 96 and 98 will hold the match signal from comparison circuit 56 of data packet pair detection circuit 48.

If one D flip-flop 96 is set and the other D flip-flop 98 is not yet set, that is, the corresponding header has not arrived at the parallel data buffer BI3 of the second data transmission path 34, The two inputs of gate 102 both go high, and therefore the stop signal 5TOP to terminal T6 (FIG. 7) of C element C2 goes high. Then, this C element C2 will be in a stopped state.

Conversely, when the D flip-flop 98 is set and the D flip-flop 96 is not set, that is, when the corresponding header has not arrived on the first data transmission path 28, the AND gate 104 outputs the stop signal 5TOP. Therefore, data transmission on the second data transmission path 34 is stopped.

In this way, the stop circuit 80 synchronizes the packets to be paired.

Next, when the two D flip-flops 96 and 98 are both set, that is, when the corresponding headers have arrived at both parallel data buffers B3 and B13,
One input of both AND gates 102 and 104 becomes low level, and stop signal 5TOP becomes low level. Then, both of the two inputs of the AND gate 100 become high level, and a high level merging control signal is output to the merging circuit 82. Therefore, the merging circuit 8
One input of an AND gate 114 included in the second circuit becomes a high level, and conversely, one input of an AND gate 116 becomes a low level. Therefore, the data from the OR gate 118 is not transmitted from the C element of the second data transmission path 34, but from the first
The signal AKO from the C element included in the data transmission line 28 of
is output, and this signal is given as the signal AKI of the C element CI2 of the second data transmission line 34. At the same time, one input of the AND gate 108 becomes low level, and the signal TRO is transmitted from the C element C12 to the C element in the previous stage.
becomes low level. Furthermore, since the merging control signal is at a high level, the output of the AND gate 110 is enabled as an input to the OR gate 112. Therefore, the first
When both the signals TRO of the C element C2 of the data transmission path 28 and the C element CI2 of the second data transmission path 34 are at high level, the C element of the first data transmission path 28 from the OR gate 112 high level signal T
PO is given. Therefore, from then on, the data packets on the data transmission path 34 of box 2 are transferred to the first data transmission path 2.
The signal is applied to the packet recombination circuit 84 provided at 8, and disappears from the second data transmission path 34.

In the data packet recombination circuit 84, the packets are recombined and a new data packet is output as the first data packet.
on the data transmission line 28, the stop circuit 80
A high level halt release signal is applied to reset both D flip-flops 96 and 98, thus disabling new data packet generation circuit 50.

In this way, a match between data packets to be paired is detected, and one new data packet is generated.

FIG. 15 is a block diagram showing another embodiment of the invention. The embodiment shown in FIG. 15 is effective in preventing so-called "deadlock" in which a data packet to be paired is forever not found.

To explain in detail, in both the embodiments shown in FIG. 6 and FIG. 9, as shown in FIG. If only one data packet pair detection section and 34a are defined, and each loop data transmission path 2 and 34 has only one data packet pair detection section, as shown in FIG. When data packets are circulated on the two looped data transmission paths 28 and 34 at the same transfer rate and in the order shown, the same identification data, e.g. It is impossible for "AI" to be detected, so a 'deadlock' occurs in such a case.

On the other hand, as shown in FIG. 17, at least one loop-shaped data transmission path 28 (or 34) has a plurality of data packet pair detection sections 28a+, 28az+.
By specifying ..., "deadlock" can be effectively avoided. This is because even if data is transferred in opposite directions at the same transfer rate and in the order shown in both loop-shaped data transmission paths 28 and 34, the data packet pair detection section 34a of the loop-shaped data transmission path 34 When identification data such as "A2" exists, the data packet pair detection section 28a and 2 of the other loop-shaped transmission line 28
This is because there is always a chance that the same identification data "A2" exists in any one of 8a2. Therefore, "deadlock" can be avoided by defining a plurality of data packet pair detection sections on one of the loop-shaped data transmission paths.

In FIG. 15, the first loop-shaped data transmission path 2
8 includes a plurality of data packet pair detection sections 28a+, 2
8a2. ...+, 28an, and one data packet pair detection section 34a is defined in the second loop-shaped data transmission path 34. Corresponding to the data packet pair detection sections 28a to 28an of the first data transmission path 28,
A plurality of identification data detection circuits 52. ~52n is provided,
On the other hand, one identification data detection circuit 54 is provided corresponding to the data packet pair detection section 34a of the second data transmission path 34. The identification data from the identification data detection circuits 52+ to 52n associated with the first data transmission path 28 are individually transmitted to corresponding comparison circuits 56. ~56n is given to one input. The identification data from the identification data detection circuit 54 of the second data transmission path 34 is commonly applied to the other inputs of these comparison circuits 56+ to 56n.

And each comparison circuit 56. 56n, when a match of identification data is detected, a control signal is given to the new data packet generation circuit 50 from the corresponding comparison circuit. In response to the match signal, the new data packet generation circuit 50 generates a new data packet from the two matched data packets.
For example, one new data packet is created in the same manner as in the previous embodiment of FIG.

In addition, in FIG. 15, two data transmission paths 28 and 3
4 are shown and described as transmitting data in the same direction, but of course they can be configured as reverse loops as shown in FIG. 17.

FIG. 18 is a block diagram showing the embodiment of FIG. 15, that is, a concrete example of FIG. 17. In the embodiment shown in FIG. 18, one identification data detection circuit 52 is provided in connection with one loop-shaped data transmission path 28, and two identification data detection circuits are provided in connection with the other loop-shaped data transmission path 34. Circuit 54. and 54□ are provided. That is, the identification data detection circuit 52 extracts identification data from the input data to the four parallel data buffers B and -B4 forming the data transmission path 28. Identification data detection circuit 54 and 5
4□ are input data to the parallel data buffer Bl+"'BI4 and 8
2 Extract identification data from the input data to B24. The identification data detected by the identification data detection circuit 52 is sent to two comparison circuits 56. and 56□. The identification data detected by the identification data detection circuits 54+ and 54□ are sent to the corresponding comparison circuits 56. and two comparison circuits 56. and 56□ individually provided. and 56□ compare whether the two applied identification data match, and the matching signals are respectively applied to the stop circuit 80'. The stop circuit 80' is for synchronizing the pair of data packets transmitted on the two data transmission paths 28 and 34, and
It is very similar to the one shown in Figure 2. And the stop circuit 80
A control signal is given to the confluence circuit 82 from ', and the confluence circuit 8
2 cooperates with the packet recombination circuit 84 to send a new data packet onto the data transmission line 28.

The stop circuit 80' receives the header signal from the header signal line H3L between the parallel data buffers B3 and 84 that constitute the first data transmission path 28, and the parallel data buffer B23 that constitutes the second data transmission path 34. and B24
A header signal from the header signal line H3L2 between the two is applied. Further, a signal T from C elements C3 and C23 corresponding to parallel data buffers B3 and B23, respectively.
RO, and TRO□ are given.

From the stop circuit 80', the preceding stage C elements C4 and C24
stop signals S T OP + and S
T OP 2 is applied, and at the same time, a merging control signal is applied to the merging circuit 82 .

The stop circuit 80' includes an OR gate 86', as shown in FIG. 19, and two inputs of the OR gate 86' are connected to respective comparison circuits 56. Coincidence signal 1 and coincidence signal 2 from 56° and 56° are applied, and the output thereof is applied to one input of AND gate 88. The other input of AND gate 88 is given a header signal from header signal line H3L. Two inputs of AND gate 90 are supplied with match signal 1 and a header signal from header signal line H3L2. The outputs of AND gates 88 and 90 are provided through OR gates 92 and 94 as D inputs of D flip-flops 96 and 98, respectively. The clock input of this D flip-flop 96 receives a signal TR from the C element C3 associated with the first data transmission line 28.
O, is given and similarly, D flip-flop 98
A signal TRO2 from the C element C23 of the second data transmission line 34 is applied to the clock input of the . The output Q of each D flip-flop 96 and 98 is provided as its own D input through an OR gate 92 and 94.

The output Q of D flip-flop 96 is applied as is to one input of each of AND gates 100 and 102, and is inverted by an inverter and applied to one input of AND gate 104. In addition, the output Q of the D flip-flop 98 is directly connected to the AND gate 100.
and 104 , and is inverted by an inverter and applied to the other input of AND gate 102 . The output of the AND gate 102 is the stop signal 5
TOP is applied to the C element C4 of the first data transmission path 2nd, and the output of the AND gate 104 is the stop signal 5TO.
The signal P2 is applied to the C element C24 of the second data transmission path 34. Furthermore, the output of the computer game 100 is given to the merging circuit 82 as a merging control signal.

Furthermore, a stop release signal is applied to the reset inputs of D flip-flops 96 and 98.

The merging circuit 82 and data packet recombination circuit 84 are similar to those shown in FIG.

When the data packet header is transferred to the parallel data buffer B3 of the first loop-shaped data transmission path 28, the header signal line H8Li becomes high level, and at this time, the comparison circuit 56 included in the data packet pair detection circuit 48 ．． Alternatively, when a high-level coincidence signal is obtained from 56□, both of the AND gates 88 of the stop circuit 80' become high level, and the D input of the D flip-flop 96 becomes high level. At this time, the signal TRO from the C element C3
, becomes high level, the D flip-flop 96 is set, and its output Q becomes high level. Furthermore, when the header is transferred to the parallel data buffer B23 included in the second loop-shaped data transmission path 34, the header signal line H3
When L2 becomes high level and a match signal is obtained from the comparator circuit 56□, the signal TRO from the C element C23
, the D flip-flop 98 is set.

That is, D flip-flops 96 and 98
Parallel data buffer B of the loop-shaped data transmission line 28
3 and the parallel data buffer B23 of the second loop-shaped data transmission line 34. When the headers of the data packets to be paired arrive, whichever is faster is set. The D flip-flops that have not been sent are always set when the header arrives. That is, D flip-flops 96 and 98 hold the match signals from comparison circuits 561 and 56□ of data packet pair detection circuit 48.

If one D flip-flop 96 is set and the other D flip-flop 98 is not yet set, that is, the corresponding header has not arrived at the parallel data buffer B23 of the second data transmission path 34,
The two inputs of the AND gate 102 of the stop circuit 80' are both at high level, and therefore the terminal T of the C element C4
The stop signal 5TOP to 6 (FIG. 7) becomes high level. Then, this C element C2 will be in a stopped state.

Conversely, when the D flip-flop 98 is set and the D flip-flop 96 is not set, that is, when the corresponding header has not arrived at the first data transmission path 28, the AND gate 104 outputs the stop signal 5TOP2. , Therefore, data transmission on the second data transmission path 34 is stopped.

The state in which the two D flip-flops 96 and 98 are both set, that is, the parallel data buffers B3 and B
23, one of the inputs of AND gates 102 and 104 becomes low level, and both stop signals 5TOP and 5TOP2 become low level. Accordingly, and gate 100
Both inputs become high level, and the confluence circuit 82
A high-level merging control signal is output to. Therefore, the AND gate 114 included in the confluence circuit 82
(Fig. 14), both inputs become high level,
Conversely, one input of AND gate 116 becomes low level. Therefore, from the OR gate 118 (FIG. 14), the data is not transmitted from the C element of the second data transmission path 34, but from the first
The signal AKO from the C element included in the data transmission line 28 of
is output, and this signal is given as the signal AKI of the C element C24 of the second data transmission line 34. At the same time, one input of the AND gate 108 (FIG. 14) both becomes low level, and the signal TRO from cyicz4 to the C element in the previous stage becomes low level. Furthermore, since the merging control signal is at a high level, the merging circuit 82 (first
(Figure 4) As the input to the OR gate 112, the output of the AND gate 11o is enabled. Therefore, the C element C4 of the first data transmission path 28 and the second data transmission path 3
Both signals TPO and TPO□ of C element C24 of 4
When both are at high level, a high level signal TPO is applied from the OR gate 112 to the C element in the previous stage of the first data transmission path 28. Therefore, from then on, the data packets on the second data transmission line 34 are transferred to the packet recombination circuit 84 provided on the first data transmission line 28.
and disappears from the second data transmission path 34.

In the data packet recombination circuit 84, the packets are recombined and a new data packet is output as the first data packet.
on the data transmission path 28, the stop circuit 80
A high level deactivation signal is applied to ', D flip-flops 96 and 98 are both reset, and new data packet generation circuit 50 is therefore disabled. In this way, a match between data packets to be paired is detected, and one new data packet is generated.

FIG. 20 is a modification of the embodiment shown in FIG. 18, and is also a concrete example of the embodiment shown in FIG. 15, that is, FIG. 17.

This embodiment consists of a plurality of basic modules M, , M2 . M3
．． It is constructed by cascading... The basic module M is shown in FIG. Basic module M is the 18th
The circuit shown in the figure is similar to the one shown in FIG. Identification data can be extracted.

Focusing on one basic module M2, the comparison circuit 56□ (FIG. 21) finds a match when two data packets to form a pair are both transferred to that module M2.

On the other hand, the comparison circuit 56+ can find a match because the data packet on the first data transmission path (the upper data transmission path in the figure) of the two data packets to be paired is in the module M2; The data packet on the second data transmission path (the lower data transmission path in the figure) is in the module M1 next to it (on the left side in the figure). In other words, the data packets existing in the four parallel data buffers that make up the upper data transmission path are transferred to the 8-stage parallel data buffer that includes the adjacent module. If the other party's data packet is sent to the module M2, the other party's data packet is waited for until it arrives at the module M2. Conversely, data packets existing on the lower data transmission path are forced to wait until the other party's data packet arrives at module M2 only when the other party's data packet is transferred into the same module M2. In this way, according to the embodiment shown in FIG.
By comparing two data packet pair detection sections and one data packet pair detection section of the upper loop-shaped data transmission path, we can see that "deadlock" due to data miscommunication is completely eliminated, as in Figure 18. It can be resolved by

[Brief explanation of drawings]

FIG. 1 is a conceptual system diagram showing an example of a data processing device in which the present invention can be implemented. FIG. 2 is a schematic block diagram illustrating the principle of this invention. FIG. 3 is a diagram showing an example of a data packet, and FIG. 3(A) and FIG. 3(B) each show a different example. FIG. 4 and FIG. 5 are conceptual diagrams each illustrating the generation of one new data packet from data packets to be paired. FIG. 6 is a block diagram showing one embodiment of the present invention. FIG. 7 is a circuit diagram showing an example of the C element. FIG. 8 is a timing diagram for explaining the circuit of FIG. 7. FIG. 9 is a block diagram showing an embodiment of the pond of the present invention. FIG. 10 is a block diagram showing an example of an identification data detection circuit applicable to the embodiment of FIG. 9. FIG. 11 is a block diagram showing another example of the identification data detection circuit applicable to the embodiment of FIG. 9. FIG. 12 is a block diagram showing still another embodiment of the present invention. FIG. 13 is a circuit diagram showing an example of the stop circuit of the embodiment shown in FIG. 12. FIG. 14 is a circuit diagram showing an example of the merging circuit of the embodiment shown in FIG. 12. FIG. 15 is a block diagram showing another embodiment of the invention. FIGS. 16 and 17 are schematic diagrams showing the flow of data for explaining the concept of the embodiment shown in FIG. FIG. 18 is a block diagram showing an example of the embodiment shown in FIG. 15, that is, an embodiment of FIG. 17. FIG. 19 is a circuit diagram showing the stop circuit of FIG. 18. FIG. 20 is a block diagram showing another embodiment of the embodiment shown in FIG. 15, that is, FIG. 17. FIG. 21 is a block diagram showing one basic module of FIG. 20. In the figure, 27 is a firing section, 28 is a first loop-shaped data transmission path, 34 is a second loop-shaped data transmission path, and 3
6 is an firing detection section, 48 is a data packet pair detection circuit, 5
0 is the new data packet generation circuit, 52.54, 521~
52n is an identification data detection circuit, 56.56+ to 56n are comparison circuits, 80.80' is a stop circuit, 82 is a confluence circuit,
Reference numeral 84 indicates a recombination circuit. Patent applicant Sanyo Electric Co., Ltd. (3 others) Agent Patent attorney Yama 1) Yoshito (1 other person) Figure 1 Figure 2 F8 Figure 3 (B) Figure 5 Figure 8

Claims (1)

[Claims] 1. A first data transmission path configured in a loop using a shift register for sequentially transmitting data packets including identification data in a first direction; a data packet including identification data; a second data transmission line for sequentially transmitting data in a second direction opposite to the first direction and configured in a loop shape using a shift register; identification data detection means connected to a data transmission path and configured to detect the identification data included in each transmitted data packet; pair discrimination means for discriminating data packets to be paired to be transmitted on a loop-shaped data transmission path; and new data for generating one new data packet from the two data packets discriminated by the pair discrimination means. comprising packet generation means;
Data processing equipment. 2. In response to the identification data detecting means detecting specific identification data transmitted through one of the first and second loop-shaped data transmission paths, the loop-shaped data transmission path of the other one of the first and second comprising a means for waiting for the arrival of a data packet to be a pair on the data transmission path of
A data processing device according to claim 1. 3. The data processing apparatus according to claim 2, wherein the waiting means includes stopping means for stopping shifting of the one loop-shaped data transmission path. 4. The identification data detection means includes extraction means for extracting identification data from specific data packet pair detection sections of the first and second loop-shaped data transmission paths, respectively.
A data processing device according to any one of claims 1 to 3. 5. The data processing device according to claim 4, wherein the data packet pair detection section includes one or more register stages. 6. A plurality of data packet pair detection sections are defined for at least one loop-shaped data transmission path,
A data processing device according to claim 4 or 5. 7. The method according to any one of claims 1 to 6, wherein each of the shift registers forming the first and second loop-shaped data transmission paths is configured as a self-propelled shift register. Data processing equipment.