JPS6127784B2 - - Google Patents
Info
- Publication number
- JPS6127784B2 JPS6127784B2 JP14815482A JP14815482A JPS6127784B2 JP S6127784 B2 JPS6127784 B2 JP S6127784B2 JP 14815482 A JP14815482 A JP 14815482A JP 14815482 A JP14815482 A JP 14815482A JP S6127784 B2 JPS6127784 B2 JP S6127784B2
- Authority
- JP
- Japan
- Prior art keywords
- register
- interface
- microinstruction
- address
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 claims description 18
- 230000004044 response Effects 0.000 description 9
- 230000005540 biological transmission Effects 0.000 description 8
- 238000007796 conventional method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000003068 static effect Effects 0.000 description 2
- FFBHFFJDDLITSX-UHFFFAOYSA-N benzyl N-[2-hydroxy-4-(3-oxomorpholin-4-yl)phenyl]carbamate Chemical compound OC1=C(NC(=O)OCC2=CC=CC=C2)C=CC(=C1)N1CCOCC1=O FFBHFFJDDLITSX-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30105—Register structure
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30101—Special purpose registers
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14815482A JPS5936838A (ja) | 1982-08-26 | 1982-08-26 | インタフエ−ス制御方式 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14815482A JPS5936838A (ja) | 1982-08-26 | 1982-08-26 | インタフエ−ス制御方式 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5936838A JPS5936838A (ja) | 1984-02-29 |
JPS6127784B2 true JPS6127784B2 (cs) | 1986-06-27 |
Family
ID=15446463
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14815482A Granted JPS5936838A (ja) | 1982-08-26 | 1982-08-26 | インタフエ−ス制御方式 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5936838A (cs) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62151365U (cs) * | 1986-03-14 | 1987-09-25 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020004866A1 (en) * | 2000-05-08 | 2002-01-10 | Bucht Thomas W. | Hardware method to reduce CPU code latency |
-
1982
- 1982-08-26 JP JP14815482A patent/JPS5936838A/ja active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62151365U (cs) * | 1986-03-14 | 1987-09-25 |
Also Published As
Publication number | Publication date |
---|---|
JPS5936838A (ja) | 1984-02-29 |
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