JPS61276322A - Semiconductor manufacturing equipment - Google Patents
Semiconductor manufacturing equipmentInfo
- Publication number
- JPS61276322A JPS61276322A JP11908185A JP11908185A JPS61276322A JP S61276322 A JPS61276322 A JP S61276322A JP 11908185 A JP11908185 A JP 11908185A JP 11908185 A JP11908185 A JP 11908185A JP S61276322 A JPS61276322 A JP S61276322A
- Authority
- JP
- Japan
- Prior art keywords
- etching
- wafer
- periphery
- substance
- semiconductor manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、プラズマ中の反応を利用してエツチングを
行なう半導体製造装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor manufacturing apparatus that performs etching using reactions in plasma.
従来この種の半導体製造装置を第3図に示す。 A conventional semiconductor manufacturing apparatus of this type is shown in FIG.
第5図は第3図の千面図である。図におりで、(4)は
ウェハ周辺を覆う物質、(2) Viシリコンウェハ、
(3)は電極である。従来装置では、ウェハ周辺を覆う
物質(4)の表面は、なめらかに処理されている。FIG. 5 is a thousand-sided view of FIG. In the figure, (4) is the material covering the wafer periphery, (2) Vi silicon wafer,
(3) is an electrode. In the conventional apparatus, the surface of the material (4) surrounding the wafer is smoothed.
従来の装置でエツチングを行った時のエッチレートのウ
ェハ内分布を第4図に示す。第4図に示した様にエッチ
レートのウェハ内分布は不均一で、ウェハ(2)中央部
では遅く、ウェハ(2)周辺部では早くなっている。FIG. 4 shows the etch rate distribution within a wafer when etching is performed using a conventional apparatus. As shown in FIG. 4, the etch rate distribution within the wafer is non-uniform, being slower at the center of the wafer (2) and faster at the periphery of the wafer (2).
従来の半導体製造装置は以上のようにウェハ周辺を覆う
物質の表面が滑らかに処理されているので、ウェハ中央
部ではエッチレートが遅く、ウニへ周辺邪ではエッチレ
ートが速く、場合によっては周辺部でのみレジスト下部
へのくい込み(サイドエッチ)が発生するという問題点
があった。In conventional semiconductor manufacturing equipment, the surface of the material surrounding the wafer is smoothed as described above, so the etch rate is slow in the center of the wafer, and fast in the periphery, and in some cases, the etch rate is fast in the periphery. However, there was a problem in that digging into the lower part of the resist (side etch) occurred only when the resist was used.
この発明は上記のような問題点を解消するためになされ
たもので、ウニへ周辺邪でのエッチレートを抑え、サイ
ドエッチの発生を防止し、均一性の良いエツチングが可
能な半導体製造装置を提供することを目的とする。This invention was made to solve the above-mentioned problems, and provides a semiconductor manufacturing device that suppresses the etch rate caused by peripheral etching, prevents the occurrence of side etching, and can perform etching with good uniformity. The purpose is to provide.
この発明に係る半導体製造装置は、ウェハの周辺を覆う
物質の表面に凹凸をつけたものである。In the semiconductor manufacturing apparatus according to the present invention, the surface of the material covering the periphery of the wafer is roughened.
この発明においては、ウェハの周辺を覆う物質の表面状
態を凹凸にすることにより、該物質の表面積が増加する
と共に、イオンの入射方向に対して平行な壁面を有する
ようになるため、等方的なエッチャントが効果的に吸収
される。In this invention, by making the surface of the material covering the periphery of the wafer uneven, the surface area of the material increases and the material has a wall surface parallel to the direction of ion incidence. Etchant is effectively absorbed.
以下、この発明の一実施例を図について説明するO
第1図は本発明の一実施例による半導体製造装置を示し
、第2図は本実施例装!Iiによるエッチレートのウェ
ハ内分布を示し、図中、第4図と同一符号は同一部分を
示す。(1)はウエノ・(2)の周辺をおおう物質で、
表面に凹凸をつけである。An embodiment of the present invention will be described below with reference to the drawings. Fig. 1 shows a semiconductor manufacturing apparatus according to an embodiment of the invention, and Fig. 2 shows the equipment of this embodiment. 4 shows the distribution of the etch rate within the wafer according to Ii, and in the figure, the same reference numerals as in FIG. 4 indicate the same parts. (1) is a substance that covers the area around Ueno (2),
The surface is textured.
次に作用効果について説明する。Next, the effects will be explained.
$1図に示すようにウェハ(2)の周囲を覆う物質(1
)の表面に処理を行い凹凸をつけたことによフ、該物質
(1)の表面積は従来装置のそれよシも大きく、イオン
の入射方向に対して平行な壁面を有することとなる。そ
の結果、上記物質(1)はその表面に等方的なエッチャ
ントを効果的に吸収し、ウェハ(2)の周辺部のエッチ
レートを抑え、エツチングレートのウェハ(2)内分布
は第2図に示すようにその均一性が向上する。また、そ
のことによりサイドエッチが発生しなくなシ、均一性の
良いエツチングが可能となる。$1 As shown in the figure, the material (1) surrounding the wafer (2)
), the surface area of the material (1) is larger than that of the conventional device, and has a wall parallel to the direction of ion incidence. As a result, the substance (1) effectively absorbs the isotropic etchant on its surface, suppressing the etching rate at the periphery of the wafer (2), and the distribution of the etching rate within the wafer (2) is shown in Figure 2. The uniformity is improved as shown in . Moreover, this prevents side etching from occurring and enables etching with good uniformity.
なお上記実施例では、ウェハの周辺を覆う物質(1)の
表面を処理して凹凸をつけたものを用いたが、これは多
孔質な素材のものを選択してもよい。In the above embodiment, the material (1) covering the periphery of the wafer was treated to have an uneven surface, but a porous material may also be selected.
以上のように、この発明によればウェハの周辺を覆う物
質の表面状態を凹凸にしたので、ウニ凸面内の形状、エ
ッチレートを均一化することが可能となり、精度の高い
エツチングが達成できる効果がある。As described above, according to the present invention, since the surface condition of the material covering the periphery of the wafer is made uneven, it is possible to make the shape and etch rate within the convex surface of the wafer uniform, thereby achieving the effect of achieving highly accurate etching. There is.
第1図は本発明の一実施例による半導体製造装置のウニ
八周辺の断面図、第2図は木夾施例装置によるエッチレ
ートのウェハ内分布を示す図、第3図は従来の半導体製
造装置のウニへ周辺の断面図、第4図は従来装置による
エッチレートのウェハ内分布を示す図、第5図は従来装
置のウニへ周辺の平面図である。
(1)・・・ウニ八周辺を覆う物質、(2)・・・シリ
コンウェノS 。
なお、図中同一符号は同一部分又は相当8分を示す。FIG. 1 is a cross-sectional view of the area around the wafer of a semiconductor manufacturing apparatus according to an embodiment of the present invention, FIG. 2 is a diagram showing the distribution of etch rate within a wafer using the Kiwami embodiment of the apparatus, and FIG. 3 is a diagram of a conventional semiconductor manufacturing apparatus. FIG. 4 is a cross-sectional view of the periphery of the apparatus, FIG. 4 is a diagram showing the distribution of etch rate within a wafer by the conventional apparatus, and FIG. 5 is a plan view of the periphery of the conventional apparatus. (1)...Substance that covers the area around Sea Urchin Eight, (2)...Silicon Ueno S. Note that the same reference numerals in the figures indicate the same parts or equivalent 8th parts.
Claims (1)
半導体製造装置において、被エッチング物の周辺をおお
う物質の表面状態を凹凸にしたことを特徴とする半導体
製造装置。(1) A semiconductor manufacturing device that performs etching using a reaction in plasma, characterized in that the surface of a material covering the periphery of an object to be etched is made uneven.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11908185A JPS61276322A (en) | 1985-05-31 | 1985-05-31 | Semiconductor manufacturing equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11908185A JPS61276322A (en) | 1985-05-31 | 1985-05-31 | Semiconductor manufacturing equipment |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61276322A true JPS61276322A (en) | 1986-12-06 |
Family
ID=14752406
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11908185A Pending JPS61276322A (en) | 1985-05-31 | 1985-05-31 | Semiconductor manufacturing equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61276322A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1997027622A1 (en) * | 1996-01-26 | 1997-07-31 | Matsushita Electronics Corporation | Semiconductor manufacturing apparatus |
JP2010010304A (en) * | 2008-06-25 | 2010-01-14 | Tokyo Electron Ltd | Processing device |
-
1985
- 1985-05-31 JP JP11908185A patent/JPS61276322A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1997027622A1 (en) * | 1996-01-26 | 1997-07-31 | Matsushita Electronics Corporation | Semiconductor manufacturing apparatus |
US6214740B1 (en) | 1996-01-26 | 2001-04-10 | Matsushita Electronics Corporation | Semiconductor manufacturing apparatus |
KR100309225B1 (en) * | 1996-01-26 | 2002-02-19 | 모리시타 요이찌 | Semiconductor manufacturing apparatus and drying etching method |
JP2010010304A (en) * | 2008-06-25 | 2010-01-14 | Tokyo Electron Ltd | Processing device |
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