JPS61276025A - Computer system with control panel unit - Google Patents

Abstract

PURPOSE:To control plural processors with one control panel unit by connecting the control panel unit to a common bus and providing a panel data register and a panel control register at a processor unit. CONSTITUTION:When a processor unit 2 is stopped, in order to start a unit 2 from a key 11 for the control, a control panel unit 3 reads the contents of a panel control register 7 of the unit 2. At such a time, when the bit of a PRDY flag 24 is 1, the contents of a RUN flag 22 are changed to 1, and written to the register 7 at such a time. When the bit of the flag 24 is 0, the reading of the register 7 is repeated until the bit of the flag 24 comes to be 1. The contents of the register 7 are investigated at the constant time interval by the starting of a timer 10 at the unit 2. At such a time, when the contents are different from a previous contents, the necessary processing is executed. In the present case, since the flag 22 is changed from 0 to 1, a processor 9 starts to execute the sequence from the address of the program counter.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a computer system with a control panel unit.

[Conventional technology]

Conventionally, in this type of computer system with a control panel unit, due to the configuration, it has been common to provide a unique interface between the control panel unit and the processor port, and also to connect the control panel unit on a common bus. Even in this case, a dedicated control line was required between the controlled processor unit and the controlled processor unit.

(Problems to be Solved by the Invention) The above-mentioned conventional computer system with a control panel unit has a one-to-one relationship with a controlled processor unit.
Therefore, in a system that includes multiple processor units, it is necessary to prepare as many control panel units as there are processor units. Even in the case of a panel unit, there is a drawback that the mounting positions of the processor unit and the control panel unit are fixed.

[Means for solving problems]

A computer system with a control panel unit according to the present invention is connected to a common bus that connects the units that make up the system, and controls the panel data register that holds data transferred to and from the control panel unit and its own processor unit. A processor or multiple processor units that have a panel control register that holds control information for the panel control register, check the contents of the panel control register at regular intervals, and execute the operation instructed by the panel control register. It has one or more control panel units that access the panel control register and panel data register of the processor unit via the common bus and at fixed time intervals by address designation.

The control panel unit sets control information in the panel control register of the selected processor unit via the common bus and interface circuit in accordance with instructions input by the operator from the panel. On the other hand, the processor unit implements panel control functions such as setting data sent from the control panel unit in the panel data register and stopping instruction execution by checking the contents of the panel control register at regular time intervals. The contents of this panel data register are transferred to and displayed on the control panel unit through access from the control panel unit at fixed time intervals.

In this way, by connecting the control panel unit to a common bus and providing the processor unit with panel data registers and panel control registers that are accessed by the control panel unit, even in a system including multiple processor units, a single processor unit can be used. It becomes possible to control these plurality of processor units by the control panel unit.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a computer system with a control panel unit according to the present invention. However, although only one processor unit is shown for convenience, it is of course possible to connect a plurality of processor units. Further, units such as memory and Ilo are omitted.

A data transfer path between the processor unit 2 and the control panel unit 3 is secured by this common bus l. The processor unit 2 includes a panel control register 7 that holds control information for controlling the processor unit 2 via the bus interface circuit 6, and a panel data register 8 that holds data transferred to and from the control panel unit 3. and processor 9 are present. The processor unit 2 further includes a timer 10 that generates an interrupt to the processor 9 at regular time intervals.

The processor 9 thereby examines the contents of the panel control register 7 and executes the operation specified by the panel control register 7. The control panel unit 3 includes a data set key 4 for setting data in the panel data register 8, a control key 11 for setting control information in the panel control register 7. A data display 5 on which data read and transferred from the panel data register 8 is displayed is connected, and these are used as an operator interface. The control panel unit 3 accesses the panel control register and panel data register of the designated processor unit 2 via the common bus 1 by addressing at regular time intervals to learn the state of the processor unit.

FIG. 2 is a diagram showing the configuration of the panel control register 7. As shown in FIG.

The HEX data 21 reflects the contents of the data bits input using the data set key 4. The RUN flag 22 is a bit that controls the operating state of the processor unit 2, and is used to start and stop the processor unit 2 ("l" means operation, "O" means stop).
. The CHG flag 23 is set to l'' when changing the contents of the register inside the processor unit 2. At this time, the HEX data 21 is shifted into the lower 4 bits of the register number 2 of the register group 27.PR
The DY flag 24 indicates whether or not the processor unit 2 can accept control commands from the control panel unit 3 ("1" means that the control command can be accepted; "0" that means that the command cannot be accepted).

DRDY25 indicates whether or not the register contents of the processor unit 2 are set in the panel data register 8 when the register contents are read.

The 5TEP flag 26 is a flag indicating a request for single step operation. Register group 27 and register number 28 are used to specify registers within processor unit z.

Next, the operation of this embodiment will be explained.

Assume that processor unit 2 is now in a stopped state. At this time, from the control key 11 to the processor unit 71/2
In order to start up the control panel unit 3,
reads the contents of the panel control register 7 of the processor unit 2. At this time, if the bit of the PRDY flag is "l", the contents of the RUN flag 22 are changed to "l" and this time it is written to the panel control register 7. , If the PRDY flag bit is "O", the panel control register 7 is read repeatedly until the PRDY bit becomes "1'. In the processor unit 2, the panel control is performed at fixed time intervals by starting the timer IO. Examining the contents of register 7. At this time, if the content differs from the previous content, necessary processing is performed.

In this case, the RUN flag 22 has changed from 0'' to 1'', so the processor 9 starts executing instructions from the address of the program counter.

〔Effect of the invention〕

As explained above, the present invention connects a control panel unit to a common bus, and provides a preset unit with a panel data register and a panel control register that can be accessed by the control panel unit.
Even in a system that includes multiple processor units, there is an advantage that these multiple processor units can be controlled by one control panel unit.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of a computer system with a control panel unit according to the present invention, and FIG. 2 is a diagram showing the configuration of the panel control register 7 of FIG. 1. 1...Common bus, 2...Processor unit, 3...Control panel unit, 4...Data set key. 5... Data display, 6... Bus interface circuit, 7... Panel control register, 8... Panel data register, 9... Processor, 10... Timer 11...
・Control key. District 1, Figure 2

Claims (1)

[Claims] A panel data register that is connected to a common bus that connects the units that make up the system and holds data transferred to and from the control panel unit, and a panel control register that holds control information for controlling its own processor unit. and one or more processor units that check the contents of the panel control register at regular time intervals and execute operations instructed by the panel control register, and the panel control register and panel data register of the designated processor unit. A computer system with a control panel unit, characterized by comprising one or more control panel units that are accessed at fixed time intervals via a common bus and by specifying addresses.