JPS6127531A - Continuous light emission type stroboscopic device - Google Patents

Abstract

PURPOSE:To execute exactly turn-on and off by following a continuous gate signal of a minute interval, by reverse-biasing a conducting semiconductor switching element, cutting it off, and eliminating immediately the potential between the gate and the cathode. CONSTITUTION:A changeover switch SW is connected to a contact 95a, a continuous light emitting signal x1 is inputted, a signal multi-pulth is generated 98, H is outputted by setting an FF101, and a light emitting trigger and start signals A1, B are sent out to a light emitting part which is not shown in the figure. When an output L of an invertor 73 is inputted to ORs 71, 72, and an output (H or L) of an FF74 is inputted to the OR71, and inverted 75 and inputted to the OR72, transistors 52, 54 and 62, 64 repeat turn-on and off alternately, capacitors 55, 65 repeat charge and discharge, and the FF74 outputs alternately H and L. H of the FF74 and the FF101 drives a total light emission time setting circuit 200B and a logical circuit part 200E, and outputs a light emitting trigger signal A2, a light emission restart signal D, a light emission stop signal C and a light emission end signal E2 to the light emitting part. In such a way, a light emission which follows a continuous minute interval signal is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a continuous flash device, more specifically, to a continuous light emitting strobe device, and more specifically, to a continuous light emitting flash device, by rapidly controlling on/off of a semiconductor switching element connected in series with a flash discharge tube. The present invention relates to a continuous emission type strobe device which is capable of emitting light, and which is capable of accurately performing the above-mentioned continuous emission.

(Prior art) Generally, the luminous intensity of a flash discharge tube in a strobe device is 1
As is well known, it has a peak shape and increases rapidly from the time the light emission starts, and the light emission ends in an extremely short period of several seconds.

Therefore, in a camera that employs a focal plane shutter, there is a problem in that the strobe may emit synchronized light at a shutter speed faster than the strobe synchronization time, and normal strobe photography cannot be performed. In other words, the focal plane shutter does not fully open at a high shutter speed that is higher than the strobe synchronization time.

In such a case, the slit formed by the leading and trailing curtains runs in front of the film surface.

No matter at what point the strobe device was used to emit flash light, only a portion of the film surface was exposed to the strobe light, making it impossible to take photographs with uniform exposure.

Therefore, as a means to solve the above-mentioned problems, the applicant first developed a method to control the flash discharge tube K so that it repeatedly emits pulsed light, thereby improving the conventional static flat light emitting strobe. We have proposed a flat light-emitting strobe device that can obtain light-emitting characteristics that are substantially equivalent to those of the 91 flash discharge tube, or alternatively, we have proposed a flat light-emitting strobe device that can obtain light-emitting characteristics that are substantially equivalent to the light-emitting characteristics of the device. We have proposed a continuous flash flash device that can emit light with a constant intensity.

However, in order to cause the flash discharge tube to emit light in a pulsed manner as described above, K sends a control signal to the gate of a semiconductor switching control element (for example, a thyristor) connected in series to the flash discharge tube for the duration of the pulse. It must be applied at minute intervals that match the interval. However, when a portion of the thyristor is turned off, the potential between the gate and cathode of the thyristor is greatly biased in the negative direction, and it takes a long time for the potential biased to the negative side to return to zero. Therefore, even if a positive control signal is applied to the gate in an attempt to turn on the thyristor again, it will be absorbed by the potential biased to the negative side, and the thyristor will not turn on as intended. There was a risk that it would not turn on.

Here, the above-mentioned phenomenon is shown in Fig. 13, using two flash discharge tubes.
This will be explained in detail using the continuous light emitting strobe device of this invention. The main circuit section 100 of this continuous flash flash device is constructed as follows. A power supply circuit 1 consisting of a well-known DC-DC converter is installed in the power supply of this strobe device, and a rectifier diode 2 is connected from its positive output terminal.
A positive operating voltage supply line fix (hereinafter abbreviated as line 11) is derived from the negative output terminal, and a negative operating voltage supply line Jlo (hereinafter abbreviated as line N) is derived from the negative output terminal. At the same time, the line is grounded.

A main capacitor 3 which serves as a main power source for light emission is connected between the two housings No. 11, and a charging completion detection circuit consisting of a series circuit of a resistor 4 and a neon lamp 5 is connected. . Further, a series circuit of the resistor 6, the first trigger capacitor 7, and the primary coil of the first trigger transformer 80 is connected between both inputs flI11o, and the connection point between the first trigger capacitor 7 and the resistor 6 is connected to the first flash discharge. The tube X1 is connected to the anode of the first trigger thyristor 9, whose cathode is connected to the line 10, and whose gate is connected to the resistor l.
It is connected to line io via O. The gate of the first trigger thyristor 9 is supplied with a light emission trigger (tj number A1) of the first flash discharge tube XS via a resistor 11 and a capacitor 12.

One end of the secondary coil of the first trigger transformer 8 is.

It is connected to the line Do, and the other end is a ## of a xenon discharge tube, etc.
J! It is connected to the trigger electrode of the flash discharge tube X1. One electrode of the flash discharge tube The main thyristor 26 has a cathode connected to the line fiO. In addition, the gate of the main thyristor 26 is connected to the resistor 2.
7 through the line ρOK, and a resistor 28.
It is connected to the output terminal of an OR gate 30 via a capacitor 29 in order, and the input terminal of this OR gate 30 is supplied with a light emission start signal B and a light emission restart signal R. In addition, a resistor 1 is connected between both lines fto -11.
3, the second trigger capacitor 14, and the second trigger transformer 1
A series circuit with a 50 primary coil is connected. The connection point between the resistor 13 and the second trigger capacitor 14 is
It is connected to the anode of a second trigger thyristor 16 for triggering the second flash discharge tube XS, the cathode of the thyristor 16 is connected to the line A0, and the gate is connected via a resistor 17 to the line 1o. A resistor 18 and a capacitor 1 are connected to the gate of the second trigger thyristor 16.
9, a light emission trigger signal A8 for the second flash discharge tube is supplied.

One end of the secondary coil of the second trigger transformer 15 is connected to the line, and the other end is connected to a trigger electrode of a second flash discharge tube X such as a xenon discharge tube. One electrode of the flash discharge tube X2 is connected to the line 11, and the other electrode is connected to the anode of a commutating thyristor 31, which is a second switching element, and also connects the current capacitor 24 and diode 23. The cathode of the rotating flow thyristor 31 is connected to the line fioK. Also, the gate of the same thyristor 31 is connected to the resistor 3.
2 to line fiO and resistor 33
A light emission stop signal C is supplied through the capacitor 34. Further, the diode 23 supplies a charging current to the commutating capacitor 24,
Its anode is connected to the line fhK through the resistor 22, and its cathode is connected to the commutation capacitor 241c.

Further, one end of a capacitor 36 is connected to the connection point between the commutating capacitor 24 and the anode of the main thyristor 26, and the other end of the capacitor 36 is connected to the gate of the commutating thyristor 31 via a resistor 36a. It is connected.

Further, one end of a capacitor 37 is connected to the connection point between the commutating capacitor 24 and the anode of the commutating thyristor 31.

The other end of the capacitor 37 is connected to the gate of the main thyristor 26 via a resistor 37a.

Further, the light emission trigger signal A1. As, the light emission start signal B, etc. are sent from a separately provided control circuit (not shown), but a detailed explanation of this control circuit will be omitted.

In the main circuit section 100 configured in this way, when the user of the camera presses the release button (not shown), a light emission trigger signal A1 is sent from the control circuit (not shown) to the first Applied to the gate of the trigger thyristor 9, the first trigger thyristor 9
is conductive. Then, both ends of the first trigger capacitor 7 are short-circuited via the primary coil of the first trigger transformer 8 , and the discharge current of the charge accumulated in the first trigger capacitor 7 flows through the primary coil of the first trigger transformer 8 . Flows to 2
A high voltage is generated in the next coil, and this high voltage is applied to the trigger electrode of the first flash discharge tube X1, so that the first flash discharge tube X1 is brought into an excited state. At the same time, the light emission start signal B generated by the control circuit is transmitted to the OR gate 30. Capacitor 29. The main thyristor 26 is made conductive via the resistor 28. When the main thyristor 26 is conductive, the main capacitor 3
The electric charges that have been stored in the flash discharge tube X1 are discharged through the first flash discharge tube X1 in the excited state and the anode/cathode of the main thyristor 26, and the first flash discharge tube X1 starts emitting light. On the other hand, according to set values corresponding to film sensitivity and aperture value information provided in the control circuit, a one-shot pulse is outputted as a light emission stop signal C from the control circuit after a certain period of time has elapsed.

This signal C#'i, the capacitor 34. The commutating thyristor 31 is made conductive via the resistor 33. Then.

In the commutating capacitor 24, the P side is initially (+), and the Q
Since the side is charged to (-), this charge flows through the commutating thyristor 31 as a discharge current.

A reverse voltage is applied between the anode and cathode of the main thyristor 26 to turn off the main thyristor 26. Also,
At this time, the P side of the capacitor 37 is also initially charged with (+)K, so this charging current is as follows.

Capacitor a 7 ('+-) → Commutation thyristor 31 →
It is discharged along the path of resistor 27 → resistor 37a → capacitor 37 (-). This discharge path applies a reverse bias to the gate of the main thyristor 26, so in combination with applying a reverse bias between the anode and cathode of the main thyristor 26, it is possible to ensure that the same main Thyristor 2
6 will be turned off. Therefore, due to this off operation, the light emission of the first flash discharge tube XI becomes attenuated light emission. As a result, the luminance of the light emitted decreases.

The control circuit detects this and sends out a light emission trigger signal A3 for the second flash discharge tube X2.

This light emission trigger signal "A" is a capacitor 19 and a resistor 1.
8 to the second trigger thyristor 16 of the second flash discharge tube X. Then, the electric charge accumulated in the second trigger capacitor 14 is discharged through the primary coil of the second trigger transformer 150, and a high voltage is generated in the secondary coil of the second trigger transformer 15, causing the discharge of the second flash discharge tube X2. Apply to the trigger electrode. At this time, since the commutation thyristor 31 is already conductive, the second flash discharge tube Xs starts emitting light. Then, the one-emission brightness rises again, which is detected by the control circuit, appropriate processing is performed, and a one-shot pulse is sent out as a light emission restart signal.

This signal is ORGATE 30. The main thyristor 26 is made conductive again via the capacitor 29° resistor 28.

Also, before this, the potential of the commutating capacitor 24 is at the first level.
When the flash discharge tube is in operation, the reverse KQ side is the RP side force (
-) Since it is charged with K, the charged charge is discharged through the main thyristor 26, and a reverse bias is applied between the anode and cathode of the commutating thyristor 31 to shift the second flash discharge tube X3 to attenuated light emission, and the above-mentioned The first flash discharge tube
Similarly to applying a reverse bias to the gate of the commutating thyristor 31 when the capacitor 36 (+
)→main thyristor 26→resistance 32→resistance 36a→capacitor 36 (→) and at the same time, a reverse bias is applied to the gate of the commutating thyristor 31 so that the attenuated light emission is more completely carried out. ing.

Since the main thyristor 26 becomes conductive again within the deionization time of the first flash discharge tube X1, the first flash discharge tube X1 resumes upward light emission. That is, 1st. The second flash discharge tube X1 #Xs is
- The trigger voltage from the trigger transformer 8.15 is applied only at the start of the second light emission, and the light is emitted, but from the second time onwards, the main thyristor 26 and the commutating thyristor 31 are only fired within the deionization time, and the rising light emission is started. It will start again.

After that, if one or more operations are repeated and the light is emitted alternately, the light emission waveform in this state becomes continuous light emission (flat light emission) like a continuous triangular wave.

By the way, the first flash discharge tube X emitting light as described above
When the one-light emission stop signal C is applied to shift I to attenuated light emission, the main thyristor 26 is reverse biased. When observing the potential between the gate and cathode of the same thyristor 26 at this time with a voltage waveform observation device, as shown by the solid line in FIG. increases and eventually becomes equal to zero.On the other hand,
As shown in FIG. 14(B), the light emission restart signal applied to cause pulsed light emission at minute intervals is applied to the thyristor 26 while the above potential is still slightly on the (-) side. Applied to the gate. Then, this light emission restart signal is added to the potential remaining on the (-) side, as shown by the dotted line in FIG. 14(A). That is, even if a positive (+) light emission restart signal is applied to the gate, the result will be the same as if no positive (+) signal was applied to the gate.

Such a phenomenon occurs not only in the main thyristor 26, but also in the commutation thyristor 31. However, depending on the time width of the minute intervals mentioned above, there is a possibility that continuous pulsed light emission may not be possible.

Furthermore, the above-mentioned situation is not limited to the case where two flash discharge tubes are used, but also applies to the case where one flash discharge tube is used to emit light continuously in a pulsed manner at minute time intervals. be able to.

(Objective) The object of the present invention is to turn on and off a semiconductor switching element connected in series to a flash discharge tube at minute time intervals in response to a control signal supplied.

The present invention provides a continuous light emitting type strobe device in which the semiconductor switching element is configured to perform an ON-OR operation accurately.

(Summary) In order to achieve the above object, the present invention provides for immediately returning the gate-cathode of the switching element to its initial state when a pulse that cuts off the semiconductor switching element is applied for the minimum necessary time. Particularly, it is characterized in that even if the pulses are applied to the gate of the semiconductor switching element at minute intervals, it can be turned on and off accurately.

(Example) The present invention will be explained below with reference to the illustrated embodiments.

The electric circuit of a continuous light emitting type metrobo device showing the first embodiment of the present invention is constructed as shown in FIG. 1.2. The above-mentioned FIG. 1 shows the configuration of the main circuit section 100A, and is based on the conventional example (No. 131!!!) described above.
The same reference numerals will be given to the members having the same configuration as those in (see I), and only the different constituent parts will be explained to avoid repeating the explanation.

2 between the positive electrode side of the main capacitor 3 and the line JIE
)O resistance49. so is connected in series, 1 resistor 4
The connection point VC at 9.50 is connected to the control circuit section 200, which will be described later.
The control circuit 200 is connected to supply a voltage proportional to the charging voltage of the main capacitor 30 to the control circuit 200. Also, a resistor 3 whose one end is connected to the line l□
The other end of the commutating capacitor 38 is connected to the anode of the commutating thyristor 39 and one end of the commutating capacitor 38, and the other end of the capacitor 38 is connected to the anode of the main thyristor 26. The cathode of the thyristor 39 is connected to the line 1G, and the gate of the thyristor 39 is connected to the line io via a resistor 40. The gate is connected to the output terminal of the OR gate 20 via a series circuit including a resistor 20b and a capacitor 20a. One input terminal of the OR gate 20 is connected to a light emission end signal E generated by the control circuit section 200 to notify that the total light time has ended.
When the spirit is supplied, the other input end is
A light emission end signal E to notify that the flash light emission has ended is supplied. Further, one end of a resistor 42 is connected to the gate of the main thyristor 26,
The other end of the resistor 42 is connected to the anode of a diode 43, and the cathode of the diode is connected to the backflow blocking diode 4.
4 and one end of the capacitor 41. Then, the diode 44. The cathode of is line 1
The other end of the capacitor 41 is connected to the connection point between the commutating capacitor 24 and the anode of the thyristor 26. Let this connected position be Ql.

Further, one end of a resistor 46 is connected to the gate of the commutating thyristor 31, and the other end of the resistor 46 is connected to a diode 47.
The cathode of the diode 47 is connected to the anode of the reverse current blocking diode 48 and one end of the capacitor 45. And, the cathode of the diode 48 mentioned above is the Rhine Emperor. The other end of the capacitor 45 is connected to the connection point between the commutating capacitor 24 and commutating thyristor 31. Let this connected position be P-o.

Next, as shown in FIG. 2, the control circuit section slope is V-
F' converter section 200A, total viewing time setting circuit section 2
00B, a photometric circuit section 200C, a light emission start signal input section 200D, and the like.

Note that the strobe device of this embodiment is designed to allow you to select between a normal "flash emission mode" and a "continuous emission mode." When in the "flash emission mode," it functions as a normal auto strobe; In "light emission mode", the flat light emission continues until the shutter closes.

First, the configuration of the light emission start signal input section 200D will be explained. One input terminal of the AND gate 94 is supplied with a continuous light emission start signal Jc1 from the camera body (not shown), and the output terminal of the AND gate 94 is connected to a low level input signal (hereinafter referred to as L level). ) to high level (below).

It's called H level. )K--Outputs an H level pulse of a predetermined width when rising. It is connected to the input end of a pulse generation circuit 98 consisting of a one-seat multivibrator. The other input terminal of the AND gate 94 is connected to an input terminal of an inverter 96 and a movable contact terminal of a mode changeover switch 95. A first fixed contact terminal 95a of the mode changeover switch 95 is connected to a terminal to which an operating voltage of 10 B is applied, and a second fixed contact terminal 95b is grounded.

One input terminal of the AND gate 97 is supplied with a flash light emission start signal x from a camera body (not shown), and the other input terminal is connected to the output terminal of the inverter 96. . The output terminal of the AND gate 96 is connected to the input terminal of a pulse generation circuit 99 similar to the pulse generation circuit 98 described above. The light emission start signal input section 200D is configured in this manner.

Further, the output terminal of the pulse generating circuit 98 is connected to the OR gate 1.
02, and is connected to one input terminal of the pulse generating circuit 9.
The output terminal of 9 is connected to the other input terminal of the OR gate 102, and the output terminal of the flip-flop circuit C and below is connected to the other input terminal of the OR gate 102.
It is abbreviated as F circuit. ) 103 is connected to the set input terminal. The output terminal of the FF circuit 103 is an inverter 104
and the photometry circuit section 200C, which will be described in the first place, via the resistor 105.
The NPN type switching transistor 1110 is connected to the base.

The light emission trigger signal AI and light emission start signal B are sent out from the output end of the OR gate 102.

Next, the configuration of the photometry circuit section 200C includes a resistor 107 and a variable resistor whose resistance value is set in accordance with information such as film sensitivity and aperture. 106 is connected to a series circuit, and a series circuit in which the collector emitter of an NPN phototransistor 10g, a resistor 109, and an integrating capacitor 112 are connected in sequence is also connected. The connection point between the resistor 107 and the variable resistor 106 is connected to the non-inverting input terminal of an operational amplifier 113 forming a voltage comparison circuit, and the inverting input terminal of the operational amplifier 1130 is connected to the connection point between the resistor 109 and the capacitor 112. is connected.

The output terminal of the operational amplifier 113 is connected to a pulse generating circuit 1 similar to the pulse generating circuit 98 through an inverter 114.
The output terminal of the circuit 115 is connected to the reset input terminal Ra of the FF circuit 103. The output terminal of this pulse generating circuit 115 is designed so that the light emission end signal E1 is sent out. Note that a cathode of a protection diode 113a is connected between the output end of the operational amplifier 113 and the input end of the inverter 114, and its anode is grounded.

Further, the output terminal of the pulse generating circuit 98 is connected to the FF circuit 1.
The output terminal of the FF circuit 101 is connected to the input terminal of the inverter 73, which is a part of the V-F converter section 200A, which will be described next, and the part of the total light time setting circuit section 200B. It is connected to one input terminal of an AND gate 87 which is a section.

In the V-F converter section 200A, the output end of the inverter 73 is connected to one input end of each of the two OR gates 71 and 72, and the OR gate 72
The output terminal of is connected to an NPN transistor 62 via a resistor 61.
connected to the base of.

The emitter of the transistor 62 is grounded, and the collector of the transistor 62 is connected to the base of a PNP transistor 64 via a resistor 63. The emitter of the transistor 64 is connected to a terminal to which an operating voltage of 10 B is applied and one end of a capacitor 65, and the other end of the capacitor 65 is connected to the collector of the transistor 64, the inverting input terminal of an operational amplifier 68, and a constant current. The identification current source 66 is connected to one end of the identification current source 66, and the other end of the identification current source 66 is grounded. The non-inverting input terminal of the operational amplifier 68 is connected to the non-inverting input terminal of the operational amplifier 58 via a series circuit of two resistors 67. It is connected to the 100 A connection point Vc.

Further, the output terminal of the operational amplifier 68 is connected to one input terminal of an OR gate 59, and the other input terminal of the gate 59 is connected to the output terminal of the operational amplifier 58. Further, the output terminal of the OR gate 71 is connected to the NP via the resistor 51.
It is connected to the base of an N-type transistor 520, and the emitters of the transistors 5 and 2 are grounded. The collector of the transistor 52 is connected to pNpr d' through a resistor 53.
) is connected to the base of the run raster 540, and the terminal of the transistor 54 is connected to a terminal to which an operating voltage of 10B is applied and one end of a capacitor 55. The other end of the capacitor 55 is connected to the collector of the transistor 54, the inverting input end of the operational amplifier 58, and one end of the constant current source 56, and the other end of the identification current source 56- is grounded. The output terminal of the OR gate 59 is connected to the FF circuit 74.
The output terminal of the FF circuit 74 is connected to the other input terminal of the OR game 71 and the input terminal of the inverter 75. And this inverter 75
The output terminal of is connected to the other input terminal of the OR gate 72. In this way, the V-F converter section 2 (jO
A is configured such that the output end of the inverter 75 is
Further, it is connected to the input end of the pulse generation circuit 83, and the light emission restart signal is sent from the output end of the pulse generation circuit 83, and is applied to one input end of the OR gate 30 of the main circuit section 100A. It has become. Furthermore, the FF
The output terminal of the circuit 74 is connected to one input terminal of the AND gate 7G, and the output terminal of the AND gate 76 is connected to the input terminal of the pulse generating circuit 77 and one input terminal of the AND gate 81. The light emission stop signal C is outputted from the output end of the pulse generating circuit 77, and the main circuit section 1
It is designed to be input to one end of a 00A capacitor 34. Further, the output terminal of the above-mentioned ANDGOO) 81 is connected to the input terminal of a pulse generation circuit 820, and the light emission trigger signal A3 is outputted from the output terminal of the same circuit 82.
It is input to a capacitor 19 of 00A. Further, the output terminal of the circuit 82 is connected to the input terminal of the FF circuit 78 in order to apply feedback. The output terminal of this FF circuit 78 is connected to the input terminal of an inverter 790, and the output terminal of the inverter 79 is connected to the other input terminal of the AND gate 81.

Next, the configuration of the total light time setting circuit section 200B will be described. A resistor 86 and a capacitor 85 for determining the oscillation frequency are connected between the input terminal of the oscillation circuit 840 and the terminal to which the operating voltage element B is applied. The output terminal of the oscillation circuit 84 is connected to the other input terminal of the AND gate 87.

The output terminal of the AND gate 87 is connected to one input terminal of the counter 8B, and the continuous light emission time setting signal x3 is input to the other input terminal of the counter 88.

Further, the output terminal of the counter 88 is connected to the input terminal of the FF circuit 89, and the output terminal of the FF circuit 89 is connected to the input terminal of the FF circuit 89.
It is connected to one input end of 91. The output terminal of this AND GO) 91 is connected to the input terminal of a pulse generating circuit 930.

The light emission end signal ha is outputted from the output terminal of the generation circuit 93, and this output terminal is connected to the main circuit section 1.
It is connected to one input terminal of the OR gate 20 of 00A. Further, the output terminal of the noise generating circuit 93 is connected to the reset terminal R of each of the FF circuits 74, 78, 89, 101 and the counter 88, so that they can be reset at the same time. Also, the above F
The output end of F circuit 89 is also connected to the input end of inverter 92.

The output terminal of this inverter 92 is connected to the other input terminal of the AND gate 76. In this way, the total luminescence time crotch disease circuit section 200B is configured.

The first embodiment of the present invention is configured as described above.

Before going into the explanation of the operation of this embodiment.

In order to make the present invention easier to understand, first, a flash discharge tube control section 100AI (see FIG. 1), which is a main part of this embodiment, will be taken out and the operation of this control section 100As will be explained with reference to one drawing.

FIGS. 3A, 3B, and 3C show only the flash discharge tube control section 100Aa.

Now assume that a power switch (not shown) is turned on and a predetermined voltage is applied to the two lines.

Then, as shown in Figure 3(A), line h→resistance 2
2 → Diode 23 → Commutation capacitor 24 → Resistor 25 →
A charging current flows through the path L1 of the line h, and the commutating capacitor 24 is charged with the Pi side becoming (+). Also,
Similarly, the path L of line h→resistance 22→diode 23→capacitor 45→diode 48→line fiO! A charging current flows, and the PK side of the capacitor 45 also becomes (+).
is charged to. Note that both poles of the tip 9410 are close to ground potential, so they will not be charged. In this state, the light emission trigger signal A1 is applied, a predetermined voltage is applied to the trigger electrode of the flash discharge tube
It is applied in the path of the gate of thyristor 26, turning on said thyristor 26. Then, a relatively large discharge current flows through the path of line h→flash discharge tube X1→thyristor 26→line no, and the flash discharge tube X1 emits light.

Then, when a predetermined minute time has elapsed, the light emission is stopped and the signal C is turned on.
is applied to capacitor 34. This signal C causes a current to flow through the path from capacitor 34 to resistor 33 to the gate of thyristor 31, so that thyristor 31 is turned on. Then, as described above, the charge of the capacitor 24 whose KPI side is charged to (+) becomes the :I capacitor 24.
(+) → Thyristor 31 (anode-cathode) → Thyristor 26 (cathode-anode) → Capacitor 24 (
-) The iris 26 flowing along the path Lm (indicated by the dotted line) is turned off, so the light emission stops. Also, at the same time,
As mentioned above, it passes through the uncharged capacitor 41, and then the capacitor 24 (+) → thyristor 31 → resistor 27 →
A current flows through a path La (indicated by a dotted line) of resistor 42 → diode 43 → capacitor 41 → capacitor 24 (-). The current of this path L4 is also applied to the gate of the thyristor 26, and together with the fact that the anode and cathode of the iris 26 are reverse biased, the thyristor 26 is completely turned off and the flash discharge tube is turned off. Stop the light emission of X1. In addition, if the capacitor 24 is discharged as described above, the line L6 (refer to No. 31g (B)) of Linem → Flash discharge tube X1 → Capacitor 24 → Thyristor 31 → Line 111 → Flash discharge tube X1 → Capacitor 41
→ Diode 44 → Line No route, the two capacitors 24.41 are rapidly charged, so the Qs side of both of these capacitors 24.41 is (E)K.
It will be charged. Note that, at this time, the capacitor 45 is hardly charged as described above.

In the path L6, a forward current also flows through the diode 44, so this diode 44 is also forward biased, and therefore the gate-cathode of the thyristor 26 is also forward biased. but.

Since both ends of the diode 440 are maintained at a diode potential of around 0.5V, it can be considered that the potential between the gooto cathode of the thyristor 26 is almost zero.

Moreover, the current that charges the capacitor 41 through the path L6 is passed through the thyristor 2 by the diode 43.
Since the current is prevented from being applied to the gate of L6, the thyristor 26, once cut off, will not be turned on again by the current of the path L6. That is, this situation will be explained with a diagram.

As shown in FIGS. 14(C) and 14(D)c, the potential between the gate and cathode of the thyristor 26 is
At the moment when 6 is cut off, it is greatly biased toward the negative side, as shown by arrow R8. However, by applying a reverse bias between the gate and cathode of the thyristor 26 for the minimum necessary time 1o to cut off the thyristor 26, as soon as the thyristor 26 becomes cut off,
By releasing the reverse bias between the cathode of this thyristor 26 and setting the current between the gate and the cathode to zero potential as described above, the next light emission restart signal is generated. When the signal arrives, it will be applied exactly as the gate signal island of the thyristor 26.

When the first light emission is made by the flash discharge tube X1 as described above, the second light emission is made by the flash discharge tube X. i.e. as described above.

Q of commutating capacitor 24 by path LIK! While the side is busy, thyristor 31 is on.

Flash discharge tube X! When a predetermined voltage is applied to the trigger electrode of the discharge tube, the discharge tube emits light immediately. and.

When the light emission restart signal is applied within the deionization time of the discharge tube X1, a current flows to the gate of the thyristor 26 as described above, and the third thyristor 26 is turned on. Then, the capacitor 24) → thyristor 26 (anode -
cathode) → Thyristor 31 (cathode - anode) →
Path L7 of capacitor 24← (see Figure 3 (C))
At the same time that the thyristor 311/c is reverse biased, the capacitor 24) → thyristor 26 (anode-cathode) → resistor 32 → resistor 46 → diode 47
→ Capacitor 45 → Capacitor 24 (-) path LM applies a reverse bias to the gate of the thyristor 31.
This thyristor 31 is completely cut off. When the capacitor 24 becomes almost empty on the above path L8, the line h→
Flash discharge tube X3→=densor 24→thyristor 26→line h route Lo (shown by dotted line), and line I11→flash discharge tube X! → Capacitor 45 → Diode 48 → Line No. path Lso (shown by dotted line) The capacitors 24 and 45 are rapidly charged, so the PI side of both capacitors 24 and 45 is (+).
◎The capacitor 41 is hardly charged at this time. Hereinafter, the gate of the thyristor 31 is kept at substantially zero potential as described above, so that even if the primary light emission stop signal C arrives, the thyristor 31 can be controlled to stay on exactly.

As described above, if the gates of the thyristors 26 and 31 are reverse-biased for the minimum necessary time, and then tl is set to zero potential, the thyristor 26 will die in a very short time. It is possible to continue operating reliably even when 31 and 31 are turned on and off.

The above operation is performed by the flash discharge tube control section 100 of this embodiment.
As is being done.

Next, the operation of this embodiment will be described in the first section along with the operation of the control circuit section 200. This will be explained with reference to FIG.

First, the operation of the "flash light emission mode" will be explained. In this mode, the movable contact piece of the mode changeover switch 95 is switched to the second fixed contact terminal 95b@K.

Then, the other input terminal of the AND gate 94 becomes L level, so the AND gate 94 is closed.

The continuous light emission start signal 21 from the camera body (not shown) is no longer accepted. Therefore, 1. Flash emission start signal X from the camera body (not shown)! When input, the output of the AND gate 97 becomes H level, and an H level hit pulse is generated in the pulse generating circuit 99, and this pulse is output to the OR gate 1.
02 as the light emission trigger signal A, and the first flash discharge tube X1 via the capacitor 12 and resistor 11 in FIG.
The first trigger thyristor 9 is made conductive, and the first trigger transformer 8 applies a high voltage to the trigger electrode of the flash discharge tube X1. Also, as the 1 light emission start signal B, the OR circuit 30
゜Capacitor 29. Main thyristor 26 via resistor 28
conduction. Therefore, the charge accumulated in the main capacitor 3 is discharged through the first flash discharge tube X and the main thyristor 26, and the first flash discharge tube X1 starts emitting flash light. Further, the FF circuit 103 is set by the H level output of the pulse generation circuit 99, the output of the FF circuit 103 is inverted to the H level, and the inverter 104 and the resistor 105 are inverted.
Since the base of the transistor 111 is brought to L level through the input signal, the transistor 111 is turned off. Then, the photometry circuit section 200C enters the operating state, and the capacitor 112 starts integrating the photocurrent generated by the phototransistor 108K upon receiving the reflected light from the object.

The resistance value of the variable resistor 106 is set according to film sensitivity and aperture value information. The above capacitor 112
When the integrated voltage of
14 output is not at H level.

A one-shot pulse is generated from the output end of the pulse generating circuit 115 and outputted as the light emission end signal E1. This signal makes the commutating thyristor 39 conductive via the OR gate 201, capacitor 20a, and resistor 20b shown in FIG. Then, the commutating capacitor 38 initially has (+) on the Q3 side,
Because the Pg side is charged to (-).

This charged charge flows through the commutating thyristor 39 as a discharge current, applying a reverse bias to the main thyristor 26 and turning off the main thyristor 26. Further, the signal E1 is the F
It is also supplied to the reset terminal & of the F circuit 103, and resets the same FF circuit 103. Therefore, the first flash discharge tube Xi, which has been emitting one light, stops emitting light at this point, and proper flash light photography is completed.

Next, the case of "continuous light emission (flat light emission) mode j" will be explained. In this case, the movable contact of the mode changeover switch 95 is switched to the fixed contact terminal 95a side. Since the AND gate 94 is supplied to the input terminal, this AND gate 94 is opened, but since the AND gate 97 is connected via the inverter 96, the L level output is supplied to the input terminal of the AND gate 97. , the AND gate 97 is closed.Therefore, input of the continuous light emission start signal tray from the camera body (not shown) is allowed, but input of the flash light emission start signal is no longer allowed. .and,
When the continuous light emission start signal -TI rises to the H level, the output of the AND gate 94 goes to the H level, and the pulse generating circuit 98 outputs a one-shot pulse at the H level.

This H level pulse is applied as a light emission trigger signal A1 via the OR gate 102 to the gate of the first trigger thyristor 9 via the capacitor 12 and resistor 11 shown in FIG. Ru. Then, both ends of the first trigger capacitor 70 are short-circuited via the primary coil of the first trigger transformer 8 , and the discharge current of the charge accumulated in the first trigger capacitor 7 flows into the primary coil of the first trigger transformer 8 . As a result, a high voltage is generated in the secondary coil, and this high voltage is applied to the trigger electrode of the first flash discharge tube X8, so that the first flash discharge tube X1 becomes excited. At the same time, the light emission start signal B from the OR gate 102 is output (ORG)30. Capacitor 29. resistance 28
The main thyristor 26 is made conductive via the main thyristor 26. When the main thyristor 26 is made conductive, the charges stored in the main capacitor 3 are discharged through the first flash discharge tube X in the excited state and the anode-cathode of the main thyristor 26, and starts emitting light.

Further, the one-shot pulse from the pulse generating circuit 98 is supplied to the FF circuit 101K.
The H level output sent from is supplied to the V-F converter section 200A. This V-F converter section 20
The output frequency of 0A changes depending on the voltage Vc (see FIG. 1) corresponding to the charging voltage of the main capacitor 3. Here, the V-F converter section 200A
To explain the operation, first, the output of the FF circuit 74 is at L level] and the output of the FF circuit 101 is at H level.

Since the output of the inverter 73 is at L level, the output level of the two OR gates 71 and 72 is the same as that of the FF circuit 74.
determined by the output level of That is, as described above, since the output of the FF circuit 74 is at L level, the output of the OR gate 71 is at L level. Then, transistor 52 is turned off and transistor 54 is also turned off.
The capacitor 55 starts charging with the constant current supplied from the constant current circuit 56. On the other hand, since the output of the inverter 75 is at H level, the output level of the OR gate 72 is at H level.
Since the level is reached, the transistor 62 is turned on, and the transistor 64 is also turned on. In other words, since the capacitor 65 is short-circuited by the transistor 4K, the capacitor 65 does not integrate the current of the constant current circuit 66.

Also, what are the resistors 49 and 50 (see Fig. 1 fi)?

Even when the main capacitor 3 is fully charged, the output voltage v
c is (#operation pressure + B - V' of transistor 54 ('B
), and the output voltage Va proportional to the charging voltage of the main capacitor 3 is set to be less than or equal to
．． 68 non-inverting inputs. Then, when the capacitor 55 performs an integrating operation and eventually becomes lower than the output voltage Vc applied to the operational amplifier 58K, the output of the operational amplifier 58 changes from L level to H level. Then, this H
The level output is supplied to the FF circuit 74 via the OR gate 59, so the output of this circuit 74 is inverted from L level to H level. This output, which is inverted and becomes H level, turns on the transistor 52 through the OR gate 71, and also turns on the transistor 54, so that the capacitor 55 is short-circuited, and the output of the operational amplifier 58 becomes H level again. to invert from to L level.

Therefore, since the output of the FF circuit 74 becomes H level, the output of the inverter 75 becomes L level, turning off the transistors 62 and 64, which had been on until then. Then, the capacitor 65 starts integrating. Eventually, the potential at the non-inverting input terminal of the operational amplifier 68 becomes lower.

The output of this operational amplifier 68 changes from L level to H level), and then passes through the OR gate 59 to the FF circuit 741C.
Since it is input, the output of this circuit 74 becomes L level. Therefore, the output of the inverter 75 does not go to H level, and the transistors 62 and 64 turn on to short-circuit the capacitor 65, so that the output of the operational amplifier 68 goes to L level. At this time, the transistor 52.
Since the capacitor 54 is turned off, the capacitor 55 starts integrating.

Since such an operation is repeated, the reason why the output of the FF circuit 74 is at L level is due to the capacitor 55.
It is determined by the integral time of .

Similarly, whether the output of the FF circuit 74 is at H level is determined by the integration time of the capacitor 65.

As described above, the capacitor 55.65 integrates the constant current of the constant current circuit 56.66, but as the output voltage Vc decreases, the integration time becomes longer; The higher the voltage, the shorter the integration time.

Therefore, the frequency of the pulses output from the FF circuit 74 is determined by the output voltage Ve4C, and as the charging voltage of the main capacitor 3 becomes lower #1, the frequency also becomes lower.

The V-F converter section 200A operates as described above.

Furthermore, the H level output of the F'F circuit 101 is as follows.

At the same time, the signal is also supplied to the AND gate 87, so this gate 87 is opened, and the pulse train signal sent out from the oscillation circuit 84 is passed through and input to the counter 8B to start counting. On the other hand, since the output of the FF circuit 89 is initially at the L level, the output of the inverter 92 is at the H level, and the gate of the AND gate 76 is open.As described above, the output of the FF circuit 74 is is initially at L level.

When this output becomes H level, it is supplied to the pulse generating circuit 77 via the AND gate 76 while the gate 76 is open.

The circuit 77 sends out the light emission stop signal C as a pulse.

This signal C is applied to the commutating thyristor 311 as described above.
It acts to stop the flash discharge tube Xi which is supplied with C and is emitting one light. Also.

The H level output from the AND gate 76 is as follows.

It is also supplied to the AND gate 81. At this time, since the output of the FF circuit 78 is initially at the L level, it is inverted by the inverter 79 and becomes the H level, so that the AND gate 81 is opened.

Therefore, the H level output that has passed through the AND gate 76 is supplied to the pulse generation circuit 82, which generates a one-shot pulse and supplies it as the light emission trigger signal Ag to the main circuit section 100A to trigger the flash discharge tube X. In addition to making it possible to emit light, this one-shot pulse
Since it is fed back to the circuit 78 and makes the output of the FF circuit 78 H level, the output a of the inverter 79
Since it is at L level, the AND gate 81 is closed.

When the output of the FF circuit 74 becomes L level, the output of the inverter 75 goes to H level and is supplied to the pulse generation circuit 83, which generates one pulse, and this pulse emits light. It is sent to the main circuit section 100A as a restart signal and acts to stop the flash discharge tube Xs which is in the process of emitting one light. K like this
Then, flash discharge tube X dish and X! The thyristors 26 and 31 alternately emit light, and each gate of the thyristors 26 and 31 is kept at a negative potential for the minimum necessary time as shown in FIGS. 14(C) and 14(D)K. , it is possible to repeat the firing and stopping of light accurately.

On the other hand, when the set time ZBFC, which is determined according to the time from when the front curtain of the focal plane shutter starts running to when the rear curtain finishes running, the counter 8B sends out a pulse, so that the output of the FF circuit 89 goes high. level. Therefore, since the output of the inverter 92D becomes L level, the AND gate 76 is closed, and then the 1i'F
When the output of the circuit 74 is inverted to H level, this H level signal is supplied to ANDGOO) 91. At this time, since the FF circuit 89 has already outputted the H level as described above, the AND/GO) 91 is opened and supplies the H level output to the pulse generation circuit 93, which generates the light emission end signal Ex. A one-shot pulse is generated and sent to the main circuit section 100A to stop the flash discharge tube X1 from emitting light, and is also sent to the FF circuit 74 as a reset signal.
A pulse is supplied to the reset terminal of #78, 89, 101 and the counter 88 to reset these circuits and return them to the initial state. Finally, the flash discharge tube's light emission has completely ended.

Note that the flash discharge tube control section 100 of the main circuit section 100A
A, a flash discharge tube control section 100A as shown in FIG.
, &C41i, the same effects as in this embodiment can be obtained. That is, in the control section 100As,
The cathodes of the diodes 44a and 48a are connected to the anodes of the thyristors 31 and 26, respectively, and the other configuration is the flash discharge tube control section 100A1.
is the same as

Next, a second embodiment of the present invention will be described based on FIGS. 5 to 7. As shown in sections 5 and 7, this second embodiment only partially changes the configuration of the first embodiment described above, so it uses the same structural members as the first embodiment. are given the same reference numerals to avoid repeated explanations.

The main circuit section 100B of this embodiment is configured as shown in FIG. That is, commutating capacitor 24 and thyristor 2
One end of a capacitor 121 is connected to the connection point Q with the anode of the capacitor 6, and the other end of the capacitor 121 is connected to the cathode of the diode 47 and one end of the capacitor 124. The other end of this capacitor 124 is a connection point P between the capacitor 24 and the anode of the thyristor 31.
Connected to 3. Further, one end of the capacitor 122 is connected to the above connection point QsK, the other end of this capacitor 122 is connected to the cathode of the diode 43 and one end of the capacitor 123, and the other end of this capacitor 123 is connected to the above connection point P. ,It is connected to the.

Furthermore, the first control circuit section 300 shown in FIG.
The difference from the control circuit section 200 of the embodiment (see II in FIG. 2) is that a light emission brightness detection circuit section 300A is used in place of the V-F converter section 200A, and the above-mentioned main circuit section is accordingly Only the interface with 100B has been partially changed.

That is, the output end of the FF circuit 101 is connected to the input end of an inverter 1170, and the output end of the inverter 117 is connected to the base of the transistor 134 constituting the light emission brightness detection circuit section 300A.

The circuit section 300A converts the light emitted from the flash discharge tubes into an electrical signal using a light receiving diode 131 provided near the reflector of the flash discharge tubes xl, x. That is, the cathode of the light receiving diode 131 is connected to the inverting input end of the operational amplifier 1330, and the anode of the light receiving diode 131 is connected to the non-inverting output end and grounded. Further, a resistor 132 is connected between the inverting input terminal of this operational amplifier 1330 and its output terminal. Furthermore, the output terminal of this operational amplifier 133 is connected to the collector of the switching NPN type transistor 134, and its emitter is grounded. The output terminal of the operational amplifier 133 is connected to the inverting input terminal of an operational amplifier 137 constituting a voltage comparison circuit. A resistor 135 and a variable resistor 13 are connected in series between the terminal to which the operating voltage element B is applied and the ground terminal.
The connection point between the resistor 135 and the variable resistor 136 of the voltage divider circuit consisting of 6 is connected to the non-inverting input terminal of the operational amplifier 137. The variable resistor 136 is a resistor whose resistance value is set depending on the shutter speed and the like. The output terminal of the operational amplifier 137 is connected to the input terminal of the inverter 139, and the output terminal is initially connected to an H level signal.
It is connected to a set input terminal of a flip-flop circuit 141 whose output becomes L level with the next H level signal. The output terminal of the FF circuit 141 is the pulse generating circuit 1
It is connected to the input end of 43. Also.

The output terminal of the FF circuit 141 is connected to the input terminal of an inverter 142, and the output terminal thereof is connected to the input terminal of a pulse generation circuit 149, and a light emission restart signal is sent from the output terminal of the pulse generation circuit 149. It looks like this.

In addition, the FF circuit of the total viewing time setting circuit section 200B
The output terminal of the FF circuit 89 is connected to one input terminal of an AND gate 144, and the output terminal of the FF circuit 89 is connected to one input terminal of an AND gate 145 via an inverter 146. The output terminal of the pulse generating circuit 143 is connected to the other input terminal of this AND gate 145, and the output terminal of the AND gate 145 is connected to the emission stop signal C of the first flash discharge tube X1 which makes the commutating thyristor 31 conductive. It is designed to supply

This signal C also serves as a light emission start signal for the second flash discharge tube X3. Further, the output terminal of the AND gate 145 is connected to one input terminal of the AND gate 147. Furthermore, the output terminal of the pulse generation circuit 143 is connected to an AND gate 14.
RESE is connected to the other input terminal of the AND gate 144, and transmitted from the output terminal of the AND gate 144 to all the reset terminals.
The T signal and the light emission end signal E for making the second commutation thyristor 39 conductive are sent out. Also, the other input terminal of ANDGOO) 147 is the FF circuit 1
The output terminal of the AND gate 147 is connected to the pulse generating circuit 148, and the light emission trigger signal A2 of the second flash discharge tube X3 is sent from the output terminal of the pulse generating circuit 148. It has become. Further, a reset signal is sent to the FF circuit 119 from the output terminal of the pulse generation circuit 148. The output signal from the photometric circuit section 200C passes through an inverter 114 and a pulse generation circuit 115, and a light emission end signal E1 is sent from its output end.

The second embodiment of the present invention configured as described above operates as an iC as follows.

First, the operation in the "flash light emission mode" is exactly the same as the first embodiment described above, so the explanation will be omitted.

Next, before explaining the operation in the "continuous light emission mode", the operation of the flash discharge tube control section of this embodiment is shown in FIG. 6(A).
, (B). Capacitors 121 and 122° 12a just before flash discharge tube X1 emits light
, 124 are as shown in FIG. 6(A). In this state, when the light emission trigger signal A1 and the light emission start signal B are supplied from the control circuit section 300, the trigger signal is applied to the trigger electrode of the flash discharge tube X1, and the light emission start signal is applied to the gate of the thyristor 26. B is added. Then, this thyristor 26 is turned on, and even if the discharge tube X1 emits light, the capacitor 121
The potential range of ~124 remains as shown in FIG. 6(A). Subsequently, when the 1-light emission stop value number C is applied, the thyristor 31 is turned on, the second flash discharge tube Resistor 27 → Resistor 42
→ Diode 43 → Capacitor 123 (-) → Path M1 and Capacitor 123 (+) → Thyristor 31 →
Thyristor 26 (cathode-anode) → capacitor 1
22→capacitor 123 (-) path M2, a reverse bias is applied between the gate and cathode of the thyristor 26, and at the same time the commutating capacitor 24
The thyristor 26 is quickly cut off since commutation also takes place. When this cut-off is performed, the discharge 11L current flowing through the flash discharge tube The flow flows through the path of tube X1 → capacitor 24 → thyristor 31 and the path of discharge tube X1 → capacitor 121 → capacitor 124 → thyristor 31, so that the capacitor 24
, 121 to 124 are charged to the charge complementarity shown in 61 id (B), and the gate reverse bias applied to the thyristor 26 is instantly eliminated as described above.

Then, when the light emission restart signal is again applied to the gate of the thyristor 26, the thyristor 26 is turned on and the charge stored in the capacitor 121 Vc is transferred from the capacitor 121 (+) to the thyristor 26 to the resistor 3. -2→
The path of resistor 46 → diode 47 → capacitor 121 (-) and capacitor 121 (+) → thyristor 26 →
Thyristor 31 (cathode-anode) → capacitor 1
24→capacitor 121(-), the gate and cathode of the thyristor 31 are reverse biased. At the same time, commutation is also performed by the commutation capacitor 24, so the thyristor 3
The capacitor 24.1 should not be cut off rapidly, and the discharge current from the flash discharge tube X3 will cause the capacitor 24. -121 to 124 are not in the state shown in FIG. 6(A) K, and the gate reverse bias to the thyristor 31 described above disappears. In this way, the reverse bias applied to the thyristors 26, 31 is applied only for the minimum necessary period, and is immediately extinguished once the period ends. In this manner, the flash discharge tube control section operates.

The operation in the case of "continuous light emission mode 9" will be explained. In this case, the movable contact piece of the mode changeover switch 95 is connected to the fixed terminal 95a Ic as in the first embodiment described above. In this state, the flat light emission signal is X! When the flash discharge tube X1 is applied, the light emission trigger signal A1 and the light emission start signal B are applied as in the first embodiment, and the flash discharge tube X1 starts emitting light. On the other hand, at the same time, the H
The one-shot pulse of the same level sets the FF circuit 101, and the output of the FF circuit 101 becomes H level, is inverted by the inverter 117, becomes L level, and turns off the transistor 134. Now the luminance brightness detection circuit section 300
A enters the operating state. The photodiode 131 that receives the rising light emitted by the first flash discharge tube A variable resistor 136 is applied to the inverting input terminal of the variable resistor 136, and the resistance value is set according to information such as film sensitivity, aperture value, shutter speed, and subject distance.
and a brightness determination level which is a reference potential set by a voltage dividing circuit of resistor 135. When this comparison voltage exceeds the reference potential, the output of the operational amplifier 137 is inverted and becomes the L level, and this L level output is inverted by the inverter 139 to set the JIFF circuit 141 to the H level.

The output of the FF circuit 141 causes the pulse generation circuit 143 to output a one-shot pulse, which is input to the AND gate 145. AND gate 145 is total viewing time setting circuit section 20
Since the output from the pulse generation circuit 143 is passed through the AND gate 145 as it is and becomes the light emission stop signal C, the capacitor 34.0B in FIG. Commutation thyristor 3 via resistor 33
1 conducts. The electric charge stored in the commutation capacitor 24 applies a reverse bias to the main trigger thyristor 26.

The fifth flash discharge tube X1 stops emitting light. Further, the output of the AND gate 145 is applied to one input terminal of the AND gate 147. When the light emission of the first flash discharge tube X1 becomes attenuated light emission, the light emission brightness decreases, so at this time,
The operational amplifier 137 is inverted again and becomes H level.

On the other hand, the one-shot pulse output of the pulse generating circuit 98 sets the FF circuit 119, its output side becomes H level, and the AND gate 147 is opened.

Therefore, the output simultaneously with the light emission stop signal C that has passed through the AND gate 145 causes the pulse generation circuit 148 to generate a one-shot pulse via the AND gate 147. This is the light emission trigger signal AS of the second flash discharge tube X8, and is the capacitor 19 in FIG. The second trigger iris 16 is made conductive via the resistor 18 .

The electric charge charged in the second trigger capacitor 14 is transferred to the second trigger capacitor 14.
Discharge to the primary coil of trigger transformer 15.

A high voltage is generated in the secondary coil and the second flash discharge tube
2 trigger electrodes. In addition, since the commutating thyristor 31 is in a conductive state due to the signal C, the second flash discharge tube X transfers the charge stored in the main capacitor 3 to the second flash discharge tube It starts emitting light as it flows through the air.

Then, the emission brightness rises again, and when the output of the operational amplifier 133 reaches the set level of the emission brightness detection circuit 300A, the output of the operational amplifier 137 is inverted and becomes L level, and the inverter 139 changes it to H level and the FF circuit 141
Enter. This FF circuit 141 is a flip-flop circuit in which the first H level signal causes the output to be H level, and the 91st H level signal causes the output to become L level. The output is L level. This L level signal becomes H level via the inverter 142, and the pulse generating circuit 149 generates a one-shot pulse. This is the light emission restart signal for the second flash discharge tube X2, and is the OR circuit 30 in FIG. Main thyristor 26 is made conductive via capacitor 29 and resistor 28. At this time, the commutating capacitor 24 is connected to the flash discharge tube XI.
h Commutation capacitor 24. Since it was being charged by the current flowing through the thyristor 31, the Qa side was (+).

The P3 side is charged in the form of (-), and the thyristor 26
Since K becomes conductive, the commutating thyristor 31 is reverse biased by the electric charge charged in the commutating capacitor 24, thereby stopping the second flash discharge tube X2 from emitting light.

Since the main thyristor 26 is turned on again within the deionization time, the flash discharge tube X starts emitting light again.

Please repeat the above steps. 1. The second flash discharge tubes X1 and X2 alternately emit light, resulting in continuous light emission (flat light emission).

Then, the preset counter 88 preset by the total viewing time setting signal x3 outputs an H level signal after counting the pulses of the constant pulse train from the oscillation circuit 84, so the output sets the FF circuit 89. That H
The level output is andgoo) 144 open. Through this AND GO) 144 pulse generation circuit 143, the ONE SHI hit pulse is passed.

Since the reset signal RESET resets each operating circuit, the control circuit section 300 returns to the initial state, and the reset signal becomes the light emission end signal E3, and the fifth
Figure 20. Capacitor 20a and resistor 20
The second commutating thyristor 39 is made conductive through b, and whichever flash discharge tube is emitting light, it immediately stops emitting light.

In both embodiments 1 and 2 described above, two flash discharge tubes are used.
Although this was described above, it is not necessarily necessary to use two of the discharge tubes.

Next, a third embodiment of the present invention using one flash discharge tube will be described with reference to FIGS. 8 and 9.

FIG. 8 shows the main circuit section 100C.

The main difference from the first embodiment (see Figure 1) is as follows.

Since only one flash discharge tube is used, the discharge tube control section and the like are naturally removed.

The anode of the thyristor 31a is connected to the line h, and the cathode of the thyristor 31a is connected to the line h.
connected to the anode of the Also.

One end of a resistor 32a is connected to the gate of the thyristor 31a, and the other end of the resistor 32a is connected to the anode of the thyristor 31. Further, the gate of the thyristor 31a is connected to the capacitor 2 through a resistor 28b.
The other end of the capacitor 29b is connected to the output end of the OR gate 30b, and one input end of the OR gate 30b is supplied with a charging start signal G1 from the control circuit section 400 described below. are connected like this. The other input end of the above-mentioned OAG) 30b is also connected so that the recharging signal G2 is supplied from the control circuit section Yanagi.

Further, one input terminal of the OR gate 30 is connected so that the light emission start signal B is supplied from the control circuit 400, and the other input terminal is similarly connected so that the light emission restart signal is supplied. has been done.

Further, the gate of the thyristor 31 is connected to the output end of the OR gate 30a via a series circuit of a resistor 33 and a capacitor 34. And - and oagu) 3
One input terminal of 0a is connected so that the light emission end signal E supplied from the control circuit section 400 is applied,
The other input terminal of the OR gate 30a is the light emission stop signal C.
is connected so that it is supplied with

Further, as shown in FIG. 9, the control circuit section 400 includes:
Total light time setting circuit section 200B, photometry circuit section 200C
, a light emission start signal input section 200D, and a light emission brightness detection circuit section 300A, all of which have already been described, and will not be described again.

The output terminal of the operational amplifier 137 constituting the luminance brightness detection circuit section 300A is connected to the input terminal of the inverter 1390 and the cathode of the diode 138.
38 anodes are grounded. Further, the output terminal of the inverter 139 is connected to the input terminal of the FF circuit 141, and the output terminal of the FF circuit 141 is connected to one input terminal of the AND gate 151. Further, the output terminal of the FF circuit 141 is connected to one input terminal of the busy AND gate 158 so as to supply the one light emission stop signal C to the main circuit section 100C. This and gate 15
The other input terminal of 8 is connected to the total light time setting circuit section 200.
It is connected to the output end of the FF circuit 89 constituting B. The AND gate 158 then receives the reset signal R.
It is designed to supply ESET, and the FF circuit 116
．． It is connected to the reset terminal of the counter 88 and the FF circuit 89.

Further, the output terminal of the FF circuit 89 is connected to the input terminal of an inverter 154, and the output terminal of this inverter 154 is connected to the input terminal of the delay circuit 1560 and the above-mentioned ant.
51.

The output terminal of this AND gate 151 is connected to the input terminal of a delay circuit 152, and the output terminal of the delay circuit 152 is connected to a pulse generation circuit 153 that generates a one-shot pulse, and the output terminal of this generation circuit 153 is connected to the input terminal of the delay circuit 152. Recharge signal G! occurs, and the main circuit section 1000 is connected to the main circuit section 1000. Further, the output terminal of the delay circuit 156 is connected to the input terminal of the pulse generation circuit 1570, and a light emission restart signal is generated from the output terminal of the pulse generation circuit 157, and this signal is supplied to the main circuit section 1000K. connected so that

Next, the operation of this embodiment configured as described above will be explained. In the case of the "flash light emission mode", the operation is exactly the same as that of the first embodiment already described, so a repeated explanation will be omitted.

In the case of "continuous light emission mode", when the flat light emission start signal 3:1 is applied as described above, the pulse generation circuit 98
A pulse is generated from This pulse is OR gate 102
A light emission trigger signal A1, a light emission start signal B, and a charge start signal GK are supplied to the main circuit section 1000K, respectively, to cause the flash discharge tube X1 to emit light and to activate the thyristor 3.
1a is turned on to charge the commutation capacitor 24. Further, the above pulse is also supplied to the FF circuit 116 to activate the first light emission brightness detection circuit section 300A and open the gate of the AND gate 118 to allow the pulse generated by the oscillation circuit 84 to pass. When the luminance of the flash discharge tube X increases, the circuit section 300A performs the same process as described above, and causes the FF circuit 141 to generate a pulse.

As this Pulse light emission stop signal C, the main circuit section 100
C and turns on the thyristor 31.

Since the charge stored in the commutating capacitor 24 is discharged and the thyristor 26 is cut off, the flash discharge tube X1
emits attenuated light. Further, the above pulse is transmitted to the delay circuit 152 via the AND gate 151. Now, the delay time of the delay circuits 152 and 156 is 1. , 1.
and ts<ts, and t・x is bulk>ts
xoff (However, tu10111a thyristor 31
Assume that K is set (time required for cutoff). With this setting, the FF circuit 141
After one hour t1 has elapsed, a light emission restart signal is sent from the pulse generation circuit 157, causing the flash discharge tube X1 to emit light. When 1 hour has passed, a recharge signal Gs is sent from the pulse generating circuit 153, which turns on the thyristor 31a and rapidly charges the commutation capacitor 24 through the path of thyristor 31a → capacitor 24 → thyristor 26. Let's do it.

By repeating the above operation repeatedly, the flash discharge tube x1 is caused to emit light repeatedly. When the set time has elapsed, the output of the FF circuit 89 constituting the total viewing time setting circuit section 200B becomes H level, and the AND gate 151 is closed.

At the same time, the gate of the AND gate 158 is opened, and the above-mentioned H level output is sent from the gate 158 to the reset signal R.
This signal RISET resets the FF circuit 116.89 and the counter 88 to stop all circuits.

Note that even if a high-speed trigger circuit is used for the trigger circuit of the thyristors 26 and 31 used in this embodiment, the reverse bias circuit described above can produce the same effect as a multi-emission flash.

Also, instead of the reverse bias circuit shown in this embodiment, a second
Of course, the reverse bias circuit used in the embodiment (see FIG. 5.7) may also be used.

Next, a fourth embodiment of the present invention will be explained based on FIGS. 10 and 11.

FIG. 1θ shows the main circuit section 100D.

The only difference from the main circuit section 100C of the third embodiment (see FIG. 8) is the flash light emission control section 100Dl.

The flash emission control unit 100D* includes a thyristor 26°3
1, 163 and capacitors 24, 164, 173
, 195, 202 and resistance 25.27, 162, 165
,166,168,171,172゜175 ,177
, 178 , 180 , 181 , 184 , 185
, 187.191°192 , 194 , 196 ,
198, 199 and diode 169, 197°20
1 and NPN transistors 174, 179, 186
, 189, PNP type transistors 176, 183, and transistors 182, 188, 193 are connected as shown in FIG. 1O.

Further, FIG. 11 shows a control circuit section 500, which includes a photometry circuit section 200C, a light emission start signal input section 2
00D, emission brightness detection circuit section 300A and OAG) 102, 204 and inverters 104, 114
, 117.

139, 209 and FF circuits 89, 103, 11
6, 205.

Pulse generation circuit 115 that generates one-shot pulses
, 149 , 201 , 207 , 208 , 211 , Antgelt 202 , 203 , 212 , and resistor 8
6, 104a, a capacitor 85, an oscillation circuit 84, and a counter 88.206 are connected as shown in the figure.

Next, before explaining the operation of this embodiment configured as described above, the operation of the flash light emission control section 100Ds will be explained.

Transistors 174, 176 #179, 183
, 186, 189 is powered by capacitor 1.
It has a charge of 95 K. tb, the voltage divided by the dividing resistors 194 and 196 serves as a charging voltage for the capacitor 195. In this state, when the light emission start signal B or the light emission restart signal R is applied, the transistors 189 and 183 are turned on in sequence.
Line h → Diode 197 → Resistor 196 → Transistor 183 → :f N7' Sensor 202 → Cm y,
A gate current flows through the path of the gate of the thyristor 26, turning on the thyristor 26 and charging the &'c':1 capacitor 202. Also, the light emission stop signal C! Alternatively, when the light emission end signal E is generated, the transistor 186 is turned on and the electric charge charged in the capacitor 202K is transferred to the capacitor 2.
02(+) → Transistor 186 → Resistor 27 → Resistor 19
8 → The capacitor 202 (-) is discharged, and the gate of the thyristor 26 is reversely biased. And transistors 174, 176, 179 and resistor 168
, 172, 171 and the diode 169 also performs the same operation as described above.

Note that the resistors 168, 172, 198, 199
The magnitude of each resistance value is resistance 198> resistance 199
．． The resistor 172 is set as the resistor 168, and the gate current of the thyristor 26 is passed while charging the capacitor 202, or the gate current of the thyristor 31 is passed while charging the capacitor 173.

Both of these capacitors 173 and 202 are charged by flowing a large current in a short period of time. Conversely, when the capacitor 202 discharges, the resistor 198.
The value of capacitor 202 is set.

First, the operation of the "flash light emission mode" will be explained. As in the previously described embodiment, the flash light emission start signal X! is applied, a light emission trigger signal A and a light emission start signal B are sent from the OR gate 102 to the capacitor 12 of the main circuit section 100D.
And or gate 193 and busy are applied. Then, a trigger voltage is applied to the flash discharge tube X1, and the transistor 18
Since transistor 9 is turned on, transistor 183 is also turned on.
Line h → diode 197 → resistor 196 → transistor 183 → co-diode 201 → resistor 199].

capacitor 202-) C resistor 198 A current flows in the path of the gate of the thyristor 26 and makes the thyristor 26 conductive, so that the flash discharge tube Xi emits light. Further, when the brightness determination level is exceeded, the photometric circuit section 200C is activated, and the pulse generation circuit 115 sends out a one-shot pulse light emission end signal E, and the main circuit section 100C is activated.
0D OAG) is applied to 182. Then, the transistor 179 turns on, so the transistor 179 turns on.
6 is also not on, line h → diode 197 → resistor - [
196-+) Langimeta 1 flow capacitor 173-+
[≦To the customer 721°1694MK168] → Thyristor 3
A current flows through the path of the gate No. 1, turning on the thyristor 31. As a result of this turning on, the electric charge charged in the commutation capacitor 24 is discharged, and the thyristor 26, which has been in a conductive state, is reverse biased, and this thyristor 26
Since the flash discharge tube X1 is turned off, the flash discharge tube X1, which is emitting light, stops emitting light, and proper flash photography is completed.

Next, the operation in the case of "continuous light emission mode" is as follows:
It becomes like the time chart shown in W. As is clear from FIG. 12, the gate potential V of the thyristor 26.31
1 m Vg is biased in the negative direction for the minimum necessary time, so that there is no adverse effect when the next signal to turn on the thyristor 26, 31 arrives.

Note that the signal X'4Fi*light emission interval setting signal input to the counter 206 is also input to the pulse generating circuit 208°2.
Light emission restart signal D I +D sent from 07 respectively
The pulse width of the mushroom needs to be set to be longer than the time required for Cyrisk 26.31 to cut on or cut off.

For example, if a Mitsubishi Electric thyristor (CR3JM-8> is used as the thyristor 26.31 above, the resistor 19
9=200. When the capacitor 202 = 0.1 μF and the voltage of the capacitor 195 = 30 V, the pulse width of the signal D1 is 5 μs to 10 μs, and the pulse width of the signal D2 is 250 V to 330 μs when the voltage of the main capacitor 3 is 250 V to 330 μs.
When the time is between 3 and 5 μs. That is.

When the above CR3JM-8 is used as a thyristor.

Assuming that the commutation capacitor 24 is 2.2 μF, the thyristor 31 is turned on to perform commutation, and at the same time, the gate of the thyristor 26 is reverse biased.

Since this thyristor 26 is cut off in about 3 μs, a reverse bias time for a sufficiently reliable cutoff can be obtained. Also, based on the same idea as above, the light emission stop signal C
The pulse width of i r C2 can also be determined.

Further, the recharge signal G generated from the pulse generation circuit 211 generates a pulse at the falling edge of the 1 light emission restart signal Ds.

That is, by outputting the signal G after the thyristor 31 is surely cut off, the thyristor 163 is cut off.
is turned on. If the above thyristor 3
The above thyristor 163 until t where the cutoff of 1 is uncertain.
When cut on, the tiling load charged in the main capacitor 3 will be discharged along the path from the thyristor 163 to the thyristor 31.

Furthermore, the reason why the FF circuit 205 and the OR gate 204 are provided and the light emission stop signal C3 and the light emission restart No. 46 D1 are applied to the OR gate 204 is as follows. That is, when the prescribed luminance is reached, the output of the operational amplifier 137 is inverted, and a pulse is generated from the pulse generating circuit 149 or 201 to perform commutation. This is because the light emitting brightness detection circuit 300A is not activated by inputting the signal (good) to the FF circuit 116 via the OR gate 204 and setting the output of this circuit 116 to the L level. In other words, we are looking at the emission brightness closely.

This is to prevent the possibility that the operational amplifier 137 may erroneously output an output due to the influence of external light when the discharge tube stops emitting light, although it is not affected by external light because the luminance of the discharge tube is high during light emission. be. Then, when the 1-light emission restart signal DI (a signal signal may be applied), the output of the FF circuit 116 becomes H level.

The detection circuit 300A is now activated again.

(Effects) According to the present invention, a reverse bias is applied between the anode and cathode and between the gate and cathode of a conductive semiconductor switching element to cut off the semiconductor switching element and perform the necessary steps for this cutoff. After a minimum amount of time has passed, the potential between the gate and cathode is reduced to almost zero.

Even when gate control signals are applied at minute intervals, the semiconductor switching element can accurately repeat on/off operations.

[Brief Description of the Drawings] Fig. 1 is an electric circuit diagram showing the main circuit of a continuous flash flash device according to the first embodiment of the present invention, and Fig. 2 shows the connection to the main circuit shown in Fig. 1 above. FIG. 3 is an electrical circuit diagram showing a control circuit. Figures 3 (A), (B), and (C) are electric circuit diagrams for explaining the operation of the flash discharge tube control section of the main circuit shown in Figure 1 above, and Figure 4 is a diagram similar to Figure 1 above. FIG. 3 is an electric circuit diagram showing a modification of the flash discharge tube control section of the main circuit shown in FIG. Figure 5 is an electrical circuit diagram showing the main circuit of a continuous flash flash device according to the second embodiment of the present invention, Figure gg6 (A),
(B) is an electric circuit diagram for explaining the operation of the flash discharge tube control section of the main circuit shown in FIG. 5; FIG. 7 is an electric circuit diagram showing a control circuit connected to the main circuit shown in FIG. circuit diagram. FIG. 9 is an electric circuit diagram showing a control circuit connected to the main circuit shown in *5ryI above. FIG. 1θ is an electrical circuit diagram showing the main circuit of a continuous flash flash device according to a fourth embodiment of the present invention. FIG. 11 is an electric circuit diagram showing a control circuit connected to the main circuit shown in factor 10 above, and FIG. 12 is a time diagram showing the operation of the "continuous light emission mode" in the strobe device of the fourth embodiment above. chart. Fig. 13 is an electrical circuit showing the main circuit of a conventional continuous flash flash device. Fig. 14 (A), CB), (C), and (D) show potential changes at the gate of the main thyristor, respectively. FIG. 24... Commutation capacitor 26... Main thyristor 31... Commutation thyristor 41, 45, 121-124, 173, 202...
・Capacitor 43.44.47.48...Diode patent applicant Olympus Optical Industry Co., Ltd. Figure 4 Hi1 Hi2 1:lLJ
U-measure 1411Z Denii T Procedural amendment (voluntary) 1. Indication of the case 1982 Patent Application No. 148756 2. Title of the invention Continuous emitting strobe device 6. Relationship with the person making the amendment Patent applicant location Tokyo 2-46-2 Hatagaya, Shibuya-ku, Tokyo Name (037) Orinokus Optical Industry Co., Ltd. 4
, Agent Address: 5-52-14-5 Matsubara, Setagaya-ku, Tokyo.
The "Detailed Description of the Invention" column of the specification subject to amendment, Drawing 6, Contents of the amendment (1) Added "reta" after "connected" at the end of line 15 on page 15 of the specification. Masu. (2) Shiji 7 ~, described in the second line of page 28,
Delete "Line 21" written in the 6th line of the same page after "7". (3) Delete the text after “45 is” in line 10 of page 28 of the same page to the end of line 11 of page 28, and delete “Capacitor 4
5 (+) → Anode/cando of thyristor 31 → Line, 8o → Resistor 32 → Resistor 46 → Diode, delete the part before "Line 2," written at the end of line 19 on the same page, and read "Also, ”. (5) Delete "is hardly charged" in line 7 on page 61 of the same document, and replace "is, capacitor 41(+)".
→ Anode/cathode of thyristor 26 → Line 1o →
Resistor 27 → Resistor 42 → Diode 43 → Capacitor 41
Substitute (-) and "-" which is discharging. (6) "Brightness" stated in page 66, line 14 of the same
Correct the light intensity to J. (7) The “amount” stated in page 51, line 13 of the same
Change it to "Brightness". (8) Next to the "input terminal" listed on page 58, line 8, add "and one input terminal of AND gate 159." (9) "Delay circuit 156" in the 59th purchase will be corrected to "the other side of AND gate 159." (10) r 151 stated in page 61, line 15 of the same
After J, add r and 159J. (11) Delete the text after "Nari" written in the first line of the 64th purchase and before "→Transistor" written in the second line of the same page, and substitute "Capacitor 195". Masu. 1 (12) Delete the text after “Nari,” written in line 16 of page 65 of the same page and before “→transistor” written in line 17 of the same page, and substitute “capacitor 195.” To do. (13) "Brightness" stated in the 66th purchase initial publication will be corrected to "appropriate luminous intensity." (14) Delete the text after "Nari," written in the 6th line of page 66 and before "→transistor" written in the 7th line of the same page, and substitute "capacitor 195". Masu. (15) Figure 9 of the drawings attached to the application has been revised as shown in the attached drawing.

Claims (1)

[Claims] A series circuit including a power supply, a main capacitor, a flash discharge tube inserted in a discharge loop of the main capacitor, and a semiconductor switching element is provided, and the on/off operation of the semiconductor switching element is extremely controlled. This is a continuous flash flash device that repeatedly emits light at high speed, and by applying a reverse bias between the anode and cathode of the semiconductor switching element, the semiconductor switching element is cut off, and in synchronization with the operation, the semiconductor switching element is also cut off between the gate and cathode. 1. A continuous light emission type strobe device, characterized in that a means is provided for applying a reverse bias and for releasing the reverse bias between the gate and the cathode immediately after the cutoff operation is completed.