JPS61274536A - Communication control equipment - Google Patents

Abstract

PURPOSE:To attain simply the communication control of channels having different speeds by giving the direct transfer control to the control information channel part via a microprocessor and using an exclusive transfer controller which is started by a processor to control the information channel part. CONSTITUTION:A microprocessor 10 starts an information channel transmission and reception parts 11 and 12 when the command word indicates the transmission and the reception respectively. Then the parts 11 and 12 control a storage address register 15 or 16 and controls the transfer of data between a buffer 17 or 18 and a storage part. While the processor 10 gives -1 to the contents of a byte counter 37 or 38 for each transfer of a byte and finishes the transmission/reception control when the counter 37 or 38 is set at 1. While a transmission data control part 13 allocates the information channel of the reception data to a conversion processing part 19 and the signal channel to a conversion processing part 20 respectively. Then the transmission data delivered from both parts 19 and 20 are arrayed into a prescribed style and sent to a communication circuit.

Description

[Detailed Description of the Invention] [Summary] This is a control method for a communication control device that controls a high-speed digital data communication line. Data multiplexed and transmitted on the line is divided into a high-speed information channel portion and a low-speed control information channel portion, the control information channel is directly transferred and controlled by the microprocessor, and the information channel portion is directly controlled by the processor. By controlling by a dedicated transfer control means activated by , communication control of channels with different speeds is possible with a relatively simple configuration.

[Industrial application field]

The present invention relates to a control method for a communication control device that controls a high-speed digital data communication line.

In high-speed digital data communication lines, a method is often used in which a high-speed information channel and a low-speed control information channel (signal channel) are time-division multiplexed and transmitted.

For example, a high-speed digital communication line of 6312 Kbps (kilobits per second) has 168K, consisting of a 6144Kbps information channel, a 64Kbps signal channel, etc.
Control information equivalent to bps is multiplexed and transmitted.

In such data transmission/reception processing, an economical configuration is desired that allows the processing to be executed at an appropriate processing speed depending on each transmission speed.

[Prior art and problems to be solved by the invention] FIG. 3 is an explanatory diagram of the - format of data transmitted over the above-mentioned high-speed digital data communication line.

In the system shown, the transmitted data consists of 789 bits, consisting of 96 channels of 8-bit information channel 1, 8-bit signal channel 2 and protection channel 3, and 5-bit service information channel.

By transmitting data in this format at 6312 Kbps, the information channel part has a total of 6144 Kbps, and the signaling channel and protection channel each have a speed of 64 Kbps.
It is clear that the service information channel is 40 Kbps.

The communication control device includes, for example, a storage unit 5 as shown in FIG.
, a line control section 6, a processor section 7, and an interface control section 8 are connected by a bus 9. The line control section 6 connects to a communication line, and the interface control section 8 connects to a host device.

When applying a known control method of a conventional communication control device to the data reception and reception processing as described above, a line control word for each channel is provided in the storage unit 5, and a control method for each processing is applied. Store information, status information, etc.

The common control mechanism of the line control unit 6 reads out the line control words one after another at regular intervals, and automatically connects lines of various communication speeds by executing the control specified by the information of the control words. Configure it to scan as often as you want.

Such a time-sharing processing method is adopted as an economical method when controlling a large number of relatively low-speed communication lines. However, when controlling high-speed lines, the proportion of overhead due to the switching time of control using line control words gradually increases, and in order to cope with this, it is necessary to increase the speed of memory and control circuits, and the equipment is The problem of pricing arises.

[Means for solving problems]

FIG. 1 is a block diagram showing the configuration of the present invention.

The figure shows the configuration of the line control section 6, in which 1o is a microprocessor, 11 is an information channel transmission control section, 12 is an information channel reception control section, and 13 is a transmission data control section.

[For production]

The microprocessor 10 reads the command word from the storage section 5 according to the designation from the processor section 7, and controls the information channel transmission control section 11 when the command word is a transmission command, and controls the information channel reception control section when the command word is a reception command. 12.

Each control unit 11.12 has a storage address register 15 or 1
6 and the buffer 17 or 18 and the storage section 5.

Control data transfer.

The conversion processing unit 19 converts the transmission byte data of the buffer 17 into a bit serial signal and passes it to the transmission data control unit 13, and also receives and receives the received data bit string from the transmission data control unit 13, and sequentially transfers the data bytes to the buffer 18. do.

Further, the conversion processing unit 19 converts the received data into, for example, HD
The range of valid data is identified by detecting the flag bit pattern defined in the LC transmission control procedure.

When the transmission or reception of designated data is completed, the information channel transmission control section 11 or the reception control section 12 notifies the microprocessor 10, and the microprocessor 10 notifies the processor section 7 of the completion of the transmission and reception.

The transmission data control section 13 distributes the information channel of the received data to the conversion processing section 19 and the signal channel to the conversion processing section 20 according to the data format shown in FIG.

Furthermore, the transmission data passed from the conversion processing units 19 and 20 is arranged in a predetermined format and sent to the communication line.

The conversion processing unit 20 exchanges data such as signal channels with the microprocessor 10, and the microprocessor 10 directly processes data such as the signal channels.

With the above configuration, the data of the high-speed information channel is efficiently processed by the dedicated control unit, and the data of the low-speed signal channel is processed by allocating part of the processing power of the microprocessor that controls the entire line control unit. , the control mechanism can be constructed economically.

〔Example〕

In FIG. 1, a microprocessor 10 executes a microprogram stored in a control memory 30 to perform overall control of the line control section 6 and specific control described below.

Upon receiving the control signal from the processor section 7, the microprocessor 10 reads out the command word at a predetermined storage address in the storage section 5.

When the microprocessor 10 accesses the storage unit 5, it sets a storage address in the storage address register 31 and sends an access request signal to the storage control circuit 32, and in the case of reading, the data is transferred to the data register 33.
In the case of reading and writing to the data register 34 in advance,
A write operation is performed by transferring the data set to the storage unit 5.

In the line control unit 6, access requests are issued not only from the microprocessor 10 but also from the information channel transmission control unit 11 and the information channel reception control unit 12 as described later, so the storage control circuit 32 identifies the request source. , controls the address switch 35 and the data switch 36, and selects the corresponding register.

When the microprocessor 10 reads the command word, if the command word is a transmission command, the information channel transmission control unit 11
In the case of reception, the information channel reception control section 12 is activated.

Also, the start address of the storage area for the transmitted/received data specified by the command word is set in the storage address register 15 or 16, and the size of the storage area also specified by the control word, ie, the schedule of the transmitted/received data, for example, is set. number of bytes) is set in the byte counter 37 or 38.

Each control unit 11.12 has a storage address register 15 or 1
6 to control the data transfer between the buffer 17 or 18 and the storage section 5, and set the contents of the byte counter 37 or 38 to 1 every time one byte is transferred.
Or, if 38 becomes 0, the transmission/reception control currently being executed is terminated.

Buffers 17 and 18 are so-called first-in-first-out (FIF) that hold the required number of bytes in a byte-serial shift register configuration.
O) method buffer.

The buffer 17 sequentially inputs and holds the transmission bytes read out from the storage section 5 to the data register 39, and the conversion processing section 19 reads them in the order of input. The buffer 18 sequentially inputs and holds the received bytes from the conversion processing section 19, and sends them out to the storage section 5 via the data register 40 in the order of input.

The conversion processing section 19 converts the transmission byte data in the buffer 17 into a bit serial signal and passes it to the transmission data control section 13 . Also, by receiving the received data bit string from the transmission data control unit 13 and detecting, for example, a flag bit pattern prescribed in the IDLC transmission control procedure, the range of valid data is identified, and the valid data bytes are stored in the buffer 18. Transfer sequentially.

When the end of the specified data transmission process is detected by the byte counter 37, or the end of the reception process is detected by the byte counter 38 or the flag bit pattern,
The information channel transmission control section 11 or reception control section 12 notifies the microprocessor 10, and the microprocessor 1
0 notifies the processor section 7 of the end of transmission and reception.

As described above, the information channel data transmission/reception processing is performed from the microprogram 10 to the information channel transmission control unit 11.
Alternatively, by activating the information channel reception control section 12, the processing is thereafter executed independently of the microprocessor 10.

During this time, the transmission data control section 13 converts the information channel of the received data to the conversion processing section 19 in accordance with the data format shown in FIG.
Then, the signal channels are distributed to the conversion processing section 20. Furthermore, the transmission data passed from the conversion processing units 19 and 20 is arranged in a predetermined format and sent to the communication line. In this example, it is assumed that the backup and service information channels are not used, and the transmission data control unit 13 processes them as dummy bit strings as appropriate.

The conversion processing unit 20 has functions of serial/parallel signal conversion and buffering for relaying signal channel data between the microprocessor sensor 10 and the transmission data control unit 13.

The microprocessor IO sends and receives data on the signal channel to and from the conversion processing section 20 for processing, and if necessary, transfers data sent and received on the signal channel to and from the storage section 5, etc.
Processing related to signal channels is performed in parallel.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, a communication control device for controlling high-speed digital data communication can be constructed economically, which is a remarkable industrial advantage.

effective.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of an example of the configuration of a communication control device, and FIG. 3 is an explanatory diagram of a transmission data format. In the figure, 5 is a storage section, 6 is a line control section, 7 is a processor section, 10 is a microprocessor, and 11 is an information channel transmission control section. 12 is an information channel reception control unit, 13 is a transmission data control unit, 15.16.31 is a storage address register, 17.18
is the buffer, 19.20 is the conversion processing unit, 33.34
．． 39.40 is a data register, and 37.38 is a byte counter. Little Burning Moon's Furusegu Material Japanese Zuf'rock Rokko 1 Mouth Communication I&JftP Koji 1 Lecture Equipment 11 Brotu 7 Kokuro
2 Mouth 6L Theta Jibu's theory 5th month evening F 3 Mouth

Claims (1)

[Claims] In a line control unit (6) that controls transmission and reception of data between a storage unit (5) of a communication control device and a communication line, a microprocessor (10); transfer control means (11, 12) that is activated and operates independently of the microprocessor (10) to control the transfer of transmitted and received data between the specified area of the storage section (5) and the communication line; , divides the data received from the communication line according to a predetermined transmission/reception data format, and transmits the data to the transfer control means (11, 12).
) and the microprocessor (10), and means (13) for combining the data transferred from the transfer control means (11, 12) and the microprocessor (10) and transmitting the combined data to a communication line. A communication control device characterized by: