JPS61274350A - Substrate bias generating circuit - Google Patents

Abstract

PURPOSE:To realize high speed and stable operation of an integrated circuit by a method wherein the source voltage of an oscillator for back-bias generating clock is clamped and a clock amplitude is restricted to a certain value. CONSTITUTION:The source voltage VCC of an oscillator 12 for back-bias generating clock is clamped by a source voltage clamping circuit 13 and the back-bias (-VCC) is applied to a semiconductor substrate 15 through a substrate electrode 14. One end of the source voltage clamping circuit 13 is connected to the source voltage (VCC) and the other end is connected to the source terminal C of the oscillator 12 for back-bias generating clock and a depletion type MOS transistor T15 whose gate is connected to a voltage clamping node B is provided in the circuit 13. The voltage clamping node B is a junction node of a depletion type MOS transistor T11 with diode connection and three steps of enhancement type MOS transistors T12-T14 with diode connections and the other end of T11 is connected to the source voltage (VCC) and the other end of T14 is connected to GND.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] This is a substrate back bias generation circuit that clamps the power supply voltage of a back bias generation oscillator to suppress the depth of back bias.

[Industrial application field]

The present invention relates to substrate bias generation circuits for semiconductor integrated circuits, etc., and more particularly to improvements in substrate bias generation circuits that generate negative bias voltages.

Although recent semiconductor integrated circuits operate with only one power source (for example, 5V), semiconductor memory devices and the like may require a negative bias voltage. In such a case, it is necessary to provide a substrate bias generation circuit in the integrated circuit to generate a negative bias voltage from the +5 [V] power supply voltage.

[Conventional technology]

FIG. 3 shows an example of a conventional substrate bias generation circuit.

In FIG. 3, the oscillator 31 generates a rectangular wave, and when the output terminal Q is at a high level ("H", the output terminal Q is at a low level ("L"), and when the output terminal Q is @L", the Q is The series-connected MOS transistor Ts s T! constitutes an output buffer (drive) circuit, and the output terminal Q becomes ``H''.
When Q is 1L, T1 is ON and T is OFF, node A becomes +V.

Let us now assume that some time has passed since the power supply Vcc was turned on, and the back bias generator has already brought the substrate and node B to a slightly negative voltage.

/-)”A: OV, /-toB:-IV
, Substrate: -0.5V.

At this time, when node A becomes +5V, the voltage at node B increases by B X SV due to the coupling of capacitance CB.

CB+C capacity of node B) Generally, this capacity ratio is about 0.7 to 0.8, so in this case, the voltage of node B rises to about +3.7V.

Then, Ts turns ON and the charge on node B escapes to the ground, so after a short time (zloonII), node B reaches a voltage approximately equal to the threshold value Vth of Ts (:
O, SV).

Then, when the output terminal Q becomes @L" and the output terminal Q becomes 1H", the transistor Ts turns OFF and T becomes ON, so the node A becomes "L" level and the capacitor CB discharges. .

When node A becomes Ov, node B becomes B because of the coupling of capacitance CB. The voltage drops by B+(/-)"B.capacitance) x 5v. Therefore, node B is now 0.5V-3,7=-
It drops to about 3.2v. Then T4 is O
N so that current (Fig. 3 1) flows from the substrate to node B, and after a short time V(substrate) - V(node B)
I felt depressed at the word Vth(T<). At this time, the board is
If the node B remains in the negative voltage state, the current flowing from the substrate to the node B cannot be replenished, resulting in a negative voltage state. Since the capacitance of the substrate is large, V (substrate) hardly moves during the above operation once, but after repeated operations, V (substrate) gradually becomes more negative.

In the present example, for - times of operation, for example, the substrate knee o, s
oi V, /-do B: -1,001V, which is a little less than -0,001V) and increases in the negative direction by f.

B Ultimately, the substrate voltage decreases as V (substrate) - Mac CB + C capacitance of node B) = Vth (T4) '&.
Therefore, if the leakage current from the circuit elements formed on the substrate surface is completely bloated with no heat, the substrate voltage will be -3.5 to -4 at Vcc = 5V.
t5゜In this flexible substrate bias generation circuit, its output voltage is either the power supply voltage VCC6 or the substrate current (leakage current from the transistor element fabricated on the substrate surface to the substrate). It is easy to fluctuate due to fluctuations in etc. For this reason, the output voltage is generally stabilized by increasing the capability of the substrate bias generation circuit.

By the way, the relationship between the power supply voltage VCC and the access time of a semiconductor memory device is that the access time should be shorter and the speed should be improved when VCC is higher, but the output of the back bias generation circuit (-VIIB) stands for VCC
The threshold value (vth) of the entire transistor of the semiconductor integrated circuit connected to this increases in proportion to
increases, or the case of a depletion type transistor),! Since the current (ID58) when the near and (t- terminals are connected to the ground) becomes small, the access time becomes longer and the speed decreases, as shown in FIG. 6.

Figure 4 shows the power supply voltage (Vcc) and back bias (-VB
B) represents the relationship, and ■ is the case where no particular measures are taken, and VDB Knee 〇, 7 XVcc.

Therefore, a characteristic such as (2) is desired in which even if the power supply voltage (Vcc) is increased, the voltage does not increase beyond the value of VBB.

Therefore, conventionally, 32 diode-connected MOs shown in FIG.
S) It has been considered to provide a clamp circuit 32 consisting of a series circuit of transistors Ts and Ts (Japanese Unexamined Patent Publication No. 56
-32758). The clamp circuit 32 suppresses the back bias voltage by flowing a current from the ground side toward the substrate when the back bias voltage becomes high enough to reach a certain level. (The necessary number of transistors Ts and Ts are provided in multiple stages.) However, in this configuration, unless the current capacity of the transistors Ts and Ts of the clamp circuit 32 is made very large, the threshold value (vt
The clamp voltage cannot be determined in h), and the source and drain voltages (Vos) are affected, and as shown in Figure 4 (■), as the power supply voltage (Vcc) increases, -VBB increases, and the voltage suppression is insufficient. becomes.

[Problem that the invention seeks to solve]

Conventionally, to suppress the back bias voltage within a predetermined range,
The current capacity of the clamp circuit 32 shown in FIG.
This requires a very large channel width (for example, 1 mm)9, which occupies a large area of the integrated circuit and impedes an increase in the degree of integration. Furthermore, even if the transistor is made large enough to be clamped at the threshold value (vth), a similar phenomenon will occur due to the sub-threshold current. As a result, the magnitude of the back bias is actually determined not by the Vth of the transistor but by the VD8 when a current flows through the transistor, making it difficult to suppress the back bias to a constant value.

In addition, in conventional circuits, the back bias generator operates freely, and when it exceeds the substrate voltage (-V!IB), current is injected from the ground (GND) to neutralize it and reduce the voltage to IV, -1. Since the increase is suppressed, there is a drawback that the current consumption increases accordingly.

Furthermore, when the potential of the back bias generator output (-VBII) connected to the substrate is pushed down by the capacitor CB, the potential of the connection becomes lower than that of the substrate, and when the current is drawn, it sinks. At that time, active electrons are generated, which travel far through the board and enter the p,@H" level integrated circuit parts (SRAM flip-flop nodes, etc.), potentially causing malfunction. Regarding this point, in the conventional back bias circuit in which -VBB increases as VCC increases as described above, the voltage difference between the back bias connection of the substrate and the substrate is large (-VB
Because B is large, the voltage range that can be lowered is large)
However, the disadvantage is that the large number of active electrons may have an adverse effect on operation.

[Means for solving problems]

In the present invention, as shown in FIG. 1, the current voltage (V('C)) of the oscillator bulb of the back bias clock is clamped to keep the clock amplitude constant.

[Effect]

The clamping of the back bias clock amplitude can be suppressed to a constant value by clamping the power supply voltage, and as a result, the back bias VBB is clamped. As a result, the speed of the integrated circuit can be increased even in areas where the power supply voltage (Vcc) is high.

Furthermore, the present invention can reduce current consumption compared to the conventional case where current is flowed into the substrate from GND to neutralize the substrate potential and suppress an increase in 1Vnnl.

Furthermore, since the clock amplitude itself is suppressed to suppress the generation of active electrons at the substrate connection portion of the back bias, IV-1 can be reduced to a minimum, and the adverse effect on the operation of the integrated circuit is reduced.

[Embodiment] In Fig. 1, numeral 11 is a back bias generation circuit, numeral 11 is a back bias generation clock oscillator, and its power supply voltage VDC is clamped by a power supply voltage clamp circuit. . A back bias (-VBB) is applied to the semiconductor substrate via the substrate electrode 14.

The back bias generating circuit 11 itself is the same as that described above with reference to FIG. 3, and the symbols are also the same.

The power supply voltage clamp circuit 13 has one end connected to the power supply voltage (V
cc), the other end is connected to the power supply terminal C of the oscillator ν of the back bias generation clock, and the gate is connected to the voltage clamp node B.
It has a transistor Tts. The voltage clamp node B is the connection node between the diode-connected depletion resistor WMO8) Tit and the diode-connected three-stage enhancement type MO8) run raster T1 * Tts * T14, and the other end of Tst is the power supply voltage (Vcc).
Furthermore, the other end of T14 is connected to GND.

Here, the voltage at node B is the transistor T1r*71s
+ Let it be determined by the threshold value (vth) of T14. For this purpose, a depletion type MOS transistor Ttt
The channel width of the enhancement type MO8 is reduced, while the enhancement type MO8
) Langister Tl! ~T14 may be increased to increase the size ratio between the two. In addition, if the current that flows is small (for example, on the μA order),
11MO8) Transistors T13 to Tsa (The voltage at node B is determined by the sum of D thresholds (Vth).

This clamped node B voltage clamps the terminal voltage vdc of the depletion type transistor T1s, thereby suppressing the clock amplitude for back bias generation (Fig. 5), and eventually suppressing the depth of the back bias. (Figure 4 ■).

For example, the power supply voltage (V('
If C) is suppressed by 4VK, MBB knee 0.7 x 4 =
It becomes -2.8V.

FIG. 2 shows an overall circuit diagram of the embodiment.

The clock oscillator for back bias generation is a depletion type MO8) transistor Qi, Q4-Qt, and an enhancement transistor WMO8) transistor QIQl#Q.
It is a ring oscillator consisting of a three-stage inverter consisting of s, an MO8 resistor consisting of depletion type MO8) transistors Qs, Qs, Qs, and a CR coupling consisting of MO8 capacitors C1, Cm, Cm, and its oscillation waveform is Transistors Q1o-Qts that shape and output
It is equipped with an output circuit. In this embodiment, as shown in FIG. 2, the transistor Q14* of the output driver of the oscillator
Although the power supply V6c of the Qts stage is clamped by the vcc clamp circuit 13, the power supply voltages of transistors in other stages may also be clamped.

Further, T'g in FIG. 1 may be of an enhancement type instead of a depression type.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the following effects can be obtained.

■ By clamping the power supply voltage of the back bias clock generation circuit, the depth of the back bias can be suppressed to a nearly constant value, making it possible to increase the speed and stability of integrated circuits.

■ Current consumption can be lower than that of conventional back bias generation circuits.

■ The generation of active electrons generated in the back-biased substrate supply section can be reduced, reducing the negative effect on integrated circuit operation.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a main part of an embodiment of the present invention, Fig. 2 is an overall circuit diagram of an embodiment of the present invention, Fig. 3 is a circuit diagram of a conventional example, and Fig. 4 shows VCC and back bias (-YelB ), Figure 5 is a diagram showing the relationship between Vcc and clock amplitude, and Figure 6 is a diagram showing the relationship between Vcc and clock amplitude.
A diagram showing cc and access time of a semiconductor memory device. FIG. 7 is a circuit diagram of a conventional example of a back bias suppression circuit. Main code 11...Back bias generation circuit ν...Clock excavator for back bias generation 13.
...Power supply voltage clamp circuit 14...Substrate electrode 15...Semiconductor substrate

Claims (1)

[Claims] It consists of an oscillator that generates a periodic signal of one polarity, an output buffer circuit of the oscillator, and a bias circuit that is connected to the output buffer circuit and outputs a bias voltage of the other polarity, the output buffer of the oscillator A substrate bias generation circuit characterized in that a voltage clamp circuit is connected to a power supply voltage terminal of one polarity of the circuit.