JPS61273777A - Data demodulation system - Google Patents

Abstract

PURPOSE:To demodulate various code data by generating pulses for reproduction which synchronize with reference pulses, demodulating code data into playback data by reconversion by using the pulses for reproduction, and comparing the pulses for reproduction with the reference pulses and deciding whether or not they shift in frequency from each other. CONSTITUTION:A control circuit 15 judges a track range which includes a target block number and clock speed information, performs arithmetic operation according to data within the track range to calculate the track number and starting sector of the target block from the arithmetic result, and outputs clock speed information to a programmable synthesizer 23. The programmable synthesizer 23 generates reference pulses of time width corresponding to the clock speed information supplied from the control circuit 15 and supplies them to a converting circuit 20 and a demodulation part 14. The readout signal of an optical head 12 is supplied to a binary coding circuit 13, whose binary-coded signal is supplied to a demodulation part 14, which outputs demodulated playback data to the control circuit 15. Consequently, various code data of different frequency are demodulated into invariably accurate playback data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a data demodulation method used, for example, in an optical disk device that records or reproduces data on an optical disk.

[Technical background of the invention]

In recent years, image information such as documents that are generated in large quantities is photoelectrically converted by two-dimensional optical scanning, and the image information that has been electrically converted is recorded on an image recording device, or it can be searched and reproduced as necessary. Optical disk devices have recently been used as image recording devices in image information file devices that can be reproduced and output as node copies or soft copies.

Conventionally, such an optical disk device I/C has a
An optical disk is used that stores data in a 9-wire format.
Data is recorded or reproduced by an optical head that is moved linearly in the radial direction of the optical disk by a linear motor.

In the above-mentioned optical disk, code data obtained by modulating the recorded data according to 2-7 code conversion is recorded in order to record data at high density, and this recorded code data t-
The trap is such that the data demodulated according to the 2-7 code inverse conversion is reproduced.

[Problems with background technology]

However, in the above-mentioned optical disk device, when demodulating code data read from an optical disk by inverse conversion of a 2-7 conversion code, the process is as shown in FIG. That is, in the initial stage, instead of the code data, a reference pulse which is almost synchronized with the code data is accepted by an oscillator (not shown), and this received reference pulse is used for reproduction as a signal synchronized with the mother pulse and is used in a phase comparator circuit. 51,
The phase/voltage conversion circuit 52, the filter 53, and the voltage controlled oscillation circuit 54 are used to generate the pulse as shown in FIG. 9(a), and this reproduction pulse is used to generate code data as shown in FIG. Inverse conversion of the 2-7 conversion code to be demodulated into playback data is performed. Thereafter, a reproduction pulse is output from the voltage controlled oscillation circuit 54 in synchronization with the read code data, and the reproduction pulse is used to convert the code data into a 2-7 conversion code in the reproduction code output circuit 55. The demodulation circuit 56 demodulates the -7 converted code into reproduced data (by inverse code conversion).

However, if noise occurs in the middle of the read code data and its frequency is greatly disturbed, the reproduction noise output in response to this will be
As shown, K had the disadvantage that it was generated at a frequency different from that of the original reproduction signal.

In this way, even if the frequencies differ, conventionally only phase comparison detection was performed, so if the phases matched, it was judged as normal processing.

For this reason, accurate demodulation may not be performed.

[Purpose of the invention]

This invention was made in view of the above circumstances, and its purpose is to prevent the reproduction Norse from deviating greatly from the original frequency, and to always accurately reproduce various code data of different frequencies. The purpose of the present invention is to provide a data demodulation method that can demodulate data.

[Summary of the invention]

This invention changes the frequency of the reference Norse according to the code data to be used, first generates a reproduction pulse synchronized with the reference pulse, and then inversely transforms the code data using this reproduction four pulses. Demodulates the reproduced data, and at the time of demodulation, matches the phase of the code de=re and the phase of the reproduction pulse, compares whether the reproduction pulse and the frequency of the reference/IP pulse are shifted, and if they are, The reproduction master pulse is synchronized with the reference pulse, and if there is no deviation, the code data is demodulated.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 4 shows an optical disk device according to the present invention. That is, the optical disc (recording medium) 1 is connected to the motor 2
It is designed to be rotationally driven by. As shown in FIG. 5 of the above-mentioned optical disc IFi, a metal coating layer such as tellurium or bismuth is coated in a donut shape on the surface of a circular substrate made of glass or plastic, for example. A notch tab reference position mark 11 is provided near the center of the layer. Further, on the optical disk 1 there is a reference position mark 1. t
-rOJ is set to be divided into 256 sectors "0 to 255".

Variable length information (image information) is stored on the optical disk 1 over a plurality of clocks.
300,000 blocks of information are now stored on 36,000 tracks on the optical disk 1. The number of sectors in one block on the optical disc 1 is, for example, 40 sectors on the inner side and 20 sectors on the outer side. In addition, if each block does not end at the sector switching position, a block gap is provided as shown in the first block and the first block shown in FIG. 5, so that each block always starts at the sector switching position. At the start position of the above-mentioned clock, a block header A consisting of a block number, track number, etc. is recorded, for example, when the optical disc 1 is manufactured.

The motor 2 is composed of a spindle motor whose rotation is controlled at a constant speed (600 rpm) by a PLL motor control circuit 17. On the shaft 3 of the motor 2,
As shown in FIG. 6, a disk 4 on which signal generation marks 4M are provided at regular intervals is fixed.
The mark 4M is optically detected by a detector 7 consisting of a light emitting diode and a light receiving element. Further, a detector 8 consisting of a light emitting diode and a light receiving element for optically detecting the reference position mark 11 is provided below the disk 1. The output of the detector 7 (the output of the light receiving element) is supplied to the clock/9 pulse input terminal of a sector counter 10 via the amplifier 9, and the reset input terminal of the sector counter 10 is supplied with the output of the detection port 8. The output of the light receiving element is supplied through the amplifier section 1.

Further, below the optical disc 1, an optical head 12 for storing and reproducing information is provided so as to be movable in the radial direction of the optical disc 1. This optical head 12 includes, for example, a semiconductor laser r oscillation s, a collimating lens,
This is a well-known device consisting of a beam splitter, a λA wavelength plate, an objective lens, a light receiver, and the like. The output of the optical head 12 is supplied to a binarization circuit 13, and the signal binarized by the binarization circuit 13 is demodulated by a demodulation section (MJ will be explained in detail later) 14 and sent to a control circuit 15. Supplied. The demodulation unit 14 demodulates the reproduced data by performing inverse conversion of the code data '12-7:1-code conversion from the binarization circuit 12 in response to clock pulses from the Progera i-Pull synthesizer 23, which will be described later. It is something to do. The control circuit 151d controls the entire reservoir in response to signals from an external device, that is, a host computer (not shown).

For example, when the control circuit 15 is supplied with a block number for recording or reproducing, it calculates the track number and start sector number to be accessed according to the conversion table stored in the storage circuit J15, and also obtains clock speed information. It is something that can be done. The memory circuit 16 has a seventh
As shown in the figure, the clock speed information of the optical disk 1 for each 256 track, the number of sectors in one block at this clock speed, and the number of the first block in the 256 tracks at the above speed correspond to the starting sector of that block. This is the one that stores the conversion table.

For example, when the control circuit 15 receives a block number rlOJ from the host computer, the block number is between 0 and 255 tracks depending on the storage contents of the memory circuit 16, and the block number of the first block in that track is "0". '', the start sector is ``00'' and the number of sectors in l block ``40'' is obtained, and the number of tracks and the number of sectors of block number ``10'' are calculated accordingly. In other words, the quotient obtained by ((target block number - first block number) x number of sectors + starting sector) ÷ 256 + track number of first block is the number of tracks, and the remainder is the number of sectors. "1", the starting sector r144J is calculated.

The control circuit 15 controls a programmable synthesizer 23, which will be described later, in accordance with the clock speed information obtained at the time of access.

Modulation is performed so that the data on the track of the optical disk 1 relative to the optical head 12 is kept at a constant linear velocity.

This allows demodulation to be performed. In addition, the control circuit 1
5 converts the track number into a scale value when the track number is calculated, and drives and controls the linear motor driver 18 until this scale value matches the position detected by the output of a position detector (not shown). It has become. This linear motor driver 18 includes a control circuit 15
The optical head 12 is moved by the Lulinear motor machine 1fllt19 under the control of , so that the beam light of the optical head 12 illuminates a predetermined track. The linear motor mechanism 19 moves the optical head 12 in the radial direction on the optical disk 1. In addition, when the optical head 12 corresponds to the target track at the time of access, when the start sector and the count value of the sector counter 10 match, the control circuit 15 causes the optical head 12 to
This is used to start recording and playback operations.

Further, the control circuit 15 modulates the recording data from the host computer into code data using 2-7 code conversion in the modulation circuit 20, and supplies the code data to the radar driver 2.

The modulation circuit 20 modulates recording data in response to a clock signal from a programmable synthesizer 23, which will be described later.

That is, the modulation circuit 20 outputs the recorded data such as "B".
rolooolooooooooo 1000J modulated with 3' data according to the 2-7 code conversion shown in Table IK below.
The encoded data (code data) is recorded.

The laser drino 421 records data by driving a semiconductor radar (not shown) within the optical head 12 in accordance with the supplied modulation signal.

There is also a 22Fi reference clock oscillator (reference/9 pulse generation section), which generates a reference clock/9 pulse. This reference clock oscillator 22 is designed to generate reference clock noculus of different frequencies depending on the selection signal from the control circuit 15. For example 1
The frequency during normal data reproduction is twice the frequency during original preformat reproduction. The signal from the reference clock oscillator 8 is supplied to a programmable synthesizer (reference/arm pulse generator) 23. The programmable synthesizer 23 uses the supplied reference clock to generate a clock pulse (reference pulse) having a time width corresponding to the clock speed information supplied from the control circuit 15. That is, as the optical head 12 moves from the inside to the outside, the time widths of clock pulses and pulses become shorter.

The clock/wavelength of the programmable synthesizer 23 can be supplied to the demodulation section 14 and the modulation circuit 20. In addition, the above programmable synthesizer 2
3 generates a reference pulse as shown in Fig. 3(a) during normal data reproduction according to the change in the frequency of the supplied reference clock, and generates a reference pulse as shown in Fig. 3(a) during original preformat reproduction.
A reference pulse as shown in a) is generated.

FIG. 1 explains the demodulating section 14. That is, the reference signal from the programmable synthesizer 23 is
A frequency dividing circuit 63 outputs a divided clock whose frequency is divided by two, for example, and the code data from the binarization circuit J3 and the divided clock from the frequency dividing circuit 63 are divided in response to a select signal from the control circuit 15. An input signal switching circuit 31 that selects and outputs the code data from the input signal switching circuit 31 (within the voltage-controlled oscillation circuit group 35 supplied via a startup signal and an oscillation circuit output signal selection circuit 39 described later) A data/reproduction/9 pulse phase comparison circuit 61 that compares the phase with the oscillation signal (pulse signal for reproduction) from the voltage controlled oscillation circuit 35a, . . . and outputs a signal according to this phase difference, the programmable A reference pulse/regeneration/4-pulse phase comparison circuit for drawing in that compares the phase of the reference pulse from the synthesizer 23 and the edge (rising edge) of the reproduction pulse on a t-1 to 1 basis and outputs a signal according to this phase difference. 62, the data/reproduction/arm phase comparison circuit 61
The signal from and said reference/? The frequency comparison circuit 32, which will be described later,
The phase comparison output signal switching circuit 32 selects and outputs the output signal according to the switching signal from the output signal switching circuit, ? a phase/voltage conversion circuit 33 that converts the phase difference signal supplied from phase difference signal 2 into a voltage and outputs it, and a low-pass filter 34 that suppresses the voltage value of the output of this phase/voltage conversion circuit 33 to remove noise) ,? A voltage controlled oscillation circuit that outputs oscillation signals in different frequency ranges according to the voltage value from the knee low-north filter 34, respectively. A voltage controlled oscillation circuit group 35 consisting of a voltage controlled oscillation circuit group 35 consisting of 5 m, .
・An oscillation circuit output signal selection circuit 39. which outputs the output signal from 35n) as a reproduction/base pulse. The code data supplied from the input signal switching circuit 31 is converted into a predetermined bit by using the reproduction pulse outputted from the oscillation circuit output signal selection circuit 39).
: A reproduced code output circuit 38 that outputs a 2-7 converted code, performs the inverse conversion of the 2-7 code conversion on the 2-7 converted code from this reproduced code output circuit 38, and converts the data into a
a demodulation circuit 36 for performing t-operation, a tolerance range setting circuit 64 in which a setting standard/4' pulse number (tolerable value) (for example, 65 to 75 pulses) as a time width supplied from the control circuit 15 is set, and the voltage control described above. The reproduction pulse from the oscillation circuit 35 and the reference pulse from the degrammaple synthesizer 1de 23 cause the frequencies of these /4' pulses to match within the time width set by the tolerance setting circuit 64. It is comprised of a frequency comparison circuit 37 that compares whether or not the signal is present and outputs a selection signal according to the comparison result.

The voltage controlled oscillation circuit 35& outputs a reproducing pulse having a frequency as shown in FIG. 3(b) K during normal data reproducing, and outputs a reproducing pulse as shown in FIG. 3(a) during original preformat reproducing. /4'rus is output. In this case, the frequency during normal data reproduction is twice the frequency during original preformat reproduction.

FIG. 2 illustrates the frequency comparison circuit 31'f. That is, the check length counter 41 creates a check length (width to be checked) by dividing the regeneration pulse from the voltage controlled oscillation circuit 35 in multiple stages, and the check length counter 41 generates a check length (width to be checked) by dividing the regeneration pulse from the voltage controlled oscillation circuit 35 in multiple steps. A start-up detection circuit 4 detects every 7o7f of the main pulse and outputs a detection signal and an initial value setting signal when detecting the start-up.
2. The reference pulses from the programmable synthesizer 23 are counted by the initial value setting signal from the start-up detection circuit 42, and when the first initial value setting signal is supplied, the reference pulse is supplied from the tolerance setting circuit 64. If h satisfies the set standard No. 4 Lus number (55a# Lus) as a tolerance value,
A delay detection circuit 43 outputs a delay signal, and the clock pulses from the programmable synthesizer 23 are counted by the initial value setting signal from the rise detection circuit 42, and the clock pulses are counted from the programmable synthesizer 23 before the next initial value setting signal is supplied. A lead detection circuit 44 outputs a lead signal when the set standard number of pulses (75 noculus) as a permissible value supplied from the permissible range setting circuit 64 is reached, and a delay signal or a lead signal from the delay detection circuit 43. When the advance signal from the detection circuit 44 is supplied, the switching signal is transferred to the output signal switching circuit 92.
It is constituted by an exclusive OR circuit 45 which outputs an output to.

Next, the operation in such a configuration will be explained. first,
Data recording will be explained. For example, now we are recording (accessing) from a host computer (not shown).
Assume that the block number is supplied to the control circuit 15. Then, the control circuit 15 uses the conversion table in the storage circuit 16 to calculate the track, start sector, and clock speed information of the target block. That is, the control circuit 15 determines the range of the track that includes the target block number in the conversion table and the clock speed information, and calculates the value of "((target block number - first f lock)" according to the data in the track range. number) × number of sectors + starting sector] ÷ 256 +
The track number of the first block is entered, and the track number and starting sector of the target block are calculated from the result of this calculation.

As a result, the control circuit 15Fi outputs the clock speed information to the programmable synthesizer 23. Then,
The programmable synthesizer 23 uses the reference clock pulses from the reference clock oscillator 22 to generate the control circuit 15.
A reference pulse having a time width corresponding to the clock speed information supplied from the clock speed information is generated and supplied to the modulation circuit 2o and the demodulation section 14.

Further, based on the track number, the control circuit 15 converts the track number into a scale value, and the linear motor driver 18f, ltl is operated until this scale value matches the position detected by the output of a position detector (not shown). The control circuit 15 then starts recording data on the optical disc 1 when the count value of the sector counter 10 and the start sector match. The recording data from the circuit 15 is modulated by the modulation circuit 2o into a 2-7 conversion code according to the reference 71 pulses from the programmable synthesizer 23, and is supplied to the laser driver 21.
When the laser driver 21 drives a semiconductor radar (not shown) in the optical head 12 according to the supplied modulation signal of the 2-7 conversion code, the laser driver 21 records the code data.

For your convenience, code data can be recorded in other blocks in the same manner as above.

However, since the block position is located on the outer periphery, data is recorded with the clock pulse being made faster. Therefore, high-density recording is performed on the optical disk 1 in the same way as if code data were recorded at a constant linear velocity.

Next, the process of reproducing data will be explained. first.

A block number to be reproduced (accessed) is supplied to the control circuit 15 from a host computer (not shown). Then, the control circuit 15 uses the conversion table in the storage circuit 16 to calculate the track, start sector, and clock speed information of the target block. That is, the control circuit 15 determines the range of the track including the target block number in the conversion table and the clock speed information, and calculates "((target block number - first block number)" according to the data in the track range. ) x tens of sectors starting sector) ÷ 256
+first block track number" is calculated, and the track number and start sector of the target block are calculated from the result of this calculation. Accordingly, the control circuit 15 outputs the clock speed information to the programmable synthesizer 23. Then, the programmable synthesizer 23 uses the reference clock pulse from the reference clock oscillator 22 to generate a reference pulse having a time width as shown in FIG. 3(b) according to the clock speed information supplied from the control circuit 15. The signal is generated and supplied to the conversion circuit 20 and the demodulation section 14.

Further, based on the track number, the control circuit 15Id converts the track number into a scale value, and starts the linear motor driver 18 until this scale value matches the position detected by the output of a position detector (not shown). The optical head 12 is moved. Next, the control circuit 15 starts reproducing data on the optical disc 1 when the count value of the sector counter 10 and the start sector match. At this time, the read signal from the optical head I2 is supplied to the binarization circuit 13, and the signal binarized by the binarization circuit 13 is supplied to the demodulation section 14. This demodulator 1
4 demodulates the signal ``!'' code data from the binarization circuit 13 by inverse conversion of 2-7 code conversion according to the reference pulse from the programmable synthesizer 23, and sends this demodulated playback data to the control circuit. Output to 15.

That is, if the frequencies of the reference 4 Lus and the reproducing 4 Lus initially differ beyond the allowable range, a switching signal from the frequency comparison circuit 37 causes the phase comparison output signal switching circuit 32 to select the pull-in reference 4 Lus. The result of the pulse/reproduction/IP pulse phase comparator circuit 62 is outputted.
Reference) 4 pulse/regeneration/f pulse phase comparison circuit 62 calculates the phase difference between the reference pulse from the programmable synthesizer 23 and the output signal from the voltage controlled oscillation circuit 35m supplied via the oscillation circuit output signal selection circuit 39. The corresponding signal is sent to the phase/phase signal via the phase comparison output signal switching circuit 32t.
It is output to the voltage conversion circuit 33. As a result, the phase/voltage conversion circuit 33 outputs a voltage corresponding to the phase difference to the voltage controlled oscillation circuit 351 via the low-north filter 34. Then, the voltage controlled oscillation circuit 35 & generates a signal with an oscillation frequency corresponding to the voltage value as shown in FIG. 3(b).
Outputs a regeneration pulse synchronized with 9 pulses.

Then, the frequency comparison circuit 37 converts the voltage controlled oscillation circuit 35a.
The frequency of the reproduction mother pulse from the permissible range setting circuit 6
When the frequency falls within the permissible range of the base 5 single frequency set by 4, a switching signal is output to the phase comparison output signal switching circuit 32. Then, the phase comparison output signal switching circuit 32 outputs the phase difference signal from the data/reproduction/4 pulse phase comparison circuit 6 to the phase/voltage conversion circuit 33.

As a result, the phase/voltage conversion circuit 33 outputs a voltage according to the phase difference to the voltage controlled oscillation circuit 35a via the loaf 4 filter 34. Then, the voltage controlled oscillation circuit 35& outputs a signal with an oscillation frequency corresponding to the voltage value, that is, a reproduction pulse synchronized with the reference pulse.

In this state, the input signal switching circuit 31 outputs the code data from the binarization circuit 13 to the reproduced code output circuit 38. Then, the reproduction code output circuit 38 uses the reproduction pulse from the voltage controlled oscillation circuit 35 to output the code data to the demodulation circuit 36 for each predetermined bit as a 02-7 conversion code. As a result, the demodulation circuit 36 demodulates the supplied 2-7 conversion code by inversely converting the 2-7 code conversion, and transfers the demodulated playback data to the control circuit 11.
Output to 5.

At this time, the code data from the input signal switching circuit 31 is supplied to the data/reproduction pulse phase comparison circuit 61. As a result, the data reproduction Norse phase comparator circuit 61 compares the phases of the code data and the reproduction pulse.
Start output from 5h. In addition, the voltage controlled oscillation circuit 35a
For playback from ・Medium Luz and Programmable Synthesizer 2
A frequency comparison circuit 37 compares whether the frequency matches that of the reference pulse from No. 3.

That is, the regeneration pulse is frequency-divided by a check counter of 4, and an initial value setting signal is output from the start-up detection circuit 42 to the delay detection circuit 43 and advance detection circuit 44 every 70 noculus of the regeneration Noculus. Ru. As a result, the delay detection circuit 43 performs the following until the next initial value setting signal is supplied.
The reference/4 pulses from the programmable synthesizer 23 are counted, and the count value between them is set as the allowable range setting circuit 6.
Setting standard NoJ supplied from 4? If the number of pulses is less than 65, it is detected that the frequencies are different, and the detection signal is supplied to the exclusive OR circuit 45, thereby outputting a switching signal from the exclusive OR circuit 45. Further, the advance detection circuit 44 counts clock noculus until the next initial value setting signal is supplied, and the count value is determined as the setting standard a4 pulse number "75" supplied from the tolerance range setting circuit 64.
In the above case, by detecting that the frequencies are different and supplying the detection signal to the exclusive OR circuit 45), the exclusive OR circuit 45 outputs a switching signal.

When this switching signal is supplied to the phase comparison output signal switching circuit 321C, the phase comparison output signal switching circuit 32 again outputs the result of the pull-in reference/pulse/regeneration/pulse phase comparison circuit 62. As a result, the standard 9 rus/
The reproduced pulse phase comparison circuit 62Fi sends a signal corresponding to the phase difference between the reference pulse from the programmable synthesizer 23 and the output signal from the voltage controlled oscillation circuit 35 to the phase/voltage conversion circuit 33 via the phase comparison output signal switching circuit 32. Output. As a result, the phase/voltage conversion circuit 33 converts the voltage according to the phase difference to low t! It is output to the voltage controlled oscillation circuit 35 via the filter 34. Then, the voltage controlled oscillator circuit 35 outputs a signal with a missing frequency corresponding to the voltage value, and outputs nine pulses for reproduction that are synchronized with the reference pulse.

The playback data demodulated as above is controlled by the control circuit 15V.
c, the data is transferred to a host computer (not shown).

Furthermore, when reproducing data of other blocks, it can be performed in the same manner as described above. In this case, as the block to be reproduced moves toward the outer periphery, the data is reproduced while the reference Norse is made faster. Therefore, data on the optical disc 1 is reproduced at high speed.

Furthermore, when reproducing the original preformat, the frequency of the reference clock output from the reference clock oscillator 22 from the control section 15 is changed to W times that of normal data reproduction. As a result, the reference pulse becomes K as shown in FIG. 3(a). Further, in response to an oscillation circuit selection signal from the control section 15, the oscillation circuit output signal selection circuit 39 outputs the output signal of the voltage controlled oscillation circuit 35o for reproduction. As shown in FIG. 3(a), this reproduction pulse has a frequency that is multiplied during normal data reproduction. Therefore, using the reference signal and the reproduction pulse, the operation is performed in the same manner as in the case of normal data reproduction.

In addition, when it is known that code data will not be input, or when recording data on the optical disc 1, the control circuit 1
A select signal is supplied from 5 to the input signal switching circuit 3. As a result, the input signal switching circuit 31 is switched to the frequency dividing circuit 63.
Outputs the reference/pulse frequency-divided clock supplied from

As a result, the reproduction pulse can be made equal to the reference pulse. As a result, when recording data, the reproduction pulse can be treated as a recording pulse (reference pulse) as it is, and when the code data is not input from the control circuit 15, it can be switched to the reference Noyals divided clock.
It is possible to avoid a large shift in frequency in advance.

The signal waveform diagram of the main parts in the above operation is shown in Figure 3 (a).
) As shown in (b).

As mentioned above, the frequency of the reproduction pulse and the reference pulse are almost the same, and the reproduction pulse and the reference pulse are synchronized, which improves the reliability of the reproduction pulse by a simple means. Therefore, various code data having different frequencies can always be accurately demodulated into reproduced data.

Furthermore, there is no need to have an external highly accurate mechanism for detecting frequency deviations, which can be processed using internal circuitry.

Furthermore, accurate demodulation processing can be performed without the intervention of a control system, and recovery can be performed in a short time in the event of an abnormality in reproduction or pulses.

In addition, since the value of the tolerance setting circuit can be changed by setting from an external control circuit, the time width or margin for comparison can be changed based on the judgment of the control circuit.
For example, margin according to 2-7 code, or MF
Comparisons can be made with margins depending on the M code. In this way, when the comparison time width is shortened, the overall comparison time can be shortened. Furthermore, it is possible to provide versatility, such as by increasing the comparison time width during data reading, resulting in better stability. Furthermore, the entire modulation group can be converted to 'fcLsI', and a special code can be used as a function, or when recording,
It is possible to provide versatility such as being able to perform comparisons in various time widths depending on the time of playback.

Furthermore, it is possible to supply highly reliable pulses for reproduction of any code data, even if it is a data format that requires a frequency change in the middle.

[Effect of release]

As described in detail above, according to the present invention, it is possible to prevent the reproduced noise signal from deviating greatly from the reference frequency, and it is possible to always accurately demodulate various code-r-data having different frequencies into reproduced data. Demodulation methods can be provided.

[Brief explanation of the drawing]

The drawings are for explaining one embodiment of the present invention, and FIG. 1 is a block diagram schematically showing the configuration of the demodulation section, FIG. 2 is a block diagram showing the configuration of the frequency comparison circuit, and FIG. Figure 4 is a schematic configuration diagram of the optical disk device, Figure 5 is a plan view showing the configuration of the optical disk, and Figure 6 is a diagram showing the relationship between the disc and the detector. FIG. 7 is a perspective view for explanation, FIG. 7 is a diagram showing an example of storage of a conversion table, FIG. 8 is a block diagram schematically showing the configuration of a conventional demodulation section, and FIG. 9 is a diagram showing the main points in FIG. FIG. DESCRIPTION OF SYMBOLS 1... Optical disk (recording medium integrated), 12... Optical head, 13... Binarization circuit, 14-... Demodulator, 15
. . . Control circuit, 22 . . . Reference clock oscillator (reference pulse generation W5′), 23 . - Phase comparison circuit, 33... Phase/voltage conversion circuit, 34-... Loaf 4 filter, 35...
Voltage controlled oscillation circuit group, 35-35n... Voltage controlled oscillation circuit, 36... Demodulation circuit, 37-... Frequency comparison circuit, 38... Reproduction code output circuit, 39... Oscillation circuit output Signal selection circuit, 41--check length counter, 42--rise detection circuit, 43--delay detection circuit, 44--advance detection circuit, 45--exclusive OR circuit, 61-- ...Data/reproduction pulse phase comparison circuit, 62...Reference pulse/regeneration/4 pulse phase comparison circuit,
6 B-... Frequency divider circuit, 64-... Tolerance range setting circuit. Applicant's Representative Patent Attorney Takehiko Suzue 44th Case 1 Sada Les No. 311(a) (Includes) Re 5 Izurus (Lμ) Figure 3 (b) Figure 4 Figure 5 Figure 7 Figure 8 Section

Claims (3)

[Claims] (1) In a device that code-converts code data read from a recording medium and demodulates it into reproduced data using a reproduction pulse generated based on a reference pulse supplied from a reference pulse generator, the reference pulse means for changing the frequency, output means for switching and outputting the reference pulse or code data obtained by this means, means for generating a reproduction pulse in synchronization with the reference pulse supplied by this output means, and this means demodulation means for code-converting the code data supplied by the output means and demodulating it into reproduction data in response to a reproduction pulse; means for adjusting the phase of the reproducing pulse to the phase of the data; and comparing the frequencies of the reproducing pulse and the reference pulse to see if they are misaligned, and if they are misaligned, the output means outputs a reference pulse so that the frequency is not misaligned. 1. A data demodulation method characterized by comprising: means for causing an output means to output code data. (2) The data demodulation method according to claim 1, wherein the means for generating the reproduction pulse includes a plurality of independent voltage controlled oscillators each having a specific frequency range. (3) The data demodulation method according to claim 2, wherein the plurality of voltage controlled oscillators are switched in response to a change in the frequency of the reference pulse.