JPS61273778A - Data demodulation system - Google Patents

Abstract

PURPOSE:To demodulate code data into playback data accurately by varying the frequency range of pulses for reproduction which synchronize with reference pulses according with the variation of the reference pulses, putting the code data in phase with the pulses for reproduction, and comparing the pulses for reproduction with the reference pulses and deciding whether or not they shift in frequency from each other. CONSTITUTION:A control circuit 15 judges a track range which includes a target block number and clock speed information, performs arithmetic operation according to data within the track range, and calculates the track number and start sector of the target block on the basis of the arithmetic result. A programmable synthesizer 23 generates the reference pulses of time width corresponding to the block speed information supplied from the control circuit 15 and supplies them to a converting circuit 20 and a demodulation part 14. A playback code output circuit 38 outputs the code data to a demodulating circuit 35 by using the pulses for reproduction from a voltage-controlled oscillation circuit 35 and the demodulating circuit 36 demodulates the converted code by reconversion and outputs the demodulated playback data to the control circuit 15. Consequently, the code data are demodulated into invariably accurate playback data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a data demodulation method used, for example, in an optical disk device that records or reproduces data on an optical disk.

[Technical background of the invention]

In recent years, image information such as documents, which is generated in large quantities, is photoelectrically converted by two-dimensional optical scanning, and this photoelectrically converted image information is recorded on an image recording device, or it can be searched and reproduced as necessary. Recently, optical disk devices have been used as image recording devices in image information file devices that can reproduce and output as hard copies or soft copies.

Conventionally, such optical disk devices have used optical disks that store data in a spiral pattern, and recorded or reproduced data using an optical head that moves linearly in the radial direction of the optical disk using an amotor. It is about to be done.

In the above-mentioned optical disk, code data is recorded by modulating the recorded data according to 2-7 code conversion in order to record data at high density.
The data demodulated according to -7 code inverse conversion is reproduced.

[Problems with background technology]

However, in the above-mentioned optical disk device, when demodulating code data read from an optical disk by inverse conversion of a 2-7 conversion code, the process is as shown in FIG. That is, initially, instead of the code data, an oscillator (not shown) accepts a reference pulse that is almost synchronized with the code data, and a reproduction pulse as a signal synchronized with the accepted reference pulse is sent to the phase comparison circuit 51 and the phase/f pulse. The voltage conversion circuit 52, the filter 53, and the voltage control rooting circuit 54 are used to generate the code booter reproduction data as shown in FIG. The 2-7 conversion code to be demodulated is inversely converted.Thereafter, a regeneration pulse is output from the voltage control rooting circuit '54 in synchronization with the read code data, and this regeneration pulse converts the code data into the regenerated code. The output circuit 55 converts it into a 2-7 converted code, and the demodulation circuit 56 demodulates the 2-7 converted code into reproduced data by inverse code conversion.

However, if noise occurs in the middle of the read code data and its frequency is greatly disturbed, the reproduction pulse output in response to this will be different from the original one, as shown in Figures 9(c) and (d). There was a drawback that the pulse was generated at a frequency different from that of the reproduction pulse.

In this way, even if the frequencies were different, conventionally only phase comparison detection was performed, so if the layers matched in phase, it was judged as normal processing.

For this reason, accurate demodulation may not be performed.

[Purpose of the invention]

This invention was made in view of the above circumstances, and its purpose is to prevent the reproduction pulse from deviating significantly from its original frequency, and to always accurately demodulate various code data with different frequencies into reproduction data. The objective is to provide data and demodulation methods that can be used to

[Summary of the invention]

This invention changes the frequency of the reference pulse according to the code data to be used, and first changes the reproduction sound pulse that is synchronized with the reference pulse in its entire frequency range in accordance with the change in the reference pulse. This frequency has been modified for playback.
- Inversely transform the code data using a pulse generator and demodulate it into playback data, and during this demodulation, match the phase of the code data and the phase of the playback pulse, and check whether the frequencies of the playback pulse and the reference pulse are out of sync. If there is a deviation, the reproduction pulse is synchronized with the reference pulse, and if there is no deviation, the code data is demodulated.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 4 shows an optical disk device according to the present invention. That is, the optical disc (recording medium) 1 is connected to the motor 2
It is designed to be rotationally driven by. As shown in FIG. 5, the optical disc 1 has a donut-shaped metal coating layer such as tellurium or bismuth coated on the surface of a circular substrate made of glass or plastic, for example. A reference position mark 11 is provided in the vicinity of the center of the optical disk.
It is divided into 256 sectors "0 to 255" as rOJ.

On the optical disk 1, variable length information (image information) is stored over a plurality of blocks,
300,000 blocks of information are stored on 36,000 tracks on the optical disk 1. The number of sectors in one block on the optical disc 1 is, for example, 40 sectors on the inner side and 20 sectors on the outer side. In addition, if each block does not end at the sector switching position, a block gap is provided as shown in the first block and the first block shown in FIG. 5, so that each block always starts at the sector switching position. ing.

A block header A consisting of a block number, track number, etc. is recorded at the start position of the block, for example, when the optical disc 1 is manufactured.

Above motor 2 i! : It is composed of a male spindle motor whose rotation is controlled at a constant speed (600 rpm) by a PLL motor control circuit 17. Shaft 3 of the above motor 2
As shown in FIG. 6, a disk 4 on which signal generation marks 4M are provided at regular intervals is fixed, and a detector consisting of marks 4M1 on this disk 4 and a light-emitting diode and a light receiving element is fixed to the disk 4. 1, optical detection is performed. Further, a detector 8 consisting of a light emitting diode and a light receiving element for optically detecting the reference position mark 11 is provided below the disk 1. The output of the output light-receiving element of the detector 7 is supplied to the clock pulse input terminal of a sector counter 10 via the amplifier 9, and the reset input terminal of the sector counter 10 is connected to the output light-receiving element of the detector 8. The output of the element is supplied via the amplifier section 11.

Further, below the optical disc 1, an optical head 12 for storing and reproducing information is provided so as to be movable in the radial direction of the optical disc 1. This optical head I2 includes, for example, a semiconductor laser f emitter, a collimating lens,
It is a well-known device consisting of a beam f-litter, a λA wavelength plate, an objective lens, a light receiver, and the like. The output of the optical head 12 is supplied to a binarization circuit 13.
The signal binarized by the digitization circuit 13 is demodulated by a demodulation section (described in detail later) 14 and supplied to the control circuit 15. The demodulation unit 14 demodulates the reproduced data by performing inverse 2-7 code conversion on the code data from the binarization circuit 13 in response to clock pulses from the programmable synthesizer 23 (described later). It is something to do. The control circuit 15 controls the entire apparatus in response to signals from an external device, that is, a host computer (not shown).

For example, when the control circuit 15 is supplied with a block number for recording or reproducing, it calculates the track number and start sector number to be accessed according to the conversion table stored in the storage circuit 16, and also obtains clock speed information. It is something that can be done. As shown in FIG. 7, the storage circuit 16 stores clock speed information of the optical disk 1 for each 256 tracks, the number of sectors in one block at this clock speed, and the number of the first block within the 256 tracks at the above speed. A conversion table that corresponds to the starting sector of the block is stored. For example, when the control circuit 15 is supplied with block number "10" from the host computer, the block number is between 0 and 255 tracks depending on the storage contents of the memory circuit 16, and the block number of the first block in that track is When the starting sector is "0" and the starting sector is "OO", the number of sectors in one block is "40", and the number of tracks and the number of sectors in the block number "10" are calculated and output accordingly. In other words, the quotient obtained by ((target block number - first block number) x number of sectors + starting sector) ÷ 256 + track number of first block is the number of tracks, and the remainder is the number of sectors. "1", the starting sector r144J is calculated.

The control circuit 15 modulates the data on the track of the optical disk 1 with respect to the optical head 12 at a constant linear velocity by controlling a programmable synthesizer 23't- to be described later according to the clock speed information obtained at the time of access. , which allows demodulation to be performed. Furthermore, when the control circuit 15 calculates the track number,
The track number is converted into a scale value, and the linear motor driver 18 is driven and controlled until this scale value matches the position detected by the output of a position detector (not shown). This linear motor driver 18
The optical head 12 is moved by a linear motor mechanism 19 under the control of a control circuit 15, so that a beam of light from the optical head 12 illuminates a predetermined track.

The linear motor mechanism 19 moves the optical head 12 in the radial direction on the optical disk 1. Furthermore, when the optical head 12 corresponds to the target track at the time of the above-mentioned access, the control circuit xsli causes the optical head 12 to start recording and reproducing operations when the start sector and the count value of the sector counter 10 match. be.

Further, the control circuit 15 modulates the recording data from the host computer into code data using 2-7 code conversion in the modulation circuit 20, and supplies the code data to the radar driver 21.

The modulation circuit 20 modulates recording data in response to clock pulses from a programmable synthesizer 23, which will be described later.

That is, the modulation circuit 20 outputs the recorded data, for example @8.
roio which modulated the 3''' data according to the 2-7 code conversion shown in Table 1 below.

100000000 1000J encoded data (
code data) are recorded.

The radar driver 21 drives a semiconductor laser (not shown) in the optical head 12 in accordance with the supplied modulation signal and records data.

In addition, 22 is a reference clock oscillator (reference pulse generation section)
Yes, this is what generates the reference clock pulse. This reference clock oscillator 22 generates a reference clock of different frequencies according to a selection signal from the control circuit 15.
It is designed to generate IP ruses. For example, the frequency during normal data reproduction is twice the frequency during original preformat reproduction. The signal from the reference clock oscillator 8 is generated by a programmable synthesizer (reference A4).
(23). The programmable synthesizer 23 uses the supplied reference clock to generate a clock pulse (reference nors) having a time width corresponding to the clock speed information supplied from the control circuit 15. That is, the time width of the clock pulse becomes shorter as the optical head 12 moves from the inside to the outside.

The clock signal of the programmable synthesizer 23 is supplied to the demodulation section 14 and the modulation circuit 20.
It has become. In addition, the above programmable synthesizer 2
3 generates a reference signal as shown in FIG. 3(b) during normal data reproduction according to a change in the frequency of the supplied reference clock, and generates a third reference signal during original preformat reproduction.
It is designed to generate a reference signal as shown in the figure (&).

FIG. 1 explains the demodulating section 14. That is, a frequency dividing circuit 63 outputs a divided clock obtained by dividing the reference pulse from the programmable synthesizer 23, for example, by 2, and the code data from the binarization circuit 13 and the divided clock from the frequency dividing circuit 63 are controlled as described above. circuit 1
An input signal switching circuit 31 that selects and outputs according to a select signal from 5, the edge (rise) of code data from this input signal switching circuit 31, and various code data from a voltage controlled oscillation circuit 35 to be described later. a data/reproduction signal phase comparison circuit 61 that compares the phase with an oscillation signal (pulse signal for reproduction) in a frequency range corresponding to the frequency range and outputs a signal according to the phase difference; and the programmable synthesizer 23.
A drawing-in reference pulse/reproduction pulse phase comparison circuit 62 compares the phase of the reference pulse from the reference pulse and the edge (rising edge) of the reproduction Noculus on a t-1 to 1 basis and outputs a signal according to this phase difference. , a signal from the data/reproduction/master pulse phase comparison circuit 61 and a signal from the reference pulse/reproduction pulse phase comparison circuit 62 are connected to a frequency comparison circuit 3 which will be described later.
a phase comparison output signal switching circuit 32 that selects and outputs the signal according to the switching signal from the output signal switching circuit 32; and a phase/voltage conversion circuit 33 that converts and outputs the voltage according to the phase difference signal supplied from the output signal switching circuit 32.
, a low/gas filter 34 that suppresses the voltage value of the output of this phase/voltage conversion circuit 33 and removes noise, and outputs oscillation signals in various frequency ranges according to the voltage value from this low/gas filter 34. A voltage controlled oscillation circuit 35, a frequency range switching circuit 39 that switches the frequency range of the voltage controlled oscillation circuit 35 in accordance with a frequency range switching signal from the control circuit 15, and the voltage controlled oscillation circuit 35.
A reproduced code output circuit 38 outputs the code data supplied from the input signal switching circuit 31 as a 2-7 conversion code for each predetermined pit using the output signal pulse of the input signal switching circuit 31, and this reproduced code. A demodulation circuit 36 performs inverse 2-7 code conversion on the 2-7 conversion code from the output circuit 38 and demodulates the data; ) (for example, 65 to 75 pulses), the reproduction pulse from the voltage controlled oscillation circuit 35, and the reference/4 pulse from the programmable synthesizer 23, The voltage controlled oscillation circuit 35 is configured by a frequency comparison circuit 37 that compares whether or not the frequencies match within the time width set by the allowable range setting circuit 64 and outputs a selection signal according to the comparison result. is frequency range switching circuit 3
9, the frequency range is switched according to the frequency range shown in Figure 3 (b) for normal data reproduction, and a frequency reproduction pulse is output as shown in Figure 3 (a) during original preformat reproduction. It is designed to output a pulse for reproduction. In this case, the frequency during normal data reproduction is twice the frequency during original preformat reproduction.

FIG. 2 explains the frequency comparison circuit 37. That is, a check length counter 41 that creates a check length (check @) by dividing the regeneration signal from the voltage controlled oscillation circuit 35 in multiple stages, and a check length counter 41 that generates a check length (check@) by dividing the regeneration signal from the voltage controlled oscillation circuit 35 in multiple stages, 70 of pulse
A start-up detection circuit 42 detects each pulse and outputs an initial value setting signal as a detection signal when detecting a rise. The reference pulses from the iser 23 are counted, and when the next initial value setting signal is supplied, if it is less than the set reference pulse number (65 pulses) as an allowable value supplied from the tolerance range setting circuit 64, A delay detection circuit 43 that outputs a delay signal counts the clock a4 pulses from the programmable synthesizer 23 according to the initial value setting signal from the rise detection circuit 42, and detects an allowable pulse before the next initial value setting signal is supplied. An advance detection circuit 44 that outputs an advance signal when the set reference pulse number (75 pulses) as an allowable value supplied from the range setting circuit 64 is reached. and an exclusive OR circuit 45 which outputs a switching signal to the output signal switching circuit 32 when a delay signal from the delay detection circuit 43 or a lead signal from the lead detection circuit 44 is supplied.

Next, the operation in such a configuration will be explained. first,
Let's explain in detail how to record data. For example, now we are recording (accessing) from a host computer (not shown).
Assume that the block number is supplied to the control circuit 15. Then, the control circuit 15 uses the conversion table in the storage circuit 16 to calculate the track, start sector, and clock speed information of the target block. That is, the control circuit 15 determines the range of the track including the target block number in the conversion table and the clock speed information, and calculates "((target block number - first block number)" according to the data in the track range. )X number of sectors + starting sector) ÷256+
The track number of the first block is calculated, and the track number and starting sector of the target block are calculated from the result of this calculation.

Thereby, the control circuit 15 outputs the clock speed information to the programmable synthesizer 23. Then, the programmable synthesizer 23 uses the reference clock oscillator 2.
Using the reference clock pulse from 2, a reference pulse having a time width corresponding to the clock speed information supplied from the control circuit 15 is generated and supplied to the modulation circuit 20 and the demodulation section 14.

Also, based on the track number, the control circuit 15 converts the track number into a scale value.

The linear motor driver 1 is operated until this scale value matches the position detected by the output of a position detector (not shown).
By driving 8t, the optical head 12f is moved. Next, the control circuit 15ilt sector counter 1
When the count value of 0 and the start sector match, recording of data on the optical disc 1 is started. At this time,
The recording data from the control circuit 15 is modulated by a modulation circuit 20 into a 2-7 conversion according to the reference pulse from the programmable synthesizer 23, and is supplied to the laser driver 21. As a result, the laser driver 21 spreads the modulation signal of the supplied 2-7 conversion code to the optical head 1.
Code data is recorded by driving a semiconductor radar (not shown) in 2.

Further, when code data is recorded in other blocks, it can be performed in the same manner as described above.

However, as the block position moves toward the outer circumference, data is recorded with faster clock pulses. Therefore, high-density recording is performed on the optical disk 1 in the same way as if code data were recorded at a constant linear velocity.

Next, data reproduction will be explained. First, playback (access) from a host computer (not shown)
The block number is supplied to control circuit 15. Then, the control circuit 15 uses the conversion table in the storage circuit 16 to calculate the track, start sector, and clock speed information of the target block. That is, the control circuit 15 determines the range of the track including the target block number in the conversion table and the clock speed information, and calculates "((target block number - first block number)" according to the data in the track range. )×number of sectors+start sector)÷256+track number of first block", and the track number and start sector of the target block are calculated from the result of this calculation. Thereby, the control circuit 15 outputs the clock speed information to the programmable synthesizer 23. Then, the programmable synthesizer 23 uses the reference clock pulse from the reference clock oscillator 22 to generate a reference pulse with a time width as shown in FIG. 3 according to the clock speed information supplied from the control circuit 15. occurs,
The signal is supplied to the conversion circuit 20 and the demodulation section 14.

Further, based on the track number, the control circuit 15 converts the track number into a scale value, and starts the linear motor driver 18 until this scale value matches the position detected by the output of a position detector (not shown). The optical head 12 is thereby moved. In addition, the control circuit 15 starts reproducing data on the optical disc 1 when the count value of the sector counter 10 and the start sector match. At this time, the read signal of the optical head 12 is supplied to the binarization circuit 13, and the signal binarized by the binarization circuit 13 is supplied to the demodulation section 14. This demodulator 1
4 demodulates the signal or code data from the binarization circuit 13 by inverse conversion of 2-7 code conversion according to the reference 4 pulses from the programmable synthesizer 23, and sends this demodulated playback data to the control circuit 15. Output.

That is, if the frequencies of the reference pulse and the reproduction pulse initially differ beyond the allowable range, the frequency comparison circuit 37
The phase comparison output signal switching circuit 32
outputs the result of the pull-in reference pulse/reproduction pulse phase comparison circuit 62. Thereby, the reference I4 pulse/reproduction pulse 4' phase comparison circuit 62 outputs a signal corresponding to the phase difference between the reference pulse from the programmable synthesizer 23 and the output signal from the voltage controlled oscillation circuit 35 to the phase comparison output signal switching circuit. 32 to the phase/voltage conversion circuit 33. As a result, the phase/voltage conversion circuit 33 outputs a voltage corresponding to the phase difference via the loaf 4 filter 34 as a voltage control excavation circuit: 45I/c. Then, the voltage controlled oscillator circuit 35 outputs a reproducing /JP pulse synchronized with the reference pulse as shown in FIG. 3(b), which is a signal having a rooting frequency corresponding to the voltage value.

Next, when the frequency of the reproduction pulse from the voltage controlled oscillation circuit 35 falls within the tolerance range of the reference frequency set by the tolerance range setting circuit 64 in the frequency comparison circuit 37, the phase comparison output signal switching circuit 5xFc Outputs switching signal.

Then, the phase comparison output signal switching circuit 32 outputs the phase difference signal from the data/reproduction pulse phase comparison circuit 61 to the phase/voltage conversion circuit 33. As a result, the phase/voltage conversion circuit 33 transfers the voltage according to the phase difference to the loaf 4 filter 34.
"f: is output to the voltage controlled oscillation circuit 35. Then, the voltage controlled oscillation circuit 35 outputs a signal with a rooting frequency corresponding to the voltage value, that is, a reproduction pulse synchronized with the reference 4 pulse.

In this state, the input signal switching circuit 3 outputs the code data from the binarization circuit 13 to the reproduced code output circuit 38. Then, the reproduction code output circuit 38 uses the reproduction pulse from the voltage controlled oscillation circuit 35 to output the code data to the demodulation circuit 35 as a 2-7 conversion code for each predetermined bit. As a result, the demodulation circuit 36 demodulates the supplied 2-7 conversion code by inversely converting the 2-7 code conversion, and transfers the demodulated playback data to the control circuit 11.
Output to 5.

At this time, the code data from the input signal switching circuit 31 is supplied to the data/reproduction/arm phase comparison circuit 6.
Ru. As a result, the data reproduction pulse phase comparison circuit 51 compares the phases of the code data and the reproduction pulse, and determines whether the reproduction pulse J? The pulse is outputted from the voltage controlled oscillation circuit 35. In addition, the voltage controlled oscillation circuit 3
A frequency comparison circuit 37 compares whether the frequencies of the reproduction Noculus from the programmable synthesizer 23 and the reference I# pulse from the programmable synthesizer 23 match.

That is, the frequency of the reproduction pulse is divided by the check counter 41, and an initial value setting signal is outputted from the rise detection circuit 42 to the delay detection circuit 43 and the advance detection circuit 44 every 70 pulses of the reproduction pulse. As a result, the delay detection circuit 43 counts the reference/false pulses from the programmable synthesizer 23 until the next initial value setting signal is supplied, and the count value during that time is supplied from the tolerance range setting circuit 64. Setting criteria: If the number of elbows is less than 65,
By detecting the signals having different frequencies and supplying the detection signal to the exclusive OR circuit 45, the exclusive OR circuit 45 outputs a switching signal. Further, the advance detection circuit 44 is operated by the clock/clock signal until the next initial value setting signal is supplied.
IP pulses are counted, and when the count value is equal to or greater than the setting standard/# pulse number "75" supplied from the tolerance range setting circuit 64, it is detected that one frequency is different, and the detection signal is exclusive ORed. By supplying the signal to the circuit 45, the exclusive OR circuit 45 outputs a switching signal.

When this switching signal is supplied to the phase comparison output signal switching circuit 32, the phase comparison output signal switching circuit 32 again outputs the result of the pull-in reference noyalus/reproduction-mother phase comparison circuit 62. As a result, the reference reference signal/regenerated reference signal phase comparison circuit 5214 converts a signal corresponding to the phase difference between the reference reference signal from the programmable synthesizer 23 and the output signal from the voltage controlled oscillation circuit 35 into a phase comparison output signal. Phase/voltage conversion circuit 3 via switching circuit 32ft
Output to 3. As a result, the phase/voltage conversion circuit 33 outputs a voltage according to the phase difference to the voltage controlled oscillation circuit 35 via the low-pass filter 34t. Then, the voltage controlled oscillation circuit 35 generates a signal with an oscillation frequency corresponding to the voltage value for reproduction in synchronization with the reference I pulse. Output the route.

The reproduced data demodulated as described above is transferred by the control circuit 15 to a host computer (not shown).

Furthermore, when reproducing data of other blocks, it can be performed in the same manner as described above. In this case, as the block to be reproduced moves toward the outer periphery, the data is reproduced with the reference pulse speeding up. Therefore, data on the optical disc 1 is reproduced at high speed.

Furthermore, when reproducing the original pre-mat 7t-mat, the frequency of the reference clock output from the reference clock oscillator 22 from the control section 15 is changed to the frequency multiplied during normal data reproduction. As a result, the reference pulse becomes as shown in FIG. 3(a). Furthermore, a frequency range switching circuit 39 switches the frequency range of the voltage controlled oscillation circuit 35 in response to a frequency range switching signal from the control section 15 and outputs a reproduction pulse.

This reproduction pulse has a frequency W times that of normal data reproduction, as shown in FIG. 3(a)K. Therefore, the entire cycle of the reference pulse and the reproducing pulse operate in the same manner as in the case of normal data reproduction.

In addition, when it is known that code data will not be input, or when recording data on the optical disc 1, the control circuit 1
An input signal switching circuit JJK select signal is supplied from 5. This is K, the input signal switching circuit 3 is the frequency dividing circuit 63.
Outputs the reference pulse frequency-divided clock supplied from As a result, the reproduced t4 pulse can be made equal to the reference arm pulse. As a result, when recording data, the playback pulse can be treated as a recording pulse (base I-" pulse) as it is, and when the code data is not input from the control circuit 15, the lock around the reference pulse is busy. By switching, it is possible to avoid a large shift in frequency in advance.

Ru.

The signal waveform diagram of the main parts in the above operation is shown in Figure 3 (a).
) (b) K is shown.

As mentioned above, the frequency of the reproduction pulse and the reference pulse are almost the same, the reproduction pulse and the reference pulse are synchronized, and the reliability of the reproduction pulse is improved by a simple means. Therefore, various code data having different frequencies can always be accurately demodulated into reproduced data. Additionally, it is not necessary to have a highly accurate external mechanism to detect frequency deviations, which can be handled by internal circuits.

Furthermore, accurate demodulation processing can be performed without the intervention of a control system, and complete recovery can be carried out in a short time in the event of an abnormality in the reproduction 4 pulses.

In addition, the value of the tolerance setting circuit can be changed by setting from an external control circuit.

The time width t, b margin for comparison can be changed according to the judgment of the control circuit, and for example, the comparison can be performed with a margin according to the 2-7 code or a margin according to the pseudo χ code. By shortening the time period for comparison, the overall comparison time can be shortened. Also, it is better to take a longer comparison time while reading data.
It is possible to have versatility, such as stability. Furthermore, the entire modulation group can be integrated into an LSI, and various codes can be used as functions, and comparisons can be made in various time widths during recording and playback. You can have it.

Furthermore, it is possible to supply pulses for reproduction with high reliability for any code data, even if the data format requires a frequency change in the middle.

〔Effect of the invention〕

As detailed above, according to the present invention, it is possible to prevent the reproduction pulse from deviating greatly from the reference frequency, and it is possible to always accurately demodulate code data into reproduction data. It can be changed from 1 to 3 and can handle any code data, providing a highly versatile data demodulation method.

[Brief explanation of drawings]

The drawings are for explaining one embodiment of the present invention, and FIG. 1 is a block diagram schematically showing the configuration of the demodulation section, FIG. 2 is a block diagram showing the configuration of the frequency comparison circuit, and FIG. 3 is a block diagram showing the configuration of the frequency comparison circuit. A signal waveform diagram for explaining the main parts of the operation, Fig. 4 is a schematic diagram of the configuration of the optical disc device, Fig. 5 is a plan view showing the configuration of the optical disc, and Fig. 6 shows the relationship between the disk and the detector. FIG. 7 is a perspective view for explaining a storage example of a conversion table, FIG. 8 is a block diagram schematically showing the configuration of a conventional demodulation section, and FIG. 9 is a main part in FIG. 8. FIG. DESCRIPTION OF SYMBOLS 1... Optical disc (recording medium), 12... Optical head, 13... Binarization circuit, 14... Demodulator, 15...
...Control circuit, 22...Reference clock excavator (reference)
23. Programmable synthesizer (reference/pulse generation section), 31. Input signal switching circuit, 32. Phase comparison circuit, 33. Phase/voltage conversion circuit, 34. ...Rono bus filter, 35...Voltage controlled oscillation circuit, 36...Demodulation circuit, 37...Frequency comparison circuit, 38...Reproduction code output circuit, 39...
- Frequency range switching circuit, 41... Check length counter, 42... Start-up detection circuit, 43... Delay detection circuit, 44... Advance detection circuit, 45... Exclusive OR circuit, 61...Data/reproduction/arm phase comparison circuit,
62...Reference/4 pulse/reproduction pulse phase comparison circuit, 6
3... Branch circuit, 64... Tolerance range setting circuit. Applicant's agent Patent attorney Suzue Takehiko Zhu Hui 0νResponse 3rd vA(a) 38(b) 4th 5th figure 7rjA Figure 8

Claims (2)

[Claims] (1) In a device that code-converts code data read from a recording medium and demodulates it into reproduced data using a reproduction pulse generated based on a reference pulse supplied from a reference pulse generator, the reference pulse A means for changing the frequency, an output means for switching and outputting the reference pulse or code data obtained by this means, and a reproduction pulse generated in synchronization with the reference pulse supplied by the output means within its frequency range. a means for changing and generating the reference pulse in accordance with a change in the frequency of the reference pulse; and a demodulating means for code-converting the code data supplied by the output means in accordance with the reproduction pulse by the means and demodulating it into reproduction data; During demodulation by the demodulation means, means for adjusting the phase of the reproducing pulse to the phase of the code data supplied by the output means, and comparing whether the frequencies of the reproducing pulse and the reference pulse are different from each other. A data demodulation method characterized in that the output means outputs a reference pulse when there is a deviation, and means for causing the output means to output code data when there is no deviation. (2) The data demodulation method according to claim 1, wherein the means for generating the reproducing pulse has a wide frequency range and includes a voltage controlled oscillator whose predetermined frequency range can be arbitrarily switched.