JPS61273674A - Picture generating device - Google Patents

Abstract

PURPOSE:To avoid the vertical shifts of divided lines by giving the prescribed arithmetic operations to the output count values of both horizontal and vertical counters which are preset by the horizontal and vertical synchronizing signals for production of signals and at the same time varying the preset values of both counters for shifts of a picture. CONSTITUTION:A horizontal counter 52 loads the horizontal position data given from a latch circuit 50 when a load pulse of a horizontal scan frequency having a prescribed phase delay against the horizontal synchronizing signal is supplied from a video timing generator 34. At the same time, the counter 52 counts the dot clock signals given from a system timing generator 32. In the same way, a vertical counter 53 counts the horizontal synchronizing signals given from the generator 34. The count value of the counter 53 is multiplied by the maximum count value of the counter 52 by a multiplying circuit 55 and then added with the count value of the counter 52 by an adder 54. Thus the read address of a V-RAM is delivered 58 and the picture data is read out and scrolled.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an image generation device, which stores image data in image information to be transmitted in an image memory, and converts the image data read from the image memory into an analog video signal. The present invention relates to an image generation device that obtains and outputs images.

2. Description of the Related Art] A digital signal is recorded on a compact disc in a frame format 1 as shown in FIG. 2(A). In FIG. 2(A), one frame consists of 588 channel bits, and a frame synchronization signal 5YNC of 24 channel bits is provided at the beginning of the frame. Frame synchronization signal 5YNC is followed by data r) each consisting of 14 channel bits. -D12 are provided, and a 3-channel bit connection dot C is provided between the frame synchronization signal 5YNC and data Do-D32, respectively. l', Ml'! 17!1 channels each
Beep] Data D of ~. -D32 each is EFM (, T-1
When it is demodulated, it is converted into 8 bits, and these 8 bits are called symbols. Among the above data Do-r)32, one symbol of subcode is recorded in data r)o, and the remaining data D1 to D
32, 24 symbols of audio data and 8 symbols of error correction data are recorded.

-1 digits = 1 symbol (-8 bits) constituting the broad is P, Q, R, S, T, U for each bit.

■, is called W. Pill-P, Q+M Conventional J: Used as a retime code, and bits R to W were not used in the past, but a standard for use in graphic display has recently been decided.

As shown in FIG. 2(B), subcode t constitutes one data block with symbols for one frame of 98 frames, and the first two symbols are rib code sinks so and si. Hit P for the remaining 96 symbols.

Q is used as a time code, and image information [P]~R~W is divided into four packs for each 24 symbols. As shown in Figure 2 (C), each pack has 6 bits of the 0th symbol ] - (Pi + - R = w > represents the usage status of bits R to W and represents one mode and item. This mode and each bit of each item is 001 001” to indicate television graphics mode.1
The 6 bits of the number symbol are instructions (instrument i ~ laxcon)
Contains. These commands include drawing commands such as clearing a single color, setting a border color, drawing a medium font, scrolling, and writing a color look up double (rCl-UTJ). The next two mountains.

The third symbol is 0, which is the control m1 data of people's 6 bits.
Parity Qo for error correction for symbol No. and No. 1
, Q+. Each 6 bits of symbols No. 4 to No. 19 are used as a data field into which image data is entered. For example, if the command is a phono (one unit drawing command),
The 4th symbol contains data for the back color, the 5th symbol contains data for the front color (for example, the color of the text), and the 6th symbol.

71! Each symbol has 10 vertical positions on the screen and 4 horizontal positions on the screen.
Contains data for each of the C/four members. In addition, there are 6 dots horizontally for each 6 bit of 12 symbols No. 8 to No. 19]
Image data for one font consisting of 12 vertical dots I- is entered. In this image data, for example, II O11 corresponds to the back color, and 11 l II corresponds to the front color. Furthermore, the 6 hits of symbols 20 to 23 are the same as numbers 0 to 23 above.
Parity Po for error correction for the 19th symbol,
They are P+, P2, and P3.

The subcodes played on a compact disc player and subjected to separate interleaving are shown in image 1-
serially transmitted to the configuration device. The image generation device first dinterleaves the transmitted subcode and converts it into the image shown in Figure 2 (
Convert to the format shown in C). Furthermore, parity Po"-P3
Error detection and error correction are performed using Qo and Q+. Thereafter, the instructions contained in the symbols No. 0 and No. 1 of the pack are decoded. For example, a video random access memory (rV-R
Image data is input to and output from AMJ (abbreviated as J). This V-
The image data sequentially read out from the RAM is converted into three primary color data using a color look up table (hereinafter abbreviated as rCL LJ TJ), and each primary color data is converted to r)/A and converted into an analog primary color signal. and then supplied to a monitor receiver.

By the way, a display section 2 is displayed surrounded by a border portion 1 on the screen 1 of the monitor receiver shown in FIG.

The display section 2 displays 48 fonts (288 dots) in the horizontal direction and 192 dots (16 fonts) in the vertical direction.

Problems to be Solved by the Invention The V-RAM in a conventional image generation device stores image data for at least 288×192 dots. At this time, the image data of the top line of the display section 2 shown in the third figure is sequentially stored in the V-RAM from the left end to the right, and then the image data of the next lower line is sequentially stored in the same way. There is.

Some conventional image generation devices perform scrolling, that is, image movement, by changing the readout start address of the V-RAM.

However, in the conventional device, the address counter that generates the read address of the V-RAM is scrolled [4].
1 and 'l as well, only the clock signal for address generation is counted, regardless of the horizontal synchronization signal of the displayed image. Therefore, when the display section 2 shown in the third figure is scrolled horizontally, for example, rightward, the normal display (non-scrolling)
The first line displayed as one line when
(i) is the earlier part L (i) a and the later part 111 1-
(i) and b, and these are displayed across two lines as shown in FIG. 3. First half 1-
(i) To the left of a is the (i-1)th line l-(
The late part 1(i-1)t') of i -1> is located, and the (i -+-1)th line l-(the early part of i +1 Part 1 (i I-1)
a is located. In this way, when the screen is moved in the horizontal direction, the display section 2 is shifted by one line in the vertical direction between the right side and the left side.

In order to solve this problem, the patent application proposed by the present applicant on the same date as this application (1. Clarification of the title of the invention [image generation device])
A read address of the V-RAM is generated by a horizontal address generator which is preset according to the horizontal synchronizing signal and an in-type address generator which is preset according to the vertical synchronizing signal as shown in s. good. However, in the device described in -1-, the efficiency of V-RAM usage is poor, a V-RAM is required between entry points, and there are problems in that the number of address lines is large.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an image generation device that solves the above problems by using a horizontal counter, a vertical counter, and an address calculation circuit.

Means for Solving the Problems In the present invention, the image information to be transmitted is arranged in a predetermined format and errors are detected and corrected. The Il control data of this image information is decoded and the image data of the image information is written to addresses corresponding to both display surfaces of the image memory. The output count value of the horizontal counter that counted the preset clock signal is supplied to the address calculator together with the output count value of the vertical counter that counted the preset horizontal synchronization signal, and a read address is generated there. Image data is sequentially read out from the image memory according to this read address, converted into color data, and then converted into an analog video signal.

Function: In the present invention, image data is stored at an address corresponding to the display screen of the image memory.

Further, the horizontal address generator is preset according to the horizontal synchronizing signal to count clock signals, and the vertical address generator is preset according to the vertical synchronizing signal to count the horizontal synchronizing signals. The output count value of the vertical counter is multiplied by the maximum count number of the horizontal counter in an address calculation circuit, and then added to the output count value of the horizontal counter to generate a read address of the image memory. In this way, the vertical counter inputs the horizontal open 111 signal independently of the horizontal counter, and since the read address is generated by the address arithmetic circuit, even when scrolling in the horizontal direction, each divided line will move up and down. There is no shift by one line, and the image memory can be used effectively.

Embodiment FIG. 1 shows a block system diagram of an embodiment of the apparatus of the present invention. 4, the terminal 10 includes a serial subcode (image information) as shown in FIG. 4(A), a bit clock signal as shown in FIG. 4(B), a word clock signal as shown in FIG. 4(C),
Further, a subcode sync signal is input and supplied to the inter-base circuit 11. The interface circuit 11 latches each pit W-P of the incoming word clock signal.The word clock signal indicates the end point of latching of the subcode of each word. It is used as an interrupt instruction signal for the first CPU (central processing unit) 12.The CPU 12 receives a 6-bit parallel signal from the interface circuit 11 via the bidirectional data bus 1; 3 at the L level of the word clock signal. Import subcodes R to W for one symbol.
The 1JB]-do sync signal is a signal that becomes 1-Level when subcode sync 80, Sl, shown in FIG. 2(B) is detected.

The CPtJ12 executes a program stored in the ROM14, and at this time, the RAM2S is used as a work area. The output address of CPU12 is address bus 1
6 to ROM14. Address decoder 17.1=supplied to each receiver 18.

The address decoder 17 selects the first position of the address from l to R.
OM14. It determines which RAM 15 is being accessed and supplies control signals to them. Selector 1
8 is the address and control signal of the CPU 12, and C which will be described later.
Switch the address and control signal of P tJ 20 and R
The RAM 15 is connected by a selector 19 to either the bidirectional data bus 13 or the bidirectional data bus 21.

The first CPLJ 12 accumulates 6 to 1 of each symbol supplied from the interface circuit 11 and performs the processing shown in the fifth figure for each pack (=271 symbols). First, the CPU dinterleave the subcode for one pack (step 40) and convert it into the format shown in FIG. 2(C).

Next, error detection is performed for the 0th to 19th symbols using the parity Po=P3 of the 20th to 23rd symbols (step 41). If it is determined that there is an error in this P parity check (step 42), the above parity P o ”
□ The error P3 is corrected (step 43), and a Q parity check (step 44) is performed. 1] If there is no error in the parity check, proceed directly to step 44.

In step 44, the parity Qo of the second and third symbols,
Error detection of ON and 1st symbols is performed using Q+. Next, it is determined whether or not there is an error in the Q parity check (slab-f45), and only if there is an error, error pin 1- is corrected using parity Qo and Q+ (step 46), and the process ends. do.

The subcode for one pack as shown in FIG. 2(C) obtained in this way is
Both are transferred and stored in an accessible area. This subcode tit second CPtJ (central processing unit ■
) 20, the instruction is decoded. CP tJ 20
executes the program stored in the ROM 22.

CP LJ 20 output address number address bus 23J, ROM 22. Address decoder 24. Selectors 1, 8, 25, and 26 are respectively supplied. The address decoder 24 reads the upper bits of the address from the ROM 22. R.A.
M15° Cathode Ray Decoder: 1-in-1 Herola (hereinafter abbreviated as rGRTCj)27. V-RAM2
8. Bordership circuit 29. A control signal for each of the CLtJTs 30 is generated and supplied to each. CP LJ 20
address and control signals are sent to the RAM via the selector 18.
One pack of image information read out from the RAM 15 is supplied to the CPU 20 via the selector 19 and the data bus 21. CP tJ 20 is this 1
Decipher the 1st symbol, which is the control data of the 1t block for the pack.

The CPLJ 20 is located at the fixed address of the V-RAM 2B when the decoded command instructs drawing in units of fonts, for example, in the 6 bits of symbols 4 to 19 in FIG. 2(C). Image data for 1 phon i is inputted and outputted via the data bus 21. Also, when the command instructs border color setting, the border latch circuit 29 latches 4-bit image data instructing the border color,
When the command instructs to write Ci U, CL LJ T
Rewrite the contents of the daple at the specified address of 30. When the command instructs scrolling, the CRTC 27 is set with the initial value of the read address of the V-RAM 28.

The system timing generator 32 has a built-in oscillator, and generates clock signals for each of C[)Us 12 and 20 from its oscillation output. The clock signal of the CPU 12 is CP
The clock signal of CP LJ 20 is supplied to LJ 12 and address decoder 17, and is also supplied as a switching signal to selectors 18 and 19, respectively.
0 and the address decoder 24. Also,
The system timing generator 32 generates a clock signal (one period of this signal corresponds to 4 dots 1) which is exactly the same as the 1 clock signal of the CPU 12 and CR'.
This dot clock signal is also supplied to the C selector 25 as a switching signal. Further, the system timing generator 32 generates a timing signal 4'li and supplies it to the parallel/serial converter 33, and further supplies a signal to the video timing generator 34. The video timing generator 34 generates a horizontal synchronization signal and a vertical synchronization signal from this clock signal and supplies them to the CRT 027, and also outputs a switching timing signal (1) to the selector 2.
Further, a composite signal obtained from the horizontal synchronizing signal 1 and the vertical synchronizing signal is supplied to the terminal 35.

Next, as shown in FIG. 6(A), the V-RAM (image memory) 28 is stored at 300 ms in the horizontal direction corresponding to the display screen (shown in the third figure).
Image data for 216 dots in the vertical direction is recorded by 0 dots i. -1 note 300 dots x 216
The image data of 288 dots 1 x 192 dots 1 of the dot image data is displayed on the display section 2 shown in the third figure. The reason why image data exceeding the display area of the display section 2 is stored in this way is to perform scrolling. 1 bit of image data consists of 4 hits, and 1/4 bit
With 6 bits i as one word, addresses of 16200 (= 75 x 216<2'') are stored in the V-RAM2B described in 1 from the left end to the right end in the horizontal direction of the display screen and from the end to the bottom end in the vertical direction. That is, 16 bits of image data from dot 1 Do to dot D3 shown in FIG. 6 (A>) is stored at address 0 of the V-RAM 28.

(7) V RAM 2 B 2 CPU U 20
Gm Yo') When writing image data, 8 bits (2 bits worth) of image data supplied from the data bus 21 are sent to an address supplied from the address bus 23 via the selector 25 and an address decoder. It is written to the location indicated by the control signal that indicates the 11th place 8 bits l- and the lower 8 bits supplied from 24. Also, V-R
Image data is read out from AM28 in words (-16 bits) It for each address.

The CRTC 27 has the configuration shown in FIG. In FIG. 7, the same parts as in FIG. 1 are marked with the same line. CRT C27L
i latch circuit 50.51. Horizontal counter 52. Vertical counter 53. It is composed of a compressor 54 and a driving circuit 55. When the latch circuit 50 receives a latch instruction control signal from the address decoder 24 via the terminal 56, it latches the 7-bit horizontal position data supplied from the CPU 20 via the data bus 21. In addition, the latch circuit 5
1 receives a latch instruction control signal from the address decoder 24 via the terminal 57 (then, the 8-bit vertical position data supplied from the CI via the data bus 21) is latched.

By the way, there are two types of drawing commands that instruct scrolling (screen movement) among the commands shown in FIG. This is because when the screen moves to the right due to scrolling, for example, an image that disappears at the right edge of the screen appears from the edge of the screen and the screen becomes a continuous cylindrical image. There are two types: scroll with preset, where the image that disappears at the right edge of the screen is erased, and the erased image appears from the left edge of the screen. Both Scroll with Copy and Suff [1-Le with Priscilla 1- are 6 each]
Parameters such as the vertical movement direction (top or down), the horizontal movement direction (left or right), the number of vertical movement dots, and the horizontal movement dot number are set in the bit symbols 4 to 19. In addition, a color parameter for erasing the image is provided in the case of a color with preset. The horizontal movement by a single scroll command is a maximum of 11 dots, and the vertical movement is a maximum of 23 dots.

In normal times when scrolling is not instructed, the value of the latch circuit 50 is 1 in decimal, and the value of the latch circuit 51 is 12 in decimal. The CPU 20 executes the process shown in FIG. 8 every time a single scroll command is received. First, determine the direction of lateral movement (step 60), add the leftward moving dots 1 to 1, and subtract the number of rightward moving dots to find the number of lateral dots (steps 61 and 62). Dividing the number by 4, adding 1 to the integer value of the quotient, and sifting the water =
18- Find the flat buying data i (step 63). At this time, the number 300 of the horizontal drive 1 is wrapped around. Also, the vertical movement direction is determined (step 6
4) Upward moving drums 1 to 3 are cylinders.

The number of dots moving in the downward direction is reduced to obtain the number of dots in the [7j direction (steps 65 and 66), and 12 is added to this number of vertical dots to obtain vertical position data, j (step 67). At this time, the vertical dot numbers 0 and 216 are wrapped around.

Thereafter, it is determined whether or not it is a vertical blanking period using the vertical synchronization signal from the timing generator 34 (step 68). If it is a vertical blanking period, the horizontal position data i, vertical position data, and j are transferred to the latch circuit 50. 51 and the latch is opened (step 69).

In this way, the values of the latch circuits 50 and 51 during normal operation (
The horizontal position data, vertical position data) are set to 1°12, and the value to be changed when scrolling according to M is V-R.
Yokota t on AM2B? 50 fonts (=300 dots 1-
-75 words), image data for 18 fonts in the vertical direction (=216 dots 1~) are stored, and 18 fonts in the horizontal direction and 16 fonts in the vertical direction are displayed on the display screen, so Of the image data stored in the V-RAM 28, only the image data of the center part 28B excluding the image data of the peripheral part 28A shown in FIG. This is to read out and use it for display when scrolling.

Returning to FIG. 7, the horizontal counter 52 is a 75-decimal counter, and the horizontal scanning frequency load pulse having a predetermined phase delay with respect to the horizontal synchronizing signal shown in FIG. (B)) is supplied from the video timing generator 34, the horizontal position data supplied from the latch circuit 50 is read [1-]. Thereafter, the horizontal counter 52 generates a drum clock signal as shown in FIG. Power run]
~do. The above load pulse corresponds to the starting position (left end) of the horizontal plane of the display section 2 on the display screen shown in the third figure. Therefore, when horizontal position data such as ``20'' in decimal is loaded during scrolling, the horizontal counter 52 counts up to ``74'' from ``20'' with the input of the dot clock signal, and then returns to ``0''. Count up to ``19''.

The vertical counter 53 is a 216-decimal counter, and the 10th
When the video timing generator 34 supplies the load pulse shown in FIG. 3B with a vertical scanning frequency that is a predetermined horizontal synchronization period apart from the vertical synchronization signal shown in FIG. The horizontal synchronizing signal supplied from the direct video timing generator 34 is loaded from 1 to 1. This load pulse is applied to the vertical start position (upper end) of the display unit 20 shown in the third figure.
It corresponds to J. Therefore, the vertical counter 53 uses, for example, "1" in -1 base as vertical position data during scrolling.
When "00" is loaded, rl
After counting sequentially from ooJ to r215J, it becomes ``0['', and then it continues counting from 1 to ``99''.

The 8-hit count value output by the vertical counter 53 is
The signal is supplied to a multiplication circuit 55 which together with an adder 54 constitutes an address arithmetic circuit. The multiplier circuit 55 increases the output count value of the vertical counter 53 to 75 (this is rOJ-r74J in decimal
There is a maximum count number of horizontal counter 52 that counts . ), and is configured with, for example, a ROM in which output values corresponding to input values are stored in advance.

Of course, the multiplication circuit 55 may be configured with a programmable logic array (PLA), an adder, or the like. Since the count value of the vertical counter 53 is the maximum decimal value r215J, the multiplier circuit 554 outputs a 14-bit value. The output value of the multiplication circuit 55 is added to the output count value of the horizontal counter 52 in an adder 54. The 14-pit read address of the V-RAM 28 thus obtained is output from the terminal 58.

That is, the 7-bit count value output from the horizontal counter 52 is the lower address, and the 8-bit count value output from the vertical counter 53 is the upper address.
5L'/l-'T'' When accessing the V-fLAM 28, the area in which the image data in the V-RAM 28 is stored is the satin-finished area in FIG. 6(C), and the remaining diagonally shaded area is an unused area.On the other hand, if V-RAM 28 is an unused area with 14 bits using a multiplying circuit 55 and an adder 54 as shown in FIG. The portion in which image data in the D41 V-RAM 2 B is stored is a satin-finished portion that is close to almost the entire area in FIG. 6(D), and the remaining slightly shaded portion is an unused area. By doing so, the storage capacity of the V-RAM 2B can be kept to a minimum and it can be used effectively.Furthermore, the number of output address lines of the CRTc 27 can be reduced.

In addition, the vertical counter 53 and the horizontal counter 52 are numbered 1 and 1.
Run the horizontal synchronization signal regardless. For this reason, the third
When the illustrated display section 2 is scrolled horizontally, for example, to the right, the first line 1 (j> that is displayed as one line during normal display (non-scrolling) is the first half 1 (, j)
8 and late part 1 (j) b, and early part L (,
j) Late part L(j)b is located on the left side of the same line as a. This also applies to other lines such as line l(j+1). Therefore, during horizontal scrolling, the display section 2 does not shift vertically between the right and left sides.

Furthermore, as shown in FIG. 8, the latching of the horizontal position data and vertical position data to the latch circuits 50 and 51, that is, the brissera i of the horizontal address counter and the vertical address counter, respectively, is performed during the vertical planning period, so the display The image does not fluctuate horizontally or vertically.

The address output by the above CRTC27 is the selector 2
5 to the V-RAM 28, and 4 bits of 16-bit image data are read out in parallel from the V-RAM 2B in accordance with this address. For example, 16 bits I~ image data read at address O is dot D.

The upper bits of the 4 pins 1- of
2, 4 bits each are arranged in the order of Da. The image data read out in this manner is supplied to the parallel/serial converter 33.

The parallel/serial converter 33 has a configuration as shown in FIG. In the figure, the wrap circuit 70 is shown in FIG. 12(A).
4 dots 1 read out from V-RAM 28 as shown in 1-
Of the image data for -16 bits 1, 1 bit data for each dot (4 bits) is input from the terminal 71. This 4-pitch 1-data is arranged such that, for example, 1 bit of dot Do is the MSB and 1 bit of tod D3 is 1-SB. The latch circuit 70 described above and the shift register 72 described later are each provided with 411, and each of these 411 performs serial/parallel conversion of 1 bit it 4 hits for each dot. The latch circuit 70 is supplied from the system timing generator 32 as shown in FIG.
A latch pulse shown in B) comes in via terminal 73 and the four bits mentioned above are latched.

The latch circuit 70 supplies the latched 4 bits F- and 2 to the shift register 72. The shift register 72 is the first
A shift i clock shown in FIG. 2(C) is supplied from the system timing generator 32 via a terminal 74, and a load pulse is supplied from the comparator 75.

The comparator 75 is supplied with 2-bit timing signals shown in FIGS. 12(1') and 12(E) from the system timing generator 32 via a terminal 76. Furthermore, 2-bit timing instruction data is supplied to the latch circuit 77 from the CPU 20 via the data bus 21 and the terminal 78. This timing instruction data is determined in step 63 of the process shown in FIG. ", and when the remainder is "3", the first and second bits are "1ilZl"0", and when the remainder is "0", the first bit]-9 is "0'°,"1'', and when the remainder is 11'', both the first and second bits are ``1''. This timing instruction data from the CPU 20 is latched by the latch circuit 77 and constantly supplied to the comparator 75. The comparator 75 compares the 2-bit timing signal shown in FIGS. 12(D) and 12(F) with the 2-bit timing instruction data, and when the two match, it generates a load pulse and outputs a shift h l nozzle. Supply to. The shift 1-register 72 takes in the 4-pip 1- data supplied in parallel from the J: reload circuit 70 as a load pulse, shifts it using the shift clock, and outputs it sequentially from the MSR. The full data output from the shift register 72 through the terminal 79 constitutes 4-bit image data for 1 driver 1 to 4 bits, together with the output serial data of the shift registers of the other three circuits. 1 to parallel image data are supplied to the selector 26.

In other words, the circuit shown in FIG. 11 changes the timing of the load pulse of the shift register 72 with respect to the latch pulse of the latch circuit 70 in accordance with the timing instruction signal from the CPU 20, thereby changing the timing of the data output from the shift register 72. It constitutes a variable length shift register with variable output timing. As a result, even though the image data is read out in 4-dot increments from the V-RAM 2B, horizontal scrolling in 1-dot units is possible.

Based on the switching timing signal from the video timing generator 34, the selector 26 switches the border latch circuit 2 during the period in which the border portion 1 of the display screen shown in FIG. 3 is displayed.
Border color image data (4 bits) supplied from 9
During the period when the display section 2 of the display screen is displayed, 4-bit image data is taken out from the parallel/serial converter 33, and the taken out image data is sent to the CI UT3.
0 as the read address. By the way, during the vertical blanking period of the display screen, a 4-bit address is taken out from the address bus 23 and supplied to the UCILJI-30 as a write address.

CLUT 30 has a 4-bit address, and each address has three primary colors R (red), G (green), and 13 (blue).
This RAM stores 8112 bits of color data, each represented by 4 bits. The color data of each address designated by these 4 bits 1 can be accessed and rewritten during the vertical blanking period as described above. During the vertical scanning period, the 4-bit image data supplied to the selector 26Jζ is accessed and color data is read out, thereby reading out the three primary colors R and G.

Color data of 4 bits each is supplied to the D/A converter 36. The I)/A converter 36 performs D/A conversion on the color data for each green color, and the resulting AB [1g red primary color video signal, green primary color video signal, blue primary color video signal] The signals are output separately from terminals 37, 38 and 39. The primary color video signals of red, green, and blue flames from the terminals 37, 38, and 39 and the composite synchronization signal from the terminal 35 are supplied to a monitor receiver (not shown), as shown in FIG. The screen is displayed.

Effects of the Invention 1 As described in 1, the image generation device according to the present invention can vary the preset values of the horizontal counter sent to the preseller 1 in response to the horizontal synchronization signal No. 13 and the preset value of the vertical counter pre-hitted in response to the vertical synchronization signal. At the same time, the address arithmetic circuit generates the read address of the image memory using the output current values of the horizontal and vertical counters.
Even when moving the image in the horizontal direction (scrolling), it is possible to prevent each divided line from shifting downward by one line, and it is also possible to reduce the number of address lines of the image memory read address, making effective use of the image memory. It has the advantage of being able to reduce its capacity.

[Brief explanation of the drawing]

FIG. 1 is a block system diagram of one embodiment of the device of the present invention, and FIG.
The figure is a diagram for explaining the subcode, Figure 3 is a diagram for explaining the display screen, Figure 4 is a time chart of an example of a signal input to the device shown in Figure 1, and Figure 5 is the diagram for explaining the display screen shown in Figure 1. FIG. 6 is a diagram for explaining the storage state of image data in the V-RAM shown in FIG. 1, and FIG. 7 and FIG. FIG. 8 is a circuit system diagram of an embodiment of each circuit of the device shown in FIG. 1; FIG. 8 is a flowchart of an embodiment of some processes executed by the second CPU shown in FIG. Each of FIGS. 10 is a time chart of one embodiment of the signal entering the circuit shown in FIG. 7, and FIG. 12 is a time chart 1- of one embodiment of the signal entering the circuit shown in FIG. 11. 11...Interface circuit, 12.20...C
PtJ, 15...RAM, 27...Cathode Ray Chicove Controller (CRTC), 28...Video Random Access Memory (V-RAM), 3
0...Color look up table (CL-L
JT), 32... system timing generator, 33.
...Parallel/serial converter, 34...Video timing generator, 36...I)/A converter, 40-46
゜60~69...step, 50.51, 70.77
...Latch circuit, 52...Horizontal counter, 53...
- Vertical counter, 54... Adder, 55... Multiplier circuit, 72... Shift 1 to register, 75... Comparator.

Claims (1)

[Claims] After arranging the transmitted image information in a predetermined format and detecting and correcting errors, decoding the control data of the image information,
The image data of the image information is written in an address corresponding to the display screen of the image memory in accordance with the control unit data, the image data read from the image memory is converted into color data, and an analog video signal is generated from the color data. An image generation device that obtains a horizontal counter that is preset according to a horizontal synchronization signal when displaying the video signal on a screen and counts a clock signal corresponding to a horizontal display speed, and a horizontal counter that is preset according to a vertical synchronization signal. a vertical counter that counts the horizontal synchronization signal, and a read address of the image memory is generated by multiplying the output count value of the vertical counter by the maximum count number of the horizontal counter and then adding the output count value of the horizontal counter. 1. An image generating device comprising an address arithmetic circuit that moves an image on both display surfaces by varying preset values of the horizontal counter and the vertical counter.