JPH02135493A - Graphic displaying device - Google Patents

Abstract

PURPOSE:To improve the picture drawing performance of the title display device to a sufficient area by a monochroic display by selecting whether all P bits of a frame buffer are to be outputted or only the bits of prefixed one plane are to be outputted in accordance with the displaying mode of the display device. CONSTITUTION:A microprocessor 1 expands displaying information to a picture pattern and stores the picture pattern in a frame buffer 4 after interpreting a solid-state displaying instruction from a host device. The frame buffer 4 is composed of P pieces of planes and stores displaying picture information of color codes of P pieces of bits in such a way that each plane is made to correspond to each bit. A color pallet 7 has 2<p> pieces of entries addressed by the output of the buffer 4 and prefixed displaying color data are stored in each entry. An area defining register 10 defines a monochroic displaying area and a pallet address control circuit 11 selectively controls the address of the pallet 7 in accordance with a selective control signal outputted from the register 10.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a graphic display device, and more particularly to a graphic display device having color and monochrome display functions.

An example of a conventional graphic display device is shown in FIG. The microprocessor 1 is a microprogram execution unit, and the memory 2 is a microprogram and data storage unit. The interface control unit 3 is a host device (not shown)
This is the part that controls the interface with.

The frame buffer 4 is a part that stores display pixel information, and if color display is possible, for example, 256 colors,
This frame buffer 4 consists of eight planes as shown in FIG. Each plane has at least the capacity of a bitmap color monitor;
This is the configuration of a color frame buffer in the case of a color monitor that simultaneously displays 256 colors with 1024 pixels. It has 8 planes #o to #7, each plane has 2048 horizontal bits (1280 of these are used),
It consists of 1111024 bits.

A color code is displayed using 8 bits corresponding to each plane, and this 8-bit color code is converted into serial information by a dot shifter 6. This 8-bit serial data becomes the address input for the color palette 7.

This color palette 7 has 256 (2") color gradation data in each entry, and has a double memory configuration as shown in FIG. Each entry provides the brightness of R (red), G (green), and B (blue) using 8 bits.

The color gradation digital data of this color palette 7 is D
The signal is converted into an analog video signal by the /A converter 8, and is displayed in color on the CRT display section 9 under the control of the display synchronization circuit 5.

In the conventional graphic display device described above, writing to the frame buffer T4 during drawing must always be performed on all planes. Therefore, even when drawing an area such as a console screen where monochrome display is sufficient, writing is performed on all places. It is necessary to write to. Therefore, there is a drawback that drawing performance is unnecessarily reduced.

Therefore, the present invention has been made to solve these drawbacks of the conventional technology, and its purpose is to improve the drawing performance when drawing an area where monochromatic display is sufficient. An object of the present invention is to provide a graphic display device that can improve the performance of graphics.

According to the present invention, it consists of planes Pfll (P is an integer greater than or equal to 1), and each plane is defined as /? It has a frame buffer that stores display pixel information in the form of a color code of P bits associated with 1 bit, and 2P entries addressed by the output of the frame buffer, and predetermined display color data is stored in each entry. A graphics display device that displays graphics according to the output of the color palette, and outputs all bits or only the bits of one predetermined plane among the P bits output from the frame buffer. There is obtained a graphic display device characterized in that the selection means for selecting whether to output the image and the control means for controlling the selection means depending on whether the display mode is a color display mode or a monochrome display mode have different widths.

Sad ■j Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a graphic display device according to an embodiment of the present invention, and in FIG. 6, parts equivalent to those in FIG. The memory 2 is a storage unit for microprograms and data, and the interface control unit 3
is the part that controls the interface with the host device.

That is, the microprocessor 1 interprets a graphic display command from a host device by executing a microprogram, develops display information into a pixel pattern, and stores the pixel pattern in the frame buffer 4.

The frame buffer 4 is a multi-plane memory that stores display pixel information in the form of a color code in which each plane corresponds to one bit. That is, in order to realize the display performance of 2P simultaneously expressed colors with a display resolution of M pixels and XN lines, it is necessary to configure a frame buffer with the number of planes P and at least M×N bits/plane.

The dot shifter 6 is a part that converts display pixel information read out from the frame buffer 104 into pixel serial information. The area definition register 10 is a register for defining a monochrome display area, and outputs a selection control signal to the palette address control circuit 11. The palette address control circuit 11 is a control circuit that selectively controls the address of the color palette 7 based on the selection control signal output from the area definition register 10. That is, when the selection control signal is logic "0", information on all planes of the frame buffer 4 is given as the address of the color palette 7. - If the force selection control signal is logic li 1 m, only information of one plane in the frame buffer 4 is given as the address of the color palette 7;

The color palette 7 is a table memory that outputs color gradation data using display pixel information selectively output by the palette address control circuit 11 as address information, and has 2' (P is the number of planes of the frame buffer 4) entries.

The D/A converter 108 is a part that converts the digital color III tone data outputted by the color palette 107 into an analog video signal.The 0 display synchronization circuit FIB5 controls the display readout of the frame buffer 4, and also controls the display readout of the frame buffer 4.
This is a part that generates a synchronization signal for display, and the CR7 display section 9 controls deflection using the synchronization signal provided from the display synchronization circuit 5, and displays the analog video signal provided from the D/A converter 8 on the screen on the cathode ray tube. This is the part to do.

2 is a detailed block diagram of the palette address control circuit 11 of FIG. 1, and FIG. 5 is a detailed block diagram of the palette address control circuit 11 of FIG.
This is an example of stored data.

When the output of the area definition register 10 is logic "0", the frame buffer outputs PO-P7 are given as they are as the color palette addresses AO-A7, resulting in 256-color display. When the output of the area definition register 10 is logic "1", the frame buffer PO is set to the color palette address A.
Therefore, in this case, the display color is determined only by the information stored in plane #0 of the frame buffer 4. In other words, it becomes a monochrome display.

Therefore, if the data of color palette 7 is horizontally constructed as shown in FIG. 5, in the screen area defined by area definition register 10, only the end OO and will be displayed.

As described in detail, according to the present invention, in the screen area defined by the area definition register, display is performed only based on information stored in only one plane of the frame buffer, not based on all planes of the frame buffer. By controlling this, when drawing an area such as a console screen where monochromatic display is sufficient, it is possible to perform drawing on only one plane, which has the effect of improving drawing performance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a specific example circuit diagram of a palette address control circuit, FIG. 3 is a block diagram showing a prior art, and FIG. 4 is a diagram showing the configuration of a frame buffer. FIG. 5 is a diagram showing the contents of the color palette l-. Explanation of symbols of main parts 4...Frame buffer 7...Color palette 10...Area definition register 11...Palette address control circuit Fig. 2

Claims (1)

[Claims] (1) Consists of P planes (P is an integer greater than or equal to 1),
It has a frame buffer that stores display pixel information in the form of a P-bit color code that associates each plane with one bit, and 2^P entries that are addressed by the output of the frame buffer, and each entry has a predetermined value. A graphics display device that displays graphics according to the output of the color palette, the graphics display device including a color palette storing display color data respectively stored in the display color data, and a graphic display device that displays graphics according to the output of the color palette. Ta1
A graphic display device comprising: a selection means for selecting whether to output only plane bits; and a control means for controlling the selection means depending on whether a color display mode or a monochrome display mode is selected.