JPS61273082A - Data recorder - Google Patents

Abstract

PURPOSE:To attain the effective utilization of a central processor by bringing a part between a port of a central processor generating binary data for recording and a latch circuit connected to the port into a high impedance state substantially except at the superimposing period decided with a synchronous signal in a video signal. CONSTITUTION:A Q output (c) of a counter 5 and an output of an inverter 9 are ANDed by a AND gate 10 and its output (g) shows the data overlap period to the video signal. The output (g) of the AND gate 10 is fed to a CPU12 and a buffer 14 and the buffer 14 goes to a high impedance state at a period other than the data overlap period. Further, no rectangular wave is outputted from a 1/4 frequency divider 7 other than the data overlap period and a 4-bit latch and a shift register circuit 11 are inoperative, then ports X1-X4 of the CPU12 and the circuit 11 are in high impedance state substantially. Thus, the ports X1-X4 of the CPU12 and a port Y are usable other than the data overlap period.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a data recording device, and more particularly to a device for recording binary data by superimposing it on a predetermined portion of a video signal.

(Summary of the Disclosure) This specification and drawings describe an apparatus for recording binary data by superimposing it on a predetermined portion of a video signal, and in which the data is stored during a superimposition period other than a superimposition period determined using a synchronization signal in the video signal. ,
To provide data recording that can effectively utilize a central processing unit by configuring a port of a central processing unit that generates binary data to be recorded and a latch circuit to which this is connected to a substantially high impedance state. This is to disclose the technology.

(Prior art) Generally, when recording a video signal on a recording medium, it is extremely difficult to record it on a single track because it is necessary to have a large relative speed. Therefore, when recording a video signal The home video tape recorder (V
As is well known in the field of video recording systems such as TR), recording was performed by forming one track for every one minute of video signal.

By the way, in the video signal recording device as described above,
When recording binary data by superimposing it on a video signal, it is considered to record the data in synchronization with the horizontal synchronization signal (HD) in the video signal, which requires recording an extra synchronization signal. This is advantageous in making the recording and playback timings of the data editions coincide. In addition, at this time, the number of data superimposed on the video signal of l track, that is, l field, the number of horizontal scanning periods (H) for superimposing data, etc. are related to powers of 2 for convenience of later processing using a binary counter etc. It is assumed that the value is Therefore, the period during which the data signal is superimposed does not necessarily coincide with the period of the l field, and therefore data is recorded in such a manner that it is superimposed only on a predetermined portion of the video signal.

(Problems to be Solved by the Invention) By the way, in the data recording device as described above, when recording data is generated via a central processing unit (CPU) such as a microcomputer, the CPU has a port for generating this recording data. In reality, it was used exclusively for this purpose.

The present invention has been made in view of the above-mentioned background, and an object of the present invention is to provide a new data recording device that can effectively utilize ports of a central processing unit.

(Means for solving the problem) In view of the above-mentioned object, the present invention provides an apparatus for recording binary data by superimposing it on a predetermined portion of a video signal. During periods other than the superimposition period, the port of the central processing unit that generates the binary data to be recorded and the latch circuit connected thereto are configured to be in a high impedance state.

(Function) By configuring as described above, it becomes possible to connect the recorded data generation port of the central processing unit to another mechanism, etc. during periods other than the overlapping period, and this mechanism Accordingly, a data recording device that can effectively utilize the central processing unit is obtained.

(Example) The following is an example in which the present invention is applied to an electronic camera device that records a visible image obtained from an optical system on a recording medium as a video signal for one field on a circular track. This will be explained in detail using .

Fig. 1 is a diagram showing the configuration of an electronic camera device as an embodiment of the present invention. 3 is a circuit that separates the vertical sync signal (VO), 4 is an AND gate,
5 is a counter, 6 is an AND gate, 7 is a l/4 frequency divider,
8 is a counter, 9 is an inverter, 10 is an AND gate,
11 is a 4-bit latch and shift register, 12 is a CP
U, 13 is l/4 frequency divider, 14 is buffer, 15 is D
P S K (Differential Phase
16 is a video signal processing circuit, 17 is an addition circuit, and 18 is a recording section.

FIG. 2 is a timing chart showing the waveform of the first figure numbered part, and the operation of the first figure numbered part will be explained below using FIG.

A visible image captured through the optical system is converted into a video signal by a circuit (not shown), and is inputted from a terminal 1. The input video signal is supplied to the HD separation circuit 2 and the VD separation circuit 3 to separate the HD (shown in FIG. 2(b)) and VD (shown in FIG. 2(b)).
The 0-separated HDs shown in a) are supplied to a counter 5 via an AND gate 4 at the beginning of each field, and the falling edge thereof is counted. When the counter 5 counts up to a preset number, it outputs a high level (Hi) as a Q output. The Q output of this counter 5 (shown in FIG. 2(C)) is supplied to an AND gate 6 and gates HD via an AND gate 4.

The HD gated by the AND gate 6 (shown in FIG. 2(d)) is input to the 1/4 frequency divider 7, and this signal becomes a 4H period rectangular wave signal (shown in FIG. 2(e)). Square wave signal (e
) drives the parallel-in/serial-out 4-bit latch and shift register 11, and the recording data input via each port of the CPU 12 is transferred to D.
The signal is supplied to the PSK modulation circuit 15. DPSK modulation circuit 1
The data signal output from 5 is supplied to adder l7,
Through the video signal processing circuit 16, the signal is frequency-multiplexed with a video signal in a signal form suitable for recording. The frequency multiplexed signal output from the adder 17 is supplied to a recording section 18 including recording means such as a magnetic head, and is recorded on a recording medium.

13 is a 1/4 frequency divider that further divides the output (e) of the 1/4 frequency divider 7 by 174, and the output of the frequency divider 13 is supplied to port Y of the CPU 12 via a buffer 14. . This signal is used by the CPU 12 to output new 4-bit recording data (baud) from XS to X.

, i.e., shift register 1
1 serially outputs 4 bits of data, new 4 bits of recording data are supplied in parallel to the 4 bit latch circuit.

On the other hand, the above-mentioned 1. The output (e) of the /44 frequency divider is counted by the counter 8, and when a predetermined number is counted, the Q output becomes Hi. The output signal of the counter 8 (shown in FIG. 2(f)) is supplied to the AND gate 4 via the inverter 9, and inhibits the AND gate 4 from gating HD(b). Accordingly, the 1/4 frequency divider 7 stops outputting the rectangular wave signal, and the 4-bit latch shift register 11 stops driving. Note that the counter 5 and the counter 8 are reset during the low level (Lo) period of VD.

The Q output (C) of the counter 5 and the output of the inverter 9 will be ANDed at the AND gate 1O, and this output (shown in FIG. 2 (g)) determines the data superimposition period on the video signal. It will be shown. The output of the anime/game) 10 is supplied to the CPU 12 and the buffer 14, and the buffer 14 is kept in a high impedance state during periods other than the aforementioned data superimposition period. Also, except for the data superimposition period, 1
Since the /4 frequency divider 7 does not output a square wave and the 4-bit latch and shift register circuit 11 is inactive, ports X1-X4 of the CPU 12 and the circuit 11
During this period, the state is substantially high impedance.

This allows port x of CPU12! ~x4 and Y are available for use outside the data overlay period. In this embodiment, this is used, and outside the data overlay period, X1#X and Y are set to the auto iris (AE) function in the camera unit. Used for control.

Next, control of this AE function will be briefly explained. 5P
When the brightness of the subject is detected by a light receiving element such as C (silicon photocell), it is supplied to an analog-to-digital converter (A/D) 20 and converted into 4-bit digital information.

At this time, the baud)Y of the CPU 12 is used for output,
It outputs the clock for A/D 20.

Further, output data for the A/D 20 is taken into the memory in the CPU 12 via input ports x1 to x4, and constantly controls the AE mechanism 21 including the aperture, shutter drive mechanism, etc.

FIG. 3 is a flowchart for explaining the operation of the CPU 12 in FIG.
2 uses x1 to x4 as an output port and Y as an input port, and performs the data recording operation described above.

Also, when the output (g) of the AND gate IO is LO, C
The PU 12 uses x1 to x4 as input ports and Y as an output port to perform the above-described AE mechanism driving operation.

In the above embodiment, the AEa structure can be driven by using the data generation board () It is also possible to configure it to process.

(Effects of the Invention) As described above, according to the present invention, it is possible to obtain a data recording device that can effectively utilize ports of a central processing unit.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the configuration of an electronic camera device as an embodiment of the present invention, Fig. 2 is a timing chart showing the waveform of the numbered part in Fig. 1, and Fig. 3 explains the operation of the CPU in Fig. 1. This is a flowchart for 1 is a video signal input terminal, 2 is a horizontal synchronization signal separation circuit,
3 is a vertical synchronization signal separation circuit, 5.8 is a counter, and 7 is a vertical synchronization signal separation circuit.
, 13 are frequency dividers, 11 is a 4-bit latch and shift register circuit, 12 is a central processing unit (CPU),
X l” Xa, Y, and Z are the ports of the CPU, respectively. Figure 3

Claims (1)

[Claims] A device for recording binary data by superimposing it on a predetermined portion of a video signal, the device determining a superimposition period between the video signal and a data signal including the binary data using a synchronization signal in the video signal. a central processing unit having a port that generates binary data to be recorded; a latch circuit to which the port is connected; and a connection between the latch circuit and the port that is substantially in a high impedance state except for the superimposition period. A data recording device comprising means for.