JPS61271695A - Memory device - Google Patents
Memory deviceInfo
- Publication number
- JPS61271695A JPS61271695A JP60113482A JP11348285A JPS61271695A JP S61271695 A JPS61271695 A JP S61271695A JP 60113482 A JP60113482 A JP 60113482A JP 11348285 A JP11348285 A JP 11348285A JP S61271695 A JPS61271695 A JP S61271695A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- battery
- backup
- power supply
- memory device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、ダイナミックRAMを用いたメモリ装置に
関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory device using a dynamic RAM.
第2図は従来のメモリ装置を示すブロック図であシ、図
において、3は電源切換手段、4はダイナミックRA
M (DYNAMICRANDOM ACCESS M
EMORY )、5はリフレッシュ回路、6は発振回路
、TはCPU 。FIG. 2 is a block diagram showing a conventional memory device. In the figure, 3 is a power supply switching means, 4 is a dynamic RA
M (DYNAMIC RANDOM ACCESS M
5 is a refresh circuit, 6 is an oscillation circuit, and T is a CPU.
Bはバッテリー、9は制御電源である。B is a battery, and 9 is a control power source.
次に動作について説明する。メモリ手段としてダイナミ
ックRAM 4を用いたメモリ装置においては、制御電
源9が切れた場合、ダイナミックRAM4の記憶内容を
保持するためKは他の電源と切換えて一定時間毎にダイ
ナミックRAM2に再書込み(以下、リフレッシュと称
す。)をする必要がある。Next, the operation will be explained. In a memory device using a dynamic RAM 4 as a memory means, when the control power supply 9 is cut off, K is switched to another power supply to retain the memory contents of the dynamic RAM 4 and rewrites the dynamic RAM 2 at regular intervals (hereinafter referred to as , called refresh).
この場合、従来のメモリ装置は電源切換手段3によって
バッテリー8に切換えて、このバッテリー8よりダイナ
ミックRAM4、リフレッシュ回路5、発振回路6に電
力を供給していた。この時、発振回路8によりリフレッ
シュタイミングを作υ、リフレッシュ回路5によってダ
イナミックRAM Jをリフレッシュする。In this case, in the conventional memory device, the power supply switching means 3 switches to the battery 8, and the battery 8 supplies power to the dynamic RAM 4, the refresh circuit 5, and the oscillation circuit 6. At this time, the oscillation circuit 8 generates a refresh timing υ, and the refresh circuit 5 refreshes the dynamic RAM J.
従来のメモリ装置は、以上のように構成されていたので
、制御電源9が切れてバッチIJ−8K切換えた場合、
バッテリー8の端子電圧は、第3図に示すように、放電
初期には高く、このため不要に多くの電流をダイナミッ
クRAM 4や他の回路が消費し、時間の経過と共に低
下し、ダイナミックRAM 4の記憶内容を保持できな
くなったところでバッテリー8の寿命となるため、バッ
テリーバックアップ時間が短かいという問題点があった
。Since the conventional memory device is configured as described above, when the control power supply 9 is cut off and the batch IJ-8K is switched,
As shown in FIG. 3, the terminal voltage of the battery 8 is high at the beginning of discharge, and therefore the dynamic RAM 4 and other circuits consume an unnecessarily large amount of current. Since the battery 8 reaches the end of its lifespan when it is no longer able to retain the memory contents, there is a problem that the battery backup time is short.
この発明は上記の問題点を解消するためになされたもの
で、バッテリーバックアップ時に不必要な消費電流を減
少させ、バッテリーバックアップ時間を長くすることが
できるメモリ装置を得ることを目的とする。The present invention has been made to solve the above problems, and an object of the present invention is to provide a memory device that can reduce unnecessary current consumption during battery backup and extend battery backup time.
〔問題点を解決するための手段〕
この発明に係るメモリ装置は、バッテリ一端子電圧をバ
ッテリー電圧検出手段で検出し、検出されたバッテリ一
端子電圧がパツ、クアツプに必要外電圧より高いときに
は給電電圧を低くシ、低くなったときには給電電圧を高
くするようにバッテリー電圧制御手段で制御するように
したものでおる。[Means for Solving the Problems] The memory device according to the present invention detects the voltage at one terminal of the battery with a battery voltage detection means, and when the detected voltage at one terminal of the battery is higher than the unnecessary voltage for the parts and the quads, the memory device starts supplying power to the parts and quads. The battery voltage control means controls the supply voltage to a low level, and when it becomes low, increases the power supply voltage.
この発明における、バッテリ電圧検出手段と、バッテリ
ー電圧制御手段によって、バックアップ電圧を制御し、
消費電流を少なくすることによってバッテリーの寿命を
延ばす。In this invention, the backup voltage is controlled by the battery voltage detection means and the battery voltage control means,
Extend battery life by reducing current consumption.
以下、この発明の一実施例を図について説明する。第1
図において3〜8は前述した従来のメモリ装置と同−又
は対応するものである。1はバッテリー8の電圧を検出
するバッテリー電圧検出手段、2はバッテリー電圧検出
手段1で検出されたバッテリー電圧がバックアップに必
要な気圧より高い時は給電電圧を低くし且つバックアッ
プに必要な電圧より低くなった時は給電電圧を高くする
ように制御するバッテリー電圧制御手段である。An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, numerals 3 to 8 are the same as or correspond to the conventional memory device described above. 1 is a battery voltage detecting means for detecting the voltage of the battery 8; 2 is a battery voltage detecting means that, when the battery voltage detected by the battery voltage detecting means 1 is higher than the atmospheric pressure required for backup, lowers the power supply voltage and lowers the voltage required for backup; This is a battery voltage control means that controls the power supply voltage to be increased when the voltage is exceeded.
上記のように構成されたメ毛り装置においては、制御電
源9が切れた場合、ダイナミックRAM4の記憶内容を
保持するため、電源切換手段3によってバッテリー8に
切換える。この時、バッテリー電圧検出手段1によって
バッテリ一端子電圧を検出し、このバッテリ一端子電圧
がバックアップに必要な電圧より十分高い時には、バッ
テリー電圧制御手段2によってバックアップ電圧を低く
し、消費電流を少なくする。次に、バッテリー8の消費
によりバッテリ一端子電圧が低下した時には、バッテリ
ー電圧制御手段2によってバックアップ電圧を高くして
ダイナミックRAM 4のバックアップを続ける。この
ためバッテリ一端子電圧の特性は第3図のように、バッ
テリー8の使用初期は従来のメモリ装置の場合と比較し
てバックアップ電圧が低く、バッテリー8の消費により
バッテリ一端子電圧が低下した時にはバッテリー電圧制
御手段2によタバックアップ電圧を高くするので、バッ
テリーバックアップ時間が第3図に示すように従来のメ
モリ装置と比較して長くなる。In the hair removal device configured as described above, when the control power source 9 is cut off, the power source switching means 3 switches to the battery 8 in order to maintain the stored contents of the dynamic RAM 4. At this time, the voltage at one terminal of the battery is detected by the battery voltage detection means 1, and when the voltage at one terminal of the battery is sufficiently higher than the voltage required for backup, the backup voltage is lowered by the battery voltage control means 2 to reduce current consumption. . Next, when the voltage at one terminal of the battery decreases due to consumption of the battery 8, the backup voltage is increased by the battery voltage control means 2 to continue backing up the dynamic RAM 4. Therefore, the characteristics of the voltage at one terminal of the battery are as shown in Fig. 3. When the battery 8 is initially used, the backup voltage is lower than in the case of conventional memory devices, and when the voltage at one terminal of the battery decreases due to consumption of the battery 8, the voltage at one terminal of the battery decreases. Since the battery backup voltage is increased by the battery voltage control means 2, the battery backup time is longer than that of the conventional memory device, as shown in FIG.
以上のようにこの発明によれば、バッテリー電圧検出手
段によってバッテリ一端子電圧を検出し、検出されたバ
ッテリ一端子電圧がバックアップに必要な電圧より高い
ときKは給電電圧を低くし、低くなった時には給電電圧
を高くするようにバッテリー電圧制御手段で制御するよ
うに構成したので、ダイナミックRAM等の回路の消費
電R,t−少なくシ、バッテリー寿命を長くシ、バック
アップ時間を長くすることができる効果がある。As described above, according to the present invention, the voltage at one terminal of the battery is detected by the battery voltage detection means, and when the detected voltage at one terminal of the battery is higher than the voltage required for backup, K lowers the power supply voltage and becomes lower. Since the power supply voltage is sometimes controlled by the battery voltage control means to increase the power supply voltage, it is possible to reduce power consumption R,t of circuits such as dynamic RAM, extend battery life, and extend backup time. effective.
第1図はこの発明の一実施例によるメモリ装置を示すブ
ロック図、第2図は従来のメモリ装置を示すブロック図
、第3図はこの発明と従来のメモリ装置のバックアップ
時間とバッテリ一端子電圧特性の比較図である。
図において、1はバッテリー電圧検出手段、2はバッテ
リー電圧制御手段、3は電源切換手段、4はダイナミッ
クRAM、5はリフレッシュ回路。
6は発振回路、7はCPU、8はバッテリー、9は制御
電源である。
なお、図中、同一符号は同一、又は相当部分を示す。FIG. 1 is a block diagram showing a memory device according to an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional memory device, and FIG. 3 is a backup time and battery terminal voltage of the present invention and a conventional memory device. It is a comparison diagram of characteristics. In the figure, 1 is a battery voltage detection means, 2 is a battery voltage control means, 3 is a power supply switching means, 4 is a dynamic RAM, and 5 is a refresh circuit. 6 is an oscillation circuit, 7 is a CPU, 8 is a battery, and 9 is a control power source. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
のリフレッシュ回路により制御されるダイナミックRA
Mと、バッテリーと、制御電源断時に前記バッテリーの
バックアップに切換える電源切換手段とを備えたメモリ
装置において、前記バッテリーの電圧を検出するバッテ
リー電圧検出手段と、前記バッテリー電圧検出手段で検
出されたバッテリー電圧がバックアップに必要な電圧よ
り高い時は給電電圧を低くし且つバックアップに必要な
電圧より低くなつた時は給電電圧を高くするように制御
するバッテリー電圧制御手段とを設けたことを特徴とす
るメモリ装置。An oscillation circuit, a refresh circuit connected to it, and a dynamic RA controlled by this refresh circuit.
M, a battery, and a power supply switching means for switching to backup of the battery when the control power supply is turned off, the battery voltage detection means for detecting the voltage of the battery, and the battery detected by the battery voltage detection means. The battery voltage control means is provided to control the power supply voltage to be lowered when the voltage is higher than the voltage required for backup, and to increase the power supply voltage when the voltage is lower than the voltage required for backup. memory device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60113482A JPS61271695A (en) | 1985-05-27 | 1985-05-27 | Memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60113482A JPS61271695A (en) | 1985-05-27 | 1985-05-27 | Memory device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61271695A true JPS61271695A (en) | 1986-12-01 |
Family
ID=14613401
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60113482A Pending JPS61271695A (en) | 1985-05-27 | 1985-05-27 | Memory device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61271695A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7085946B2 (en) * | 2002-04-05 | 2006-08-01 | Mitsubishi Denki Kabushiki Kaisha | Backup memory control unit with reduced current consumption having normal self-refresh and unsettled modes of operation |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6045997A (en) * | 1983-08-24 | 1985-03-12 | Hitachi Ltd | Semiconductor device |
JPS61148700A (en) * | 1984-12-24 | 1986-07-07 | Hitachi Ltd | Semiconductor device |
-
1985
- 1985-05-27 JP JP60113482A patent/JPS61271695A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6045997A (en) * | 1983-08-24 | 1985-03-12 | Hitachi Ltd | Semiconductor device |
JPS61148700A (en) * | 1984-12-24 | 1986-07-07 | Hitachi Ltd | Semiconductor device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7085946B2 (en) * | 2002-04-05 | 2006-08-01 | Mitsubishi Denki Kabushiki Kaisha | Backup memory control unit with reduced current consumption having normal self-refresh and unsettled modes of operation |
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