JPS61148700A - Semiconductor device - Google Patents

Abstract

PURPOSE:To operate a memory LSI stably by providing a reference voltage VL generating circuit in a chip and controlling a change of a voltage value of this VL below a constant value even when a power source voltage is changed. CONSTITUTION:A circuit 8 producing a voltage VL of a reference of an internal operation is disposed. Even when an operation condition from an ordinary operation to an information maintaining operation or from the information maintaining operation to the ordinary operation is changed or a power source voltage from VEXT to VBT or from VBT to VEXT is changed, a change of the VL being the reference of the internal operation is restricted to a range not so as to generate an erroneous operation and the erroneous operation due to a change of the power source voltage is prevented. Thereby, even if the power source voltage is changed by a battery back up operation, a memory LSI stably operating can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to improvements in semiconductor memory devices, and particularly to a semiconductor memory device suitable for battery backup operation.

[Background of the invention]

In a semiconductor device having a so-called information storage function, typified by a memory, in an electronic device using this as a component, in a so-called power outage state when a power supply for driving the semiconductor device or the like fails, the information stored in the information storage function part is It is generally desired that the information stored in the system does not disappear. For this purpose, a battery is installed in the electronic device in order to satisfy both the electrical characteristics during normal operation and the information retention characteristics during a power outage, and this battery supplies operating power during the above power outage. A so-called battery backup method is adopted.

In the battery backup method described above, in order to extend the battery-powered operation time, the semiconductor device must consume as little power as possible in the information retention state (hereinafter referred to simply as the information retention state). There is. This low power consumption characteristic of the information retention state is useful not only when using the battery backup method in the event of a power outage, but also when it is necessary to store only information stably over a long period of time, or when using small, easily portable electronic devices. It is also very convenient to carry the device around with only the necessary information stored at low consumption and perform various processing based on the stored information at any location.

A known example of reducing power consumption in the information holding state is disclosed in Japanese Patent Application Laid-Open No. 58-73096, but in order to perform effective battery back amplifier operation, it is necessary to further reduce power consumption. The inventors proposed a memory system suitable for battery backup operation that operates with extremely low power consumption in Japanese Patent Application No. 58-153308.

Figure 1 (A) is a diagram showing an overview of the system. It has two operating modes: normal operation and information retention operation. In the latter mode, the operating voltage is lowered to reduce power consumption, and battery backup is performed. This is an example where the operation is possible. In the same figure, 1 is memo I
It is a JLSI chip.

2 is a memory cell array in which memory cells are arranged two-dimensionally in rows and columns, and a circuit section that drives it; 3 is a power supply wiring, and Vw
Nt indicates the voltage value, here externally applied voltage Vtx
r is applied. That is, Vtxr=VxNt. 4 is an input/output signal wiring. 5 is a battery, VIT
is its voltage value. In the information retention state, the entire chip operates using this battery as a power source. 6 is a diode that prevents current from flowing backward from 3 to 5 during normal operation. 1
00 is a voltage change detection circuit that detects the transition from the normal operating state to the information retention state, and the result is 101.
The voltage change detection circuit is provided inside the LSI chip, but an input terminal as shown by the broken line 7 in the same figure is provided, and the memo IJ It is also possible to detect a power supply abnormality such as a power outage in an electronic device that uses LSI, and input the detection result as a signal.
), for example, an external power outage (power outage due to power source failure, power outage caused by intentionally turning off the power, etc.)
etc., the voltage value VIN〒=Vzχ te is Va
The voltage gradually decreases toward the voltage value of t. This voltage is set to a predetermined constant reference voltage, for example, V m c t
When the voltage becomes lower (time t1), the voltage change detection circuit 1
00 outputs signals such as φc (changes from "0" to "'l") and φmc (changes from l" to "0") to its output 101. In other words, 1oo causes the operating state to change to normal. In response to the signal 101, the circuit unit 2 switches the operation to the information retention state and reduces power consumption to the minimum necessary for information retention. .

3 voltage V I N t further decreases from time t1, but v! When the voltage of 1.1 is reached, diode 6 (assuming the forward voltage is Ov) is turned on, that is, power is also supplied to 5, the voltage of 3 stops at Vat, and then this 1.
The information retention operation is continued by pressure. On the other hand, when the power outage returns or the power is turned on, the voltage Vr+vt of 3 increases,
When it becomes higher than a certain reference voltage Vac 2, φMe, φ
11c, etc., respectively, are restored to their original normal operating states. This method returns the circuit section 2 to its original normal operating state.

Now, in a DRAM that lowers the operating voltage to reduce power consumption and performs battery backup, the voltage change time when switching from normal operation to battery backup operation, or from battery backup operation to normal operation. If the speed becomes larger or faster, the stored charge in the memory cell may disappear or the internal circuit may malfunction.

The details will be explained below. FIG. 2(A) shows the main circuit section of the DRAM. MC is a memory cell that stores information, and here MOS transistor Qs
and storage capacity tclI. A so-called 1 transistor/register memory cell is illustrated. DMC is a dummy cell that generates a reference voltage, YG is a data line pair selected by the Y decoder, a gate circuit connects D to the I10 line, and Pc
These are a precharge circuit that precharges the beams and D, and an amplifier circuit that differentially amplifies the minute signals read out on the SA beams and D. In a read operation in such a circuit, when the word line φW is selected and the voltage becomes high, a minute signal is read out onto the data line corresponding to the storage charge accumulated in the storage capacitor Cs.

At the same time, the dummy word line φwn is also selected and the reference minute signal is read onto the data #iD. Then SA
The drive signal φCI of is input, and the minute signal on D is differentially amplified. Next, the signal on the data line D is outputted to the I10 line through the gate circuit YG composed of Qs and Qv, and is finally taken out to the outside. Now, in a DRAM that performs such an operation, the memory capacity Ji Cs
The influence of the voltage change described above will be explained for two methods: one in which one end Vp of the electrode forming the electrode is connected to the externally applied voltage 3, and the other in which it is grounded to earth. The figure (B) shows Vp
is connected to the externally applied power source 3, the battery backup operating voltage Vat to the normal operating voltage V z x
This figure shows the main waveform when subjected to a ΔV voltage change of t. As shown in the figure, the stored information of the memory cell is 0''
(Here, when the node voltage Vs of the memory cell is low (~O
V) is *0*), depending on the value of ΔV,
Malfunction may occur. In other words, the node [voltage V5 (OV) of the memory cell written with the battery backup operating voltage V m t is caused by the voltage change of the electrode VP forming the storage capacitor Cs]. As shown in the lower part of the figure, the capacitance due to CB It rises due to combination. On the other hand, the node voltage Vog of the dummy cell that generates the reference signal voltage is the transistor Q7.
Because it is grounded, it is not affected by voltage changes. After that, when a read operation is performed at the power supply voltage value Vzxt, the effective signal voltage V, t, (
O) is V, I-(0) = V-Iw (DM) V, tg
(M)・・・・・・・・・(1) It becomes. Here, °v-tt (M is the read signal voltage from the memory cell, y, t, (DM) is the reference signal voltage from the dummy cell, and is expressed by the 9th order equation.

From equations (1), (2), and (8)...
...(4) Assuming that C8<CD, equation (4) becomes. If this value is negative, the amplification circuit SA determines it to be 10'' and amplifies it, but depending on the value of ΔV, V-It(0) may be positive, and as shown in FIG. ``'' is reversed to 11'' and malfunctions.

FIG. 2(C) shows the waveform of the main part of the field when vP is connected to ground. In this case, since there is no voltage change in Vp, there will be no malfunction such as the above-mentioned inversion of 0'' to 1'', but voltage vlI? The information written in 9″′1″ is the voltage value V z X ? In this case, a defect becomes "0" information. In other words, the effective read signal voltage V-+ in this case
t (1) is v, +, (i) = v, tg (DM) −
v, It (M) -----------(6).

When calculated from equations (6), (7), and (8) in the same way as equation (5), if this value is positive, it will be '1'', but depending on the value of Δ■, it will be negative, and the As shown in Figure 2 (C), 11'' is reversed to 10'', causing a malfunction.

All of the above are malfunctions that occur when the power supply voltage increases, but when the power supply voltage decreases, that is, from V z x r to V
Malfunctions or inconveniences also occur when switching to mr.

For example, in FIG. 2, in a cell with information '0', the node voltage Vg becomes negative '1' due to the combination with Vp, and the MOS transistor QII is turned on.
Current flows from the data line to C8. Therefore, information 9
If there are a large number of 0" cells, problems such as the potential of the data line will drop abnormally will occur.Also, even if the power supply voltage drops in the circuit of the entire memory chip, the The operating voltage at a high power supply voltage remains as a charge, causing problems such as malfunction.

[Purpose of the invention]

Therefore, an object of the present invention is to provide a dynamic memory that performs battery backup by lowering the power supply voltage, and which operates stably even when the power supply voltage decreases or increases.

[Summary of the invention]

In order to achieve the above object, the present invention provides a circuit that generates a reference voltage that serves as a reference for circuit operation within a chip, and controls the output characteristics of the circuit, so that even if externally applied voltage fluctuates, the inside of the chip remains unchanged. The fluctuation of the operating voltage of Memo IJ
The above problem is solved by keeping the LSI below the allowable value for normal operation.

[Embodiments of the invention]

The details of the present invention will be explained below using examples.

FIG. 3 is a diagram showing the basic concept of the present invention.

In the figure, reference numeral 8 denotes a circuit that generates 1 voltage VL, which serves as a reference for internal operation. In other respects, parts with the same reference numerals as those in FIG. 1 are the same or equivalent parts. In the present invention, the operating state changes from normal operation to information retention operation or from information retention operation to normal operation, and the power supply voltage changes from Vzxt to vl! ,
Alternatively, even when changing from Vat to Vxt, the change in vL, which is the standard for internal operation, is suppressed to a range that does not cause malfunctions as explained in equations (5), (9), etc., and malfunctions due to fluctuations in power supply voltage are suppressed. prevent. This makes it possible to realize a memory LSI that operates stably even when the power supply voltage changes due to battery backup operation.

FIG. 4 is an embodiment showing an example of the characteristics of VL, in which the voltage Vxut of 3 is shown on the horizontal axis and VL is shown on the vertical axis.

In this example, V! *The value of ↑ changes from Vzxt to Vat, e or from Vat to V due to the transition from normal operation to information retention operation or from information retention operation to normal operation.
When the value changes to xr, the value of vL changes from V L l to V t, o or from VLO to VLI. As a result, the amount of change ΔVr*t in Vrst is reduced to ΔVr*t.
VL, thereby preventing malfunctions that have been a problem with the prior art. Specifically, for example, in order to prevent the malfunction described in equation (5), Vgxte in equation (5) should be changed to V L I
% Replace ΔV with ΔvL, ......C
It may be set to 0 or less. To this end, also regarding the malfunction explained using equation (9), the following can be obtained in the same manner as above. That is, as described above, as can be seen from the above explanation, the gist of the present invention is to maintain the relationship between vLl and vLo constant and prevent malfunctions when transitioning to battery backup operation or transitioning to normal operating state. The characteristics of the section from VLO to vLl can take on various characteristics within the range of ΔvL as described above. Figure 5 shows some examples, including (A), (B), (C), and (
As shown in D), various characteristics can be obtained within the range of ΔVL. Further, the value of VLOe VLI can be arbitrarily set within the range of ΔVt determined from the conditions as described above, and in some cases, it can also be set such that VLO>vt,t. VLO, Vt,1 and Vt
The relationship between N↑ is not particularly limited, and the values of vLO and VLI are
It is also possible to set it larger than tNt.

FIG. 3(B) shows the operating state detection circuit 10 of FIG. 3(A).
This is a concrete example of 0, and the basic circuit configuration is included.

In the same figure, Q141 to Q14111QI51 each have a threshold voltage of Vt+4+ -Vt+4a + Vtts+
OMOS) is a 7 register. Here, Q14
1 to Q+4m constitute a Vxwt conversion circuit,
150, outputs VsNt'=VtNt-ΣVt+4tm1. Q+s+tRt□ constitutes a discriminator circuit, which itself has a threshold value that serves as a certain standard,
This is a threshold circuit that discriminates whether the input voltage is high or low. The threshold value Vtc of this circuit is Q
s s t threshold voltage Vttst and 几, □ and Qi
It is determined by the ratio of the on-resistance of st, and can be set arbitrarily, but if the R++stO value is set sufficiently larger than the on-resistance of Qist, it is possible to set Vta=V tr s r. This case will be explained here for simplicity.

The operation of this embodiment will be explained using FIG.

As V I N t gradually decreases, the voltage of 150 becomes V
otr'=Vxwt-ΣVt+4t<Vt+st1
In other words, when (time tl) Qist is turned off and the output φ
1c changes from 0'' to '1''. As a result, it is possible to detect a change in the voltage of Vxwt in the same manner as in the embodiments already described, and to detect that the operation has shifted to the information holding state.

In this example as well, by adjusting the threshold voltage or the number of stages of the MOS transistors used,
The isometric VmcO value of C) can be set arbitrarily. Also,
According to this embodiment, Q s s + is turned off when Vxwt<Vts++ ΣV141 mg, which is extremely effective in reducing power consumption in the information retention state, which is the purpose of the present invention.

Is the 150 in the same figure CB) the VIN? This is a discharge resistor for preventing charges from being accumulated in nodes such as 150 when the voltage changes from a high state to a low state. This resistance value is ■! It is necessary to choose according to the rate of change of
If the rate of change is slow, it is possible to use a parasitic riff resistance between the node 150 and the 3i substrate as a substitute; in that case, 1 is not necessary. Note that R15° here.

R15+ can also be replaced by the on-resistance of a MOS transistor.

It is disclosed in FIG.

FIG. 4 shows the schematic characteristics of Vr and V I N t.

The characteristics shown in the figure are the results selected to be suitable for the reliability test of LSI chips, as shown in the above reference or Japanese Patent Application Nos. 56-168698 and 57-220083.
This is as stated in the issue.

Kokote, Vst6D value 1'j, Qth g ~ QIsz + QI
It is determined by the point at which tz turns off, that is, the sum of the threshold voltages of each MOS transistor. Generalizing this relationship in the same way as in Figure 3 (B), here, Vtlγ is the threshold voltage of Q Iy x, Vy
Metobi is VtelB Agriculture ~V? 1 m1 (not shown) threshold to +- voltage. '- Nao, Figure 3 Nioite, V a > V to z +
As stated in the above reference, it is necessary to satisfy the conditions of V L (v? is the threshold voltage of the MOS transistor that responds to each subscript), and if these conditions are satisfied, VxNt In the state of <Vsc, that is, in the information holding state, a predetermined voltage is output, respectively. It should be noted that in this state, VL≧Vtptt as shown in FIG.

Real m? In IJ, when Qxsg (1) and #sc transition to a low voltage state (information retention state), the entire circuit is disconnected from the ground, preventing current from flowing from VxNt to ground, and reducing power consumption. ing.

According to the above embodiment, even if the externally applied voltage 3 fluctuates greatly, the change value of the internal operating voltage can be kept below the allowable range for normal operation of the LSI memory. It becomes possible to realize a memory LSI that can operate with ultra-low power consumption by lowering the operating voltage during battery backup operation.

FIG. 6 shows another embodiment. In this embodiment, only the circuit section 2b, such as a memory array, which is likely to malfunction due to fluctuations in the power supply voltage, is operated by VL, and the other circuit section 2a, which is unlikely to malfunction even when the power supply voltage fluctuates, is operated by VL. Operates directly with external power supply voltage.

According to this embodiment, 8 only needs to drive the circuit section 2b, and the load on 8 can be significantly reduced, making design easier. This makes it easier to lower the operating voltage during battery backup operation.

FIG. 7(A) shows a more specific embodiment of the present invention, in which one end of the electrode forming the storage capacitor Cs is connected to the external power source 3.
Notes connected to! This is an example in which the present invention is applied to jLsI. A reference voltage VL is applied to the electrode Vp forming the storage capacitance Cm.
operate according to. A voltage limiter circuit 14 is added to reduce the voltage change value that the memory cell receives to the change value ΔVL of VL. This operation will be explained using FIG.

In addition, here Vl? = VLO is explained as an example. As shown in the figure, when the externally applied power source 3 changes by Δ゛■■ from Vat to Vz x r, the change value of the internal reference voltage VL can be reduced to ΔVL from Vt, 6 to VL+. In this state, when a ``0'' read operation is performed as in FIG. It is possible to eliminate malfunctions in which the value is reversed to 1''.

According to this embodiment, one end of the electrode forming the storage capacitor C1 is connected to the external power supply 3. In memory LSI,
It becomes possible to prevent the malfunction that occurs when the voltage increases as described above.

For the sake of simplicity, here we will explain the case where the output of 14 is exactly the same as VL, but if they are not the same, then if VL is determined so that the output of 14 becomes the desired value, Needless to say, it's a good thing.

This also applies to the following examples.

FIG. 8(A) shows an embodiment in which the present invention is applied to a memo IJL8I in which one end of an electrode forming a storage capacitor Cs is grounded. In this embodiment, the voltage value of the externally applied power supply 3 is the normal operating voltage MIX? From battery backup voltage Vmt
ni or vl? Even if it changes from Vzxt to Vzxt, the internal operating voltage (in this case, the data line).

In order to keep the change in the precharge voltage (of D) below a permissible value, the precharge power supply vDp operates in accordance with the reference voltage VL. A voltage limiter circuit 15 is added. This operation will be explained using the main waveforms shown in FIG. Similarly to FIG. 7, the externally applied power supply 3 converts the change value Δ■ from Vat to Vgxy into a change value Δv of the data line precharge voltage by the voltage limiter circuit 15 operating according to the reference voltage VL.
It has been reduced to L. This is the battery backup voltage v3
Precharge voltage at 〒 (memory cell write voltage)
By reducing the difference between the precharge voltage at the normal operating voltage V and the precharge voltage to ΔVs, '1'' as shown in Fig. 1(C) becomes O''
This prevents malfunctions such as reversal. In other words, V z x from 711th block? (by '1'' readout when the signal voltage changes to '1') (The amount of decrease in the signal voltage V-+g(1) of the right side data line is limited by ΔVL as shown in the figure, so as shown in Figure 1 (C) It is possible to prevent malfunctions in which '1'' is reversed to 0''.

Figure 9 shows the f-line precharge voltage V as shown in Figure 8.
This is an example in which a voltage limiter circuit 16 is added to the data line precharge signal φp' in order to control it using the voltage value of t. In this embodiment, the voltages of φ and / are set to VL so that they are higher by the threshold voltage of the required data line precharge (voltage than MOS) transistors Qs and Q4.
Needless to say, it is necessary to determine the O value. Here, for simplicity, it is sufficient to assume that the precharge voltage of the data line is equal to VL as in each of the embodiments already described, and that the threshold voltage is Ov. Malfunctions in which "" is reversed to "0" can be eliminated.

According to the embodiments shown in FIGS. 8 and 9, malfunctions due to fluctuations in the power supply voltage can be prevented even in the memory IJLSI in which one end of the electrode forming the storage capacitor C8 is grounded.

It has been described above that malfunctions of a part of the memory array caused by changes in the power supply voltage can be prevented by keeping the value of ΔVt below a certain certain value according to the embodiments shown in FIGS. 7 to 9. The allowable value of ΔVL in this case is given by 2〇〇, αυ in the case of FIG. 7, and is given by 2〇a, (1:l) in the cases of FIGS. 8 and 9.

Note that in an actual memory LSI, Cm.

Needless to say, it is determined by taking into consideration the design value of the CDs and their manufacturing variations, or the sensitivity and noise of the differential amplifier circuit SA.

〔Effect of the invention〕

According to the present invention, a dynamic RAM that performs battery backup operation (information retention operation) by lowering the power supply voltage.
, a reference voltage VL generation circuit is provided inside the chip,
Even if the power supply voltage changes, the memory LSI can be operated stably by keeping the change in the voltage value of VL below a certain value. This enables operation with battery backup in DB and AM.

[Brief explanation of drawings]

Figures 1 and 2 are diagrams explaining the prior art, Figures 3 to 5 are diagrams explaining the present invention in detail, and Figures 6 to 7 are diagrams explaining other embodiments of the present invention. FIG. 8 is a diagram illustrating another example of the present invention, Q-9, and FIG. 9 is a diagram illustrating still another embodiment of the present invention. l...chip, 2...memory cell array, 3...
Power line, Ku8) $tN5 Chi 2 figure (A) ¥20 (B) Rod 2 evil CC) Rod 3 ward (Hano) ← 3 Foot opening (8) (C) Sai 3 figure (E)) Whisper 4 figure Kaya Figure 7 (A) Deaf delta concave (A) Figure 78 (8) Figure 9

Claims (1)

[Claims] 1. Two or more operating modes operating with different power supply voltages;
The device is characterized by comprising a switching means for the operation mode and a voltage converting means for converting the power supply voltage to another internal voltage within the chip, and at least a part of the circuits within the chip operate based on the internal voltage. A semiconductor device characterized in that a variation range of the internal voltage in the plurality of operation modes is equal to or smaller than a variation range of the power supply voltage. 2. The semiconductor device is a memory device constituted by a memory cell consisting of a capacitor for storing information charges and a MOS transistor for switching, and the operating voltage at one end or terminal of the capacitor is based on the internal operating voltage. 2. The semiconductor device according to claim 1, wherein the semiconductor device operates as follows. 3. Is the range of change of the internal voltage equal to the range that does not exceed the absolute value of the negative voltage of the highest possible voltage of the internal voltage?
3. The semiconductor device according to claim 2, wherein the semiconductor device is small.