JPS61271688A - Bipolar memory - Google Patents

Abstract

PURPOSE:To reduce remarkably power consumption without losing the high speed performance of access time by detecting the change in a word address signal to operates word line discharge circuit for a prescribed period. CONSTITUTION:A word address signal and another word address signal via a delay circuit 21 of a pulse generating circuit 18 of a word address signal detection circuit 17 are processed by an exclusive OR circuit 18 and the change in the word address signal is detected, then a pulse having width corresponding to a delay time of the circuit 21 is outputted. The discharge circuit current source of the word line discharge circuit 15 is controlled by the pulse and the word address signal is detected, then the circuit is operated for a prescribed period only to discharge word lines 7, 8. Thus, the transient response of the word lines 7, 8 is performed surely at high speed so as to reduce remarkably the power consumption of the bipolar memory without losing high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a bipolar memory, particularly to a word line discharge circuit therein and its control.

Conventional technology FIG. 3 shows an example of the configuration of a conventional bipolar memory.

In FIG. 3, 1 is the word address signal X o =
X n is input word decoder, 2 is word decoder
Driver (WD), 3 is bit address signal Yo-
Ys is the input bit decoder, 4 is the bit driver <80). In addition, 5 is a write/read circuit, 6 is a memory cell (MC), and 7.8 is a first
word line (We), second (1) '7-do m (We>
, 9.10 are the first bit line (B) and the second bit line (B), respectively. Furthermore, a storage holding current source (iH) 11 of the memory cell 6 is connected to each second word line 8 .

Reference numeral 12 denotes a word line discharge circuit, which is connected from the second word line 8 to a discharge circuit current source (ip) 14 via a diode (D) 13, respectively.

In the bipolar memory shown in FIG. 3, the word decoder 1 controls the voltage of only one selected word line 7 to be at HIGH level, and all others to be at LOW level.

Here, a large number of memory cells are connected to the word line 7, and a large capacitance is hanging therein. In addition, since the voltage amplitude of the word line 7 is large, the transient response of the word line 7 is considerably slow. Therefore, in order to avoid multiple selection of the word line 7, it is necessary to quickly lower the potential of the word line during the transient response transition from the selected state to the non-selected state, and as shown in FIG. It is necessary to add a discharge circuit 12.

(For example, Hideaki Ikoma, Akira Ichise [Bipolar integrated circuit]
,〈1980.12.1), Kindai Kagakusha, P137
~P 142).

Problems to be Solved by the Invention As described above, in the conventional circuit, a word line discharge circuit 12 is added in order to speed up the word line transient response and shorten the access time.

Here, since a large capacitance is hanging on the word line,
The discharge current io for speeding up the transient response of the word line requires a large current. In the conventional circuit, the discharge circuit 12 of the word line discharges a large discharge current i from the word line having the highest potential among the second words 108.

is always drawn lυ, and even when the word line is in a stable state other than waiting for a transient response, the discharge W1 current io is always drawn from the word line in the selected state.

As described above, in the conventional bipolar memory, a large amount of discharge circuit current is consumed in order to speed up the access time.

The present invention solves these problems and
It is an object of the present invention to provide a word line discharging circuit for a bipolar memory that can simultaneously realize faster time and lower power consumption.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention detects changes in the word address signal and generates a pulse signal for a certain period of time, and only during the valid period of 15 J of this pulse signal, the word line is activated. This is to operate the discharge circuit.

Operation The present invention has the above-described configuration, so that only during a transient response when the word address signal changes and the selected state of the word line changes,
Since the word line discharge circuit is operated, the transient response speed is increased, and the current source of the discharge circuit is turned off in a stable state.
(or decrease), it becomes possible to reduce power consumption.

EXAMPLE An example of the present invention will be described below based on the drawings. 1st
The figure is a block diagram showing an embodiment of the bipolar memory of the present invention, and blocks that are the same as those in FIG. 3 are given the same numbers. In FIG. 1, 1 is a word decoder to which a word address signal Xo''Xn is input, 2 is a word driver (WD>), 3 is a bit decoder to which bit address signals Yo to Ym are input, and 4 is a bit・
This is a driver (BD). Further, 5 is a write/read circuit, 6 is a memory cell (MO), 7.8 is a first word line (We), a second word line (We>, 9), respectively.
．． 10 are the first bit line (B) and the second bit line (B), respectively, and 11 is the memory holding current source (!n) of the memory cell.
It is.

15 is a discharge circuit for the word line, and the second word ra8
are connected to a discharge circuit current source (i(,') 16 through a diode (D) 13, respectively. Here, the discharge circuit current source 16 is set to 0N by the output signal of the word address signal change detection circuit 17. -OFF (or increase/decrease in current value) is controlled.This word address signal change detection circuit 17 is ORed with (n+1) pulse generation circuits 18.
The pulse generation circuit 18 is composed of a gate 19 and a first delay circuit 20, and the pulse generation circuit 18 is composed of a second delay circuit 21 and an EX-OR gate 2.
It is composed of 2.

FIG. 2 shows a waveform diagram of essential parts of the bipolar memory of the present invention shown in FIG. Figure 2 (a) shows the changed word
This is an address signal, and (b) is a signal obtained by delaying the signal in (a) by T2 by the second delay circuit 21 in FIG. The EX-OR gate 22 has (a > (b)
Since this signal is input, a pulse signal (C) with a pulse width T2 is generated. Therefore, the pulse generation circuit 1 in FIG.
8, it is possible to detect changes in word address signals Xo to X, respectively. That is, each pulse generation circuit 1
The output signal (C) of 8 is input to the first delay circuit 20 via the OR gate 19 and becomes an output signal delayed by T1. This is the output signal of the change detection circuit 17 shown in FIG. 2(d). This signal (d>) causes the word line discharge circuit 15 described above to operate.

FIG. 2(e) is a response waveform of the word line, and shows how the word line responds with a delay due to the word decoder 1 and word driver 2 after the word address signal Xo=Xn is input. ing. Here, the output signal @(
If the pulse width T2 and delay time T1 in d) are designed to appropriate values, it becomes possible to operate the word line discharge circuit only during the word line transient response. Here, the delay time T1 and pulse width T2 of the signal (d') are the first and second pulse widths, respectively.
It can be easily adjusted by the delay time of the delay circuit. Also,
The delay circuit can be configured by an inverter chain or the like.

That is, by detecting a change in the word address signal Xo=Xn, the word line discharge circuit 15 is operated only for the necessary time during a word line transient response, speeding up the word line transient response, and increasing the access speed. The time can be shortened, and at the same time, the power consumption can be significantly reduced by turning off or reducing the current source of the discharge circuit when the word line is in a stable state.

Since the conventional discharge circuit consumes a large amount of current, this amount more than offsets the increase in power consumption due to the word address signal change detection circuit added to realize the present invention.

Effects of the Invention According to the present invention, by simply adding a simple circuit, power consumption can be significantly reduced without sacrificing the fast access time of bipolar memory, which is extremely useful in practice. It is.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a bipolar memory according to an embodiment of the present invention, Fig. 2 is a waveform diagram of main parts of the bipolar memory shown in Fig. 1, and Fig. 3 is a block diagram of a conventional bipolar memory. be. 6...Memory cell, 7,8...Word line, 9,1o
...Bit line, 11...Memory cell memory retention current source, 15...Discharge circuit, 1G...Discharge circuit current source, 1
7... Word address signal change detection circuit, 18.
...Pulse generation circuit, 20...First delay circuit, 21
...PS in the second delay circuit

Claims (1)

[Claims] 1. The word line discharge circuit has a word line discharge circuit and a word address signal change detection circuit that detects a change in the word address signal and generates a pulse signal for a certain period of time; Bipolar memory that is controlled to operate only during periods when