JPS61271549A - Cache memory - Google Patents

Abstract

PURPOSE:To attain the miniaturization and, high-speed operation of a cache memory by providing an instruction address register consisting of high-order address which designates, a prescribed number of instructions as a group and a low-order address which designates each of these instructions of a group. CONSTITUTION:The instruction read out of an external storage device 11 is supplied to an execution unit via an external bus 15 and an access control part 13 and also stored in an entry corresponding to a cache memory part 3 designated by a low-order address 1a of an instruction address register together with '1' of V bits showing the validity. While high-order address 1b of another jumped address is stored in a page address register 7 and it is shown that the instruction of another page is stored in a memory part 3. Then the instructions of other pages are stored successively in the areas following the entry of the part 3 where the instructions of other page addresses are stored through a control part (not shown here). These instructions of other pages are supplied to the execution and carried out successively.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention preemptively stores instructions to be executed in a computer from a storage device, and when the currently executed instruction is completed, the next instruction is quickly executed. This invention relates to a cache memory supplied to a control unit.

[Technical Background and Problems of the Invention] In a computer, generally after the execution of one instruction is completely completed, the next instruction is taken out from the storage device and supplied to the control unit for execution. By reading and prefetching the next instruction from the storage device while an instruction is being executed, the processing time of the computer can be increased. In this case, a cache memory is used to prefetch and store not only one instruction but also a plurality of instructions as the next instruction.

A cache memory generally has a memory section, ie, a cache memory section, for storing, for example, 32 instructions as a plurality of instructions to be prefetched to be executed sequentially next, and a cache memory section that similarly stores 32 instructions corresponding to the cache memory section.
It has a tag memory section with memory locations. For example, 32 instructions stored in the cache memory section are specified by a lower address, for example, a 5-bit lower address of the address of the next instruction to be executed stored in the instruction address register. The address of the storage device that stores each instruction is divided into this lower address and the remaining upper address, and the tag memory section uses this upper address to correspond to each instruction stored in the cache memory section. I remember. This allows the upper address of each instruction stored in one of the cache memory units specified by the lower address to be known.

However, providing a tag memory section to store the upper address for each instruction stored in the cache memory section requires a fairly large memory capacity, so when integrated, it is difficult to compare. Although it occupies a large area and is also uneconomical, there is a problem in that it does not have enough functionality to justify the increased area and uneconomical nature.

To explain more specifically, if, for example, 32 instructions stored in the cache memory section are considered as one group as described above, and the unit of this one group of instructions is considered as one page, then the upper address of each The page will be specified, and the lower address will specify each instruction stored in each page. Therefore, the tag memory section stores a page corresponding to each instruction stored in the cache memory section, so that it is possible to know which page each instruction stored in the cache memory section belongs to. It has become.

However, since the instruction group stored in the cache memory section is generally a group of instructions on the same page, for example, 32 instructions, in this case, the tag memory section will all have the same page number. , that is, the same upper address is stored. In addition, when moving from one page to the next page, instructions are executed sequentially from the beginning of the next page, so the instructions in the cache memory section are stored sequentially, so the instructions for all pages are stored in the tag memory section. It may be considered that the same next page number is stored sequentially. In addition, when a jump command etc. is executed from the middle of a page and jumps to another page, different page numbers are stored sequentially from the jump command, and the page numbers after the jump command are sequentially the same number. is considered to be memorized. In this way, when moving to the next page or the page to which the page was jumped, and the instructions stored in the cache memory section are being sequentially updated, the process returns to the previous instruction part that has not been updated and remains in the cache memory section. In this case, it is necessary that the page of the previous instruction is indicated in the tag memory section, but the probability that processing will move to the previous instruction that has not been updated yet is Very few.

Therefore, it is not economical to provide a tag memory section for each of the 32 instructions in the cache memory section as described above, and it is difficult to provide a tag memory section for each of the 32 instructions in the cache memory section, for example, when the tag memory section is integrated into a microcomputer. This also occupies a large chip area, which poses a problem of increasing the cost of the microcomputer.

[Object of the Invention] This invention was made in view of the above, and its purpose is to eliminate the tag memory section to achieve economicalization, miniaturization, and high speed. The objective is to provide a cache memory that is

[Summary of the Invention] In order to achieve the above object, the present invention specifies a predetermined number of instructions as a group in order to specify the next instruction to be executed among instructions stored in a storage device in a computer. an instruction address register that stores an address consisting of an upper address and a lower address that specifies each of a group of instructions specified by the upper address; an upper address register that stores the upper address; A group of instructions specified by the stored high-order address is preempted and stored, and the stored 1
Each of the instructions in the group has a cache memory portion specified by a lower address stored in the instruction address register, an upper address stored in the upper address register, and an upper address stored in the instruction address register. Compare, and when both upper addresses match, specify one of the instructions in the cache memory section with the lower address stored in the instruction address register, read it out from the cache memory section, and output it, and when both upper addresses do not match. The gist of the present invention is to include a comparison control section that retrieves and outputs an instruction from a storage device according to an address stored in the instruction address register, and stores the retrieved instruction in the cache memory section.

[Invention Examples] Hereinafter, the present invention will be explained in detail using the drawings.

The figure is a circuit block diagram of a cache memory showing an embodiment of the present invention. In the figure, 1 is an instruction address register, and the address of the next instruction to be executed is set in this instruction address register 1 under the control of a control section (not shown). This instruction address register 1 is composed of, for example, 32 bits, and includes a lower address 1a consisting of 5 bits from the 3rd bit to the 7th bit, that is, an index part IX and 2 bits from the 8th bit to the 32nd bit.
Upper address 1b consisting of 5 bits, that is, tag part I
It is divided into PTAG and PTAG.

The instruction address register 1 is connected to an external storage device 11, which is a main storage device that stores instructions, via an access υ control unit 13 and an external bus 15, so that instructions are stored in the external storage device 11. It is now possible to retrieve commands.

Reference numeral 3 denotes a cache memory section that stores an instruction prefetched from the external storage device 11, and this cache memory section 3 includes an instruction word section 3a that stores a prefetched instruction word of, for example, 32 bits, and an instruction word section 3a that stores a prefetched instruction word of, for example, 32 bits. It is possible to store 32 entries of 33 bits consisting of 1 bit V bit 3b indicating the validity of the instruction, that is, 3
It has memory locations for storing two instruction words and the V bit, each of these 32 memory locations being designated by a lower address 1a of instruction address register 1. The V bit indicates whether the corresponding instruction is a valid instruction or not. When a new instruction is fetched into the cache memory section, the instruction has just been fetched and is valid, so the V bit indicates whether the corresponding instruction is a valid instruction or not. is “1”
”, meaning the instruction can be used.

Further, a program page address register 7 is provided corresponding to the cache memory section 3.

This page address register 7 is for storing the upper address of the instruction stored in the cache memory section 3, and is used to identify the upper address of the instruction stored in the cache memory section 3. It has become. As a result, each instruction stored in the cache memory section 3 has an upper address specified by the page address register 7 and a lower address 1 of the instruction address register 1.
This is the same as the address stored in the external storage device 11 specified by the lower address specified by a.

As mentioned above, the 3 data stored in the cache memory unit 3
If we consider two entries as one group and this one group of instructions as one page, the upper address specified in page address register 7 will specify each page, and the instructions in instruction address register 1 will be Lower address 1a
will specify each instruction stored in each page.

The page address register 7 is supplied with the upper address 1b of the instruction address register 1.

For example, if the one that is currently executing the command on the current page changes to the next page,
The first address of that page is instruction address register 1
The start address of the next page set in the instruction address register 1 is sent to the external storage table w1 via the access control unit 13 and the external bus 15.
11, the instruction is read from the external storage device 11, and this instruction is supplied to the instruction execution unit of the control section (not shown) via the external bus 15 and the access control section 13, and at the same time, this instruction is read out from the cache memory. stored in the department,
Also, the upper address of this instruction address, that is, the upper address 1 set in the instruction address register 1.
b is stored in the page address register 7 to designate the next page. As a result, the upper address indicating the next page is stored in the page address register, and the instructions for this page are stored in the cache memory section.

Also, a comparator 21 corresponds to the page address register 7.
is provided. This comparator 21 compares the upper address 1b supplied from the instruction address register 1 with the upper address from the page address register 7, and the upper address stored in the page address register 7 is the control address of the instruction address register 1. This is to identify whether the address is the same as the upper address of the next instruction to be executed. As a result of this comparison, if the upper address is correct, an output signal of "1" level is supplied from the comparator to the gate 27 of the next stage. This gate 27 is further supplied with the V bit of the cache memory section 3, and when this v bit is "1", the gate 27 is "1".
A level hit signal is output, and this hit signal is supplied to the gate 31 of the next stage. As a result, cache memory section 3
The instruction stored in the instruction address register 1 and designated by the lower address 1a of the instruction address register 1 is supplied to the execution unit and executed.

As described above, a cache memory according to an embodiment of the present invention is configured. Next, its effect will be explained.

Initially, for example, when execution is performed from the start address of the first page, the start address of the first page is stored in the instruction address register 1 by a control unit (not shown). ..., the upper address of this first page is stored in the page address register 7, and the instruction from the first address of the first page is stored in the cache memory unit 3 at a V of "1".
First, a case will be described in which the pages are sequentially stored together with the bits, and the page sequentially moves to the next page, for example, from the first page to the second page.

First, the upper address 1b of the top address of the first page, which is the address of the first instruction to be executed set in the instruction address register 1, is supplied to one input of the comparator 21, and is supplied to the other input. It is compared with the upper address from the page address register 7. In this case,
Since both upper addresses are equal, a match signal is supplied from the comparator 21 to the gate 27. On the other hand, this gate 27 is supplied with the V bit of the cache memory unit 3 specified by the lower address 1a of the instruction address register 1, but since this V bit is "1" in this case, the gate 27 is A hit signal ° is output, and the gate 31 is driven by this hit signal. As a result, the instruction in the entry specified by the lower address 1a of the instruction address register 1 is output from the cache memory section 3 to the execution unit, and is executed by the execution unit as the next instruction.

Further, at a predetermined time point during the execution of this instruction, the address of the next instruction to be executed is set in the instruction address register 1 under the control of the control section. This address is a normal address if the previous instruction is not a jump instruction or the like, and the upper address remains the same except that the lower address is incremented by +1. That is, the instruction is simply moved from the first instruction to the next instruction on the first page. Then, the upper address 1b of this address is supplied to the comparator 21 as in the first case described above, and is compared with the upper address supplied from the page address register 7. Since the pages are naturally the same, both upper addresses are equal, so a match signal is sent from the comparator 21 to the gate 2.
7.

Since the V bit of the cache memory section 3 of the entry specified by the lower address 1a is "1J," a hit signal is output from the gate 27, and the cache memory section 3 of the entry specified by the lower address 1a is outputted as in the case described above. The instructions of section 3 are supplied to the execution unit via gate 31.

Thereafter, similar operations are repeated for each instruction of the first page. After completing all instructions on the first page,
Next, the start address of the second page is set in the instruction address register 1. As a result, the upper address 1b of the address set in the instruction address register 1 is supplied to the comparator 21 and compared with the upper address supplied from the page address register 7. In this case, the page address register 7 is Since the upper address corresponding to the first page is stored, it does not match the upper address 1b corresponding to the second page supplied from the instruction address register 1, so a mismatch signal is output from the comparator 21. Due to this mismatch signal, all the V bits of the cache memory unit 3 are reset to "0", and the start address of the second page to be executed next is changed from the instruction address register 1 to the access control unit 13 to the external bus 15.
is supplied to the external storage device 11 via the external storage device 1
The instruction at the top address of the second page to be executed next is read from 1. This instruction is supplied to the execution unit via the external bus 15 and the access υ control unit 13 and executed, and is also executed at the lower address 1a of the instruction address register 1.
The instruction is stored in the corresponding entry of the cache memory unit 3 specified by , along with the v bit of 11'' indicating the validity of this instruction. Also, at this time, the upper address lb set in the instruction address register 1, that is, the upper address 1b of the first address of the second page, is stored in the page address register 7, and the instruction of the second page is stored in the cache memory section 3. Indicates that it is remembered. Then, after the entry of the cache memory section 3 where the instruction at the start address of the second page is stored, there is an I, not shown.
The IJ 111 sequentially stores two pages of instructions, and then sequentially supplies them to the execution unit for execution in the same way as in the case described above.

In addition, in the case where, for example, the first page and the second page are sequentially executed as described above and the page is moved to another page by a jump instruction or the like in the middle of the page, naturally the comparison of the upper addresses in the comparator 21 will result in a match. Since it does not, comparator 21
A mismatch signal is output from , and this mismatch signal resets all the V bits of the cache memory unit 3 to rOJ, and also sets the address of another page to be executed next that is set in the instruction address register 1 by a jump instruction, etc. is from the instruction address register 1 to the access control unit 13
, are supplied to the external storage device 11 via the external bus 15, and the command at the address of another page to be executed next is read from the external storage device 11. The following operations are similar to those described above.

That is, the instructions read from the external storage device 11 in this manner are transferred to the external bus 15 and the access control 1ss13.
is supplied to the execution unit via the instruction address register 1 for execution, and is stored in the corresponding entry of the cache memory section 3 specified by the lower address 1a of the instruction address register 1 along with the V bit "1" indicating the validity of this instruction. be done. At this time, the page address register 7 also contains the upper address 1b set in the instruction address register 1.
.

That is, the upper address 1b of the address of the other page to which the jump was made is accumulated, indicating that the instructions of the other page are stored in the cache memory unit 3. Then, after the entry of the cache memory unit 3 where the instructions at the addresses of other pages are stored, each instruction of the other pages is sequentially stored by a control system (not shown), and thereafter executed sequentially in the same manner as in the above case. is fed to the unit and executed.

In addition, in the above-mentioned jump processing, etc., if the jump is not to the start address of another page but to an address in the middle of another page, the cache memory unit 3 executes the jump from the entry in the middle of the jump to the other page. The instruction in the middle of is stored with the v bit of "1". The instruction of the previous page remains in the entry in the cache memory unit 3 above this intermediate entry, but the V bit for this instruction is rOJ, so if a jump instruction etc. Even if the upper instruction of another page is specified, the V bit is
0'', this prevents the instruction on the previous page from being used by mistake.

[Effects of the Invention] As described above, according to the present invention, a memory section that stores the upper address of each instruction stored in the cache memory section, that is, a tag memory section in a conventional cache memory section, is provided. Instead, a high-order address register that stores only one high-order address is provided, so the required memory is significantly reduced, making it economical and compact, especially when integrated. In this case, the chip area can be significantly reduced, making it more economical, and since a register is used in place of the conventional tag memory section, high speed is achieved.

[Brief explanation of the drawing]

The figure is a block diagram of a cache memory showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Instruction address register, 3... Cache memory section, 7... Page address register, 11... External storage device, 21... Comparator.

Claims (1)

[Claims] In order to specify the next instruction to be executed among the instructions stored in a storage device in a computer, a high-order address that specifies a predetermined number of instructions as a group, and each of the group of instructions specified by the high-order address are An instruction address register that stores an address consisting of a specified lower address, an upper address register that stores the upper address, and a group of instructions specified by the upper address stored in the upper address register. and each of the stored instructions is stored in a cache memory section specified by a lower address stored in the instruction address register, an upper address stored in the upper address register, and the instruction. Compare the upper address stored in the address register, and when both upper addresses match, specify one of the instructions in the cache memory section with the lower address stored in the instruction address register and read it from the cache memory section. and a comparison control unit that retrieves and outputs the instruction from the storage device according to the address stored in the instruction address register and stores the retrieved instruction in the cache memory section when the two upper addresses do not match. A cache memory characterized by: