JPS61269735A - Instruction queue control system of electronic computer - Google Patents

Abstract

PURPOSE:To shorten the stop time of an instruction read out wait operation by changing a pointer without flashing a queue and executing branching operation or flashing the queue and reading an instruction out of a memory newly. CONSTITUTION:When a branch instruction is generated, a branch address DISP is given. The DISP is supplied to adding circuits 14 and 15 together with its sign and the circuit 14 adds the DISP to the contents of a counter CB for the remaining number of instructions. When the DISP is negative and A+B is positive, a signal 271 becomes active to indicate that the branch destination instruction is an address CR+DISP indicated by a read out counter among instructions in a queue memory 1 which are already executed. Similarly, the circuit 15 subtracts the DISP from the number CP of pre-fetch instructions and checks whether the DISP is within the range of the CF. The DISP should be a positive value and an AND gate 28 signifies a signal C=1 indicating that the subtraction result is >=0 when the DISP is positive, namely, when S=0, thereby indicating that the branch destination instruction is in an address CF+ DISP among pre-fetch instructions in the queue memory.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field to which the Invention Pertains] The present invention relates to an instruction queue control method for efficiently and quickly reading instructions in an electronic computer.

[Prior art]

Conventionally, electronic computers have been divided into functions that can be processed in parallel to improve performance, and these functions have been divided into so-called ! Many of them are designed to operate in parallel due to their eveline structure.

As shown in the block diagram of Figure 2, this type of computer has a path interface unit (BIU) that controls the bus, reads and writes data, and a first-in-first-out memory (FIU) that preempts instructions.
Instruction queue unit (IQU) stored in FO),
Instruction decoding unit (IDU) that decodes instructions and issues operand access requests.

Convert the address from the IDU (for example, from a virtual address to a real address), identify the type of access, and use BI
Address Translation Unit (ATU) that communicates to the U.

and a CPU consisting of an instruction execution unit (EXU) that processes the fourth land read from the BIU according to the instructions decoded by the IDU and provides the results to the BIU.

Memory and Ilo (MI
O). In order for each of these units to operate smoothly in parallel, a queue of an appropriate length is provided between each unit.9 Normally, the instruction queue is used to process various commands because the CPU is relatively faster than MIO. Needs consideration.

In an electronic computer having this kind of pipeline structure, when the flow of the pipe is disturbed, the performance temporarily and sharply decreases. However, it is said that a program executed by an electronic computer generally includes a branch instruction every few steps, and it is known that performance degradation due to pipe flow disturbances becomes a serious problem. In particular, what appears frequently is
The program is as shown in FIGS. 3(a), (b), and (c).

Moreover, branching is often repeated, and during this time, the flow of the mother eve may remain disturbed.

FIG. 4 is a specific example of the gramogram shown in FIG. 3 (,). In other words, the 9 programs have WO in lines 100 and 101.
RK and COUNT are initialized and from line 102 to 104
After adding 5ALE a predetermined number of times between rows, TOT the result.
This is stored in AL, and the instructions from line 162 to line 104 are repeated N times. FIGS. 5(1) to 5(6) show an example of the state transition inside the IQH queue at that time.

The figure shows an example of a queue with a depth of 6 words, with the top row being the entry for instructions,
The bottom row is a FIFO with an exit.

ω is the state of the queue when the instruction at address 101 is to be executed (#), and the instruction at address 105 has already been read ahead and stored in the queue. ■Ha.

When the instruction at address 100 has been decoded, address 101 is placed at the beginning of the key reading, and the instruction at address 106 is newly read. For (3), continue to decode the command in the same way, and 10
The command at address 4 will be decoded. When the branch at address 104 occurs, all queues are cleared and invalidated in (4). This is called a flash. (5) is 1 again
The decoding is executed after waiting for the instruction at address 02 to be read. (6) shows a state in which when J@next key z is vacant, instructions are prefetched and loaded into the queue in parallel with decoding and execution of instructions.

However, when a branch instruction is decoded and executed like this,
There will be memory cycles to read useless instructions that will never be executed, and after the queue has been flushed, processing will stall until a new instruction is read. If such branches occur frequently, there is a drawback that a large performance deterioration occurs as a result. Note that for LSI microcomputers with a limited amount of circuitry, it is only possible to take passive measures such as limiting the depth of the queue to a few bytes to reduce wasteful memory accesses, and it is not possible to achieve sufficient performance improvement. [Objective of the Invention] The object of the present invention is to utilize as effectively as possible the instructions that are read into the instruction key when a branch instruction occurs, but are not executed. To provide an economical instruction queue control method in an electronic computer capable of executing a small loop program by reducing external memory access and shortening the CPU operation stop time due to waiting for instructions to be read, even without the need to provide an instruction queue control system. There is a particular thing.

[Structure of the Invention] The instruction queue control method for an electronic computer of the present invention includes a memory circuit in which prefetched and unexecuted instructions are written and stores instructions read out for decoding and execution, and the memory circuit. a queue write counter for providing a write address to the memory circuit; and a key for providing a read seat address to the storage circuit.
- a read counter, a queue preemption counter indicating the number of instructions that have been prefetched and are still unexecuted in said storage circuit, and a queue preemption counter that indicates the number of instructions that have been decoded or executed but still remain in said storage circuit; It consists of a queue execution counter and a control circuit that controls these elements.When a single branch instruction is decoded, the queue prefetch counter and Judgment is made by comparing the queue executed counter and the branch address, and if the queue is stored in the storage circuit, the queue read counter, the queue prefetch counter, and the queue executed counter are added based on the branch address. , or update by subtracting. If it is not in the memory circuit, clear all four counters,
The present invention is characterized in that, depending on the contents of the queue prefetch counter, a request is made to continue or stop the decoding and execution of the instruction, or to prefetch the instruction.

[Schematic operation of the invention]

The present invention retains instructions in a queue even after the instruction is decoded and executed;
When a relative branch of an instruction occurs, it is determined whether the branch address is within the range of the pre-execution and post-execution queues, and if it is within the range, the branch is executed by changing the queue pointer without flushing the queue. execute, and if it is out of range, flush the queue and read a new instruction from memory. Namely.

It has the characteristics of an instruction cache added to the instruction queue.

[Embodiments of the invention]

Next, an instruction queue control system according to the present invention will be described in detail by way of an embodiment with reference to nine drawings.

First, FIG. 6(a) shows the logical operation of the present invention.

This will be explained with reference to (b) and FIGS. 7 α) to (4).

FIG. 6 shows a state in which an instruction queue with a depth of 8 according to the present invention is implemented using a random access memory (RAM). CW (write counter) points to the next address to write the instruction read from memory, and RW (read counter) points to the next address to write the instruction read from memory.
DU points to the address where the instruction to be decoded is stored. When the instruction is written, CW is incremented by 1, and when the instruction is decoded and read, RW is incremented by 1. The counter is a loose counter modulo 8. FIG. 6(a) shows the execution state of the program shown in FIG. Here, the instruction at address 104 pointed to by CR is about to be decoded.
The instruction is prefetched up to the previous contents pointed to by cw, that is, address 107. The decoding of addresses ioo to 102 has been completed, and the decoding of address 103 is normally in progress.

According to the present invention, a counter CF indicates the number of instructions stored in the read-ahead queue, and a counter CB indicates the number of actually executed instructions still remaining in the queue.
The second step is to compare the two branch addresses and determine whether the instruction at the new address pointed to by the branch address is in the queue. At this time.

Although CF=CW-CR (modulo the queue depth), it is necessary to note that CB≦CR-CW (modulo the queue depth).

Like FIG. 6(,), FIG. 7 shows the execution state of the program in FIG. 4, and shows the transition of the contents of the counter. FIG. 7(1) shows a state in which instruction decoding has proceeded by one step from FIG. 6(,). When the branch instruction at address 104 is executed, the process transitions to FIG. 7(2). That is, the 4-branch address (disp) is -3.

It is compared with the counter CB of executed instructions, and since it is within that range, the queue is not flushed and retains the same contents as in FIG. 7(1). CR points to address 7 of the queue containing the instruction at address 102 to which disp has been added, and CW does not change. CF becomes 6 by subtracting disp (-3), and CB becomes 2 by adding diap (-3).

Next, since there are enough instructions to decode, the CF is determined and if it is above a certain value, no request is issued to read the instructions, and the CW
is not updated. FIG. 7(3) shows the case where the instruction execution progresses in this way, passing through the loose and 105
Shows the state in which the instruction at the address is being decoded. In this case,
This shows that CW has not changed, CF has decreased and CB has increased by the amount that CR has progressed.

FIG. 7(4) shows an example in which decoding and reading of the instruction proceed simultaneously because the value of CF has decreased, and CF and CB do not change. In addition, if we strictly express the actions of 5 or more.

(1) When an instruction is read, it is stored in a queue and the counter is updated.

The remaining days CW=CW+l CR=CRCF=CF+ 1CB
=CB-1 (CF+CB=When depth is Q) CB=CB
(When the depth of CF operator CB<Q) (2) When an instruction other than a branch instruction is taken out of the queue and decoded, the counter is updated.

CW=CW CR=CR+I CF=CF-1CB
=CB+1 (3) When the branch instruction is decoded and executed, the counter is updated.

(A) In the case of disp)CF or -disp)CB.

CW=CR=CF=CB=0 (B) 0≦disp≦CF, or 0≦-disp≦CB
in the case of.

CW=CW CR=CR+dispCF=
CF-disp CB=CB+disp. In any of the above cases, diap is a signed relative branch address.

FIG. 8 shows an example of interface signals with other units when the instruction queue unit (IQU) according to the present invention is applied to the electronic computer shown in FIG. 2. This I
QU sends an instruction read request REQ-R to BIU.
A D times signal is output, and in response, the BfU provides read data (command) R-DATA and a ITE-Q signal that guarantees read data (instruction) and data and indicates that writing to the queue is possible. On the other hand, when there is data I in the queue from the IQU, the IDU receives a Q-READY signal. It) When U gives an instruction takeover request READ-Q to IQU.

IQU outputs the instruction Q-OUT to be decoded. I
IM and J decode the instruction and, in the case of a one-branch instruction, provide a signal BRNCH indicating it and a branch address DISP to IQU.

In addition, avoid too many read-ahead instructions.

There is a signal OPT-K that gives the optimum value and a signal INZ that forcibly initializes IQU.

FIGS. 1(a) and 1(b) are block diagrams showing an embodiment of an instruction queue unit according to the present invention. In this figure, 5 queue memory 1 (Q-M) is a general memory that can be read and written.
command) When R-DATA is given as BTU, W
RITE-Q signal K Yokute write'! Read, READ-
The Q signal outputs read data to Q-OUT.

Counters 2, 3, 4.5 are CW, CR, CB, respectively.
CF is configured, and CW is the write address of Q-M.

CR gives the read address. Reference numeral 13 denotes a signed adder circuit which calculates the value of CR at the time of one branch instruction.

Signed adder circuits 14 and 15 are used to determine the range of CB and CF and two-branch addresses, respectively, and to determine the values of CB' and CF, respectively, after nine branches. 16 is CB and C
It is an adder circuit of F and is used to control the update of CB by comparing the addition result with Q-8IZE indicating the depth of QM by a comparator circuit of 17. A decoder 18 checks whether CF is 0'' or not, and generates a Q-READ''1' signal which determines whether the instruction decoding unit (IDU) can read the instruction queue.

19 indicates a comparison circuit, if CF is below a certain value.

Signal REQ-RD requesting BIIJ to read instructions
Output. The constant OPT-K that is compared may change dynamically depending on other path usage conditions. counter 2
5 operate in the same way as explained in FIG. The counter is cleared and becomes CW = CR = CB = CF - "0". Therefore, after initialization, the comparator circuit 19!+ (O
PX-K)-OF) becomes O, and R for BIU
At the same time, the decoder 18 detects CF=O and makes the output signal Q-READY of the inverter 31 inactive, and the instruction to be decoded by the IDU is sent to the Q-M. Let me know that it doesn't exist. When BIU reads the command.

R-DATA is applied to IQU to activate ■ITE-Q signal, and a command is written to Q-M accordingly. WRITE-Q signal 201 is delayed through delay circuit 20 around the time when writing is completed. is CW and CF (7)
It is given to the I terminal and +1 (added). CW indicates the address of the QM to be written next. As a result, since CF is no longer 0, the output of the decoder 18 becomes inactive, so the Q-READY signal becomes active, and the ID
U can now start decoding instructions. When I Dt,i outputs the command read signal READ -Q, Q
-M outputs the instruction at the address pointed to by CR and gives it to the IDU.

The RgAI)-Q signal, which has been appropriately delayed by the delay circuit 21, is applied to the I terminals of CR and CB for +1 (addition), and is applied to the D terminal of CF for -1 (subtraction).

That is, CR indicates the address of QM to be read next.

CB increases by 1 and CF decreases by 1. As this operation progresses, CF 10B becomes the depth of the queue (CF officer CB
=Q-3IZE), CF + CB ≦Q-5I
Since ZE must be used, if the number of CF increases by one, the number of CB decreases by one.

That is, when CF and CB are added in the adder circuit 16 and compared with Q-5IZE in the comparator circuit 17 and a match is detected, the Q-FULL signal becomes active and the AND r-1
CB -1 when the WRITE -Q signal is generated through 22
Let them do it.

When a branch instruction occurs, the BRNCH signal from the IDU becomes active and provides the 9 branch address DISP. DISP is applied to adder circuits 14 and 15 without being signed. The adder circuit 14 adds CB and DISP, but the sign bit 3 of DISP = l (DIS
and date 2 only if P is negative)
7 enables the carry output of the adder circuit. That is.

When DISP is negative and the result of A+B (Actually, since DISP is negative, CB - IDl5PI) is positive, the 271 signal becomes active and the instruction one branch ahead is in Q-M. Indicates that the instruction is at address CR+DISP among the executed instructions. Similarly, the adder circuit 15 subtracts CF and DISP to obtain DIS
Check whether P is within the range of CF.

Therefore, DISP must be a positive value, and r-
In step 28, when the sign of DISP is positive (S=0), the signal C"=1 which indicates that the subtraction result is "0" or more is enabled, and the signal 281 becomes active and the instruction at the 9th branch destination becomes Q.
-Indicates that the prefetched instruction in M is at address CF+DISP. That is, as a result.

For addition circuits 14 and 15, the actual operation is subtraction.
Valid only occasionally. Signal 271. or 281 becomes active, the signal HIT indicating that the branch destination instruction is in Q-M via 6 or f-to 30 becomes active.Since the υ1 branch instruction BRNCH is active. and? -) 23 output 231 becomes active and CR, CB, corresponding to the address of one branch destination,
The value of CF is calculated and set in adder circuits 13, 14, and 15, respectively.

CR is set to a value modulo the size of f.

For CB and CF, valid values are always sent when no carry occurs. Conversely, if the instruction at the branch address destination is not in Q-M, the HIT signal becomes inactive, so
The output of AND gate 25 becomes active. Therefore, when signal 261 becomes active, all counters CW, CR, CB, and CF are cleared and Q-M
The commands inside will be the same as the initial state when no commands are available.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, when taking adjacent branches as shown in FIG. 3, as long as the branch address is within the range of CB and CF,
You can continue the command without franchising and rereading 1
The following effects can be obtained.

(1) When the processing speed of the CPU increases, the pathneck of not being able to transfer data to be processed in time is improved.

(2) Processing that involves consecutive branches of particularly close addresses,
The instructions necessary for processing such as skipping of control instructions remain in the Q-M and are ready to be executed immediately, so high-speed processing is possible.

(3) It requires less circuitry than a general cache memory (and can be easily integrated into an LSI. Only a few circuits need to be added to a normal instruction queue).

(4) Optimal performance can be tuned by making the queue size variable.

[Brief explanation of the drawing]

1(a) and (b) are block diagrams showing the configuration of an embodiment according to the present invention, FIG. 2 is a block diagram showing an example of the configuration of an electronic computer having a conventional pipeline structure, and FIG. a) # (b) and (c) are flowcharts of example programs that are elements that disturb the flow of the Tsukubu line;
Figure 4 is an example of a specific program of the flowchart in Figure 3 (a), and Figures 5 (1) to (6) are examples of when the program in Figure 4 is executed by the computer in Figure 2. FIG. 3 is a diagram for explaining the movement of an instruction queue. 6(,) and (b) are 9 diagrams for explaining the operation of a counter that controls the instruction queue according to the present invention, and FIGS. 7(1) to (4) are 2 diagrams according to the present invention. FIG. 8 is a diagram illustrating an example of an interface signal between the instruction queue unit and other units according to the present invention. . In the figure, 1 is the queue memory (Q-M), 2 is the queue write counter (CW), and 3 is the queue read counter (C
R), 4 is a queue preemption counter (CB), 5 is a queue execution counter (CF), 13 to 16 are addition circuits, 17
．． 19 is a comparison circuit, and 18 is a decoder. 20.21 is a delay circuit. Figure 1 (b) Figure 2 Figure 3 (a) (b)
(C) Ward 4, Figure 5, Figure 7

Claims (1)

[Claims] 1. A memory circuit in which prefetched and unexecuted instructions are written and which stores instructions read out for decoding execution; a queue write counter that provides a write address to the memory circuit; and a queue write counter that provides a write address to the memory circuit; a queue read counter that provides an address; a queue prefetch counter that indicates the number of instructions that have been prefetched and are still unexecuted in said storage circuit; and a queue preemption counter that indicates the number of instructions that have been decoded or executed but still remain in said storage circuit. When a branch instruction is decoded, the queue execution counter indicates whether or not the instruction pointed to by the branch address is in the storage circuit. The determination is made by comparing the prefetch counter and the queue executed counter with the branch address, and if the queue read counter, the queue preemption counter, and the queue executed counter are stored in the storage circuit, the queue read counter, the queue preemption counter, and the queue executed counter are also updated based on the branch address. If it is not in the storage circuit, all four counters are cleared, and depending on the contents of the queue preemption counter, the instruction decoding execution is continued, stopped, or the instruction preemption is performed. An instruction queue control method for an electronic computer characterized by requesting the following.