JPH05282146A - Information processor - Google Patents

Abstract

PURPOSE:To provide an information processor for selectively storing access contravention information in the fetch of plural instruction strings in a control register. CONSTITUTION:In an information processing system provided with an instruction execution part 4 for executing the instruction strings of plural streams prior to the determination of an instruction flow and an instruction fetching part 4 for precedently fetching the flow of plural instructions 30 requested by the execution part 4, the fetching part 2 adds access contravention information 22 generated by instruction fetching to a dummy instruction 31 and supplies the information-added dummy instruction to the execution part 4. At a stage after determining the flow of the instructions, the execution part 4 generates an instruction fetch exception by using the information added to the instruction 31 and stores access contravention information 23 in the control register 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus having an instruction execution unit and an instruction fetch unit for processing a plurality of instruction streams in advance, and stores access violation information regarding instruction fetch in a control register. It is about control.

[0002]

2. Description of the Related Art In recent years, in information processing apparatuses, in order to realize virtual storage, a method in which a memory management unit or the like detects an access violation with respect to an instruction fetch is often adopted.
An example of the above-described conventional information processing unit will be described below with reference to the drawings. FIG. 4 shows a schematic configuration diagram of a conventional information processing unit. In FIG. 4, reference numeral 1 is a control register, and when an access violation related to instruction fetch is detected in the memory management unit 3, the access violation information 20
Is written, and when the exception handling handler is executed in the instruction execution unit 4, the access violation information 21
Read through. 2 is an instruction fetch unit, which fetches an instruction subsequent to the instruction being executed by the instruction execution unit 4 that has not been fetched, receives the instruction 30, and supplies it to the instruction execution unit 4 via the instruction 31. To do. When it receives the instruction fetch exception 40, it outputs a dummy instruction to the instruction 31 and asserts the instruction fetch exception 41. A memory management unit 3 converts an instruction logical address 10 into an instruction physical address 11 and at the same time examines the attribute of the memory space of the access, asserts an instruction fetch exception 40 if there is an access violation, and accesses the access violation type. Output to violation information 20. An instruction execution unit 4 receives an instruction 31 from the instruction fetch unit 2 and executes it. When an instruction fetch exception 41 is received, an instruction fetch exception occurs, and control is transferred to an instruction fetch exception processing handler. Where 50
Indicates the destination address.

The operation of the information processing apparatus configured as described above will be described below. First, the instruction fetch when no exception occurs will be described. First, the instruction fetch unit 2 outputs the instruction logical address 10 in order to fetch the instruction subsequent to the instruction executed by the instruction execution unit 4. The instruction logical address 10 is translated by the memory management unit 3 and the instruction physical address 1
1 is output. The instruction corresponding to the instruction physical address 11 is output to the instruction 30, the instruction fetch unit 2 receives the instruction 30, and supplies it to the instruction execution unit 4 via the instruction 31.

Next, a case where an instruction fetch exception occurs will be described. The instruction fetch unit 2 starts the instruction fetch as in the case where no exception is generated. Next, the memory management unit 3 uses the instruction logical address 10 to perform address conversion and access violation detection, and an access violation occurs.
Therefore, the instruction fetch exception 40 is asserted, and the access violation information 20 is fetched in the control register 1. Upon receiving the instruction fetch exception 40, the instruction fetch unit asserts the instruction fetch exception 41 and supplies the dummy instruction to the instruction 31. When executing a dummy instruction having a flag indicating that an instruction fetch exception has occurred, the instruction execution unit 4 generates an instruction fetch exception and transfers control to the instruction fetch exception handling handler. The instruction fetch exception handling handler obtains the contents of the control register 21 via the access violation information 21, that is, the information of the access violation generated by the instruction fetch, using the instruction to read the control register 1, and performs exception processing based on the information. To do.

[0005]

However, in the above configuration, a plurality of instruction sequences are fetched, and the instruction execution unit 4 executes the instructions in advance before the instruction flow is determined,
When fetching a plurality of instruction sequences in an information processing device that validates only the execution result of the instruction belonging to the selected instruction flow among the results of the instructions that were executed in advance after the instruction flow was determined If an access violation occurs,
One of a plurality of access violations can be selected when the instruction flow is determined in the instruction execution unit 4, and when the access violation is detected, it is possible to selectively write the access violation information 20 to the control register 1. Since it cannot be performed, there is a problem that access violation information cannot be passed to the exception handler.

In view of the above problems, it is an object of the present invention to provide an information processing device for selectively storing access violation information in fetching a plurality of instruction sequences in one control register.

[0007]

In order to solve the above problems, the present invention provides an instruction execution unit that executes a plurality of instruction sequences in advance before the instruction flow is determined and a plurality of instruction sequences. If an access violation occurs in the instruction fetch, the information fetching unit includes an instruction fetch unit that fetches the data and supplies it to the instruction execution unit, and a control register that stores exception information. Is supplied to the instruction execution unit, and after the instruction flow determines that an instruction fetch access violation has occurred, the instruction execution unit writes the information that caused the instruction fetch access violation in the valid instruction sequence to the control register. Be prepared.

[0008]

According to the present invention, when the access violation occurs in the instruction fetch, the information of the access violation is notified to the instruction fetch unit, and the instruction fetch unit is as if the instruction not fetched due to the access violation is fetched. As described above, the access violation information is supplied to the instruction execution unit together with the dummy instruction. When the instruction execution unit processes an instruction having access violation information when processing the completion of the instruction in the selected instruction flow after the instruction flow is determined, the instruction execution unit stores the access violation information in the control register and Generates a fetch exception and transfers control to the exception handler. The exception handler can read the control register and obtain the access violation information.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An information processing apparatus according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of an information processing apparatus in an embodiment of the present invention. In FIG. 1, 1 is a control register that stores access violation information, 2 is an instruction fetch unit that fetches a plurality of instruction streams and supplies instructions and access violation information to an instruction execution unit, 3
Is a memory management unit which performs address translation and detection of access violation, 4 executes a plurality of instruction sequences prior to determining the instruction flow, and processes the instruction having access violation information after the instruction flow is determined In this case, the instruction execution unit stores access violation information in the register 1 and generates an exception.

FIG. 2 shows a block diagram of an example of the instruction fetch unit. 2, the same parts as those in FIG. 1 are designated by the same reference numerals. Reference numerals 110 and 120 denote FIFO (first in first out) memories composed of four buffers 111 to 114 and 121 to 124 each including a pair of an instruction part and an access violation information part. 101 is FIFO memory 110 and 120, selectors 104 and 105
Is an instruction queue composed of 100 is the instruction queue 101
Is a control circuit for controlling. The control circuit 100 outputs the branch destination address indicated by the jump destination address 50 or the program order address to the instruction logical address 10 to fetch the instruction, and controls the instruction queue 101 with the signal 103. The jump destination address 50 is input from outside the instruction fetch unit 2, but this shows an example of the case where the calculation of the branch destination address is performed outside the instruction fetch unit 2, The present invention is also effective when the instruction fetch unit 2 decodes an instruction to calculate a branch destination address, and the configuration of the instruction fetch unit 2 is not particularly limited. The instruction queue 101 is controlled by the signal 103 for the following 1) and 2). 1) Fetch the fetched instruction 30 and access violation information 20 between the branching side and the branching side.
Two FIs depending on which of the two instruction streams they belong to
The FO memories 110 and 120 are separately stored, and 2) the instruction and access violation information output from the two FIFO memories 110 and 120 are selected and output to the instruction 31 and the access violation information 22. At this time,
When the access violation information indicates that some kind of violation is detected, the NOP instruction is output to the instruction 31. When the instruction flow is confirmed, the contents of the FIFO memory that does not hold the valid instruction sequence are invalidated. The instruction queue 101 is composed of two FIFO memories 110 and 120. This is because the instructions fetched in advance by invalidating one of the FIFO memories when the flow of two instructions is determined. This is because the instruction queue can be invalidated.
The configuration of 101 is not limited. Further, the number of FIFO memories and the number of buffers of the FIFO memories are not limited.

FIG. 3 is a block diagram showing an example of the instruction execution unit 4. 3, the same parts as those in FIG. 1 are designated by the same reference numerals. 21 to 23 are access violation information, 31 is an instruction, 201 is a decoder, 202 is an execution waiting buffer which stores an instruction waiting to be executed by the decoder 201, 203 is an arithmetic unit, and 204 is an arithmetic unit 203. It is a completion waiting buffer that stores an instruction that waits for completion at the completed instruction. Also, the access violation information 22 moves in pairs with the instruction 31,
It is stored in the execution waiting buffer 202 and the completion waiting buffer 204. The fetched instruction 31 is decoded by the decoder 201, and the execution wait buffer 20 along with the access violation information 22.
Store in 2. Then, among the instructions stored in the execution waiting buffer 202, an instruction having no data dependence or resource conflict is executed by the arithmetic unit 203 regardless of the program order, and is stored in the completion waiting buffer 204. The instructions stored in the completion waiting buffer 204 are completed in the order of the instructions. In other words, the completion wait buffer may contain instructions belonging to a plurality of instruction streams, but it is completed after the instruction flow is confirmed, and when the instruction flow is confirmed, the execution wait buffer 202 And the instruction belonging to the instruction stream that is not valid and is stored in the completion waiting buffer 204 is invalidated.

In this way, the instruction executing section 4 can execute instructions belonging to a plurality of instruction streams in advance. Even if an instruction pipeline having neither the execution waiting buffer 202 nor the completion waiting buffer 204 is used, it is possible to execute instructions belonging to a plurality of instruction streams in advance up to the middle of the instruction pipeline. The structure of Part 4 is not limited. The branch address is calculated by the arithmetic unit 203 and output to the jump destination address 50.

Further, if the instruction to be completed from the completion waiting buffer 204 has access violation information indicating access violation, the content is the access violation information 23.
Is output to, an exception is generated, and control is transferred to the exception handling handler. At this time, the instructions stored in the completion waiting buffer 204 and the execution waiting buffer 202 are invalidated.

The operation of the information processing apparatus configured as described above will be described below with reference to FIGS. 1, 2 and 3. First, the operation of fetching and executing an instruction sequence that does not include a branch instruction will be described. That is, there is one instruction flow. At this time, the newly fetched instruction 30 and access violation information 20 is stored in the selected one of the FIFO memory 110 or the FIFO memory 120, and the output of the selected FIFO memory is output to the instruction 31 and access violation information 22. Controlled to be done. If there is a vacancy in the selected FIFO instruction due to the supply of the instruction,
The address of the instruction following the instruction stored at the end of the FIFO memory is output to the instruction logical address 10 to start the instruction fetch.

Further, with respect to the instruction logical address 10 output from the instruction fetch unit 2, the memory management unit 3 performs address conversion and access violation detection. If there is no access violation, the instruction physical address 11 is supplied to the storage device, and the instruction corresponding to that address is sent to the instruction 30.
Fetched by the instruction fetch unit 2 as described above.
And is supplied to the instruction execution unit 4.

Next, since the supplied instruction 31 belongs to the confirmed instruction flow, it is completed without being stopped because the instruction flow is undecided in the completion waiting buffer 204. If there is an access violation in the instruction fetch, the access violation information 20 is sent to the instruction fetch unit 2. Therefore,
After the access violation information 20 is stored in the last access violation information section of the selected FIFO memory and the previous instruction is supplied through the instruction 31, the access violation information 22
Is output to. At this time, as a dummy instruction for instruction 31,
NOP instruction is output. Further, the instruction fetch following the fetch that caused the access violation is not performed. This is because the subsequent instruction cannot be executed unless the execution of the instruction that should have been obtained by the fetch that caused the access violation is completed. The dummy instruction corresponding to the fetch that caused the access violation and the access violation information are supplied to the instruction execution unit 4 via the instruction 31 and the access violation information 22, respectively. After the instruction preceding the dummy instruction is completed and is ejected from the completion waiting buffer 204, when the dummy instruction is completed, the access violation information of the dummy instruction indicates that there is an access violation. The instruction is not completed, the access violation information is stored in the control register 1 through the access violation information 23,
An exception occurs and control is transferred to the exception handler.

The exception handler is fetched in the same manner as a normal instruction string and processed by the instruction execution unit. At this time,
By executing an instruction to read the control register 1, the access violation information can be read out through the access violation information 21 and the processing can be performed according to the information.

Next, the operation of fetching and executing an instruction string including a branch instruction will be described. At this time, the instruction flow is divided into an instruction sequence preceding the branch instruction, an instruction sequence following the branch instruction, and an instruction sequence to which the branch instruction jumps. Although it is determined that the instruction sequence preceding the branch instruction is completed, the instruction sequence subsequent to the branch instruction and the instruction sequence to which the branch instruction jumps are determined to be completed when the branch instruction is executed. It's time to finish. However, there are cases where the calculation of the jump destination address of the branch instruction can be performed before the determination of the branch condition.

First, the instruction currently being executed by the instruction execution unit 4 does not include a branch instruction, and the instruction sequence belonging to the instruction flow is stored in the FIFO memory 110 of the instruction fetch unit 2. Then, a branch instruction appears in the instruction sequence, and the instruction execution unit
It is executed by the arithmetic unit 203 of 4 and the address of the branch destination is output to the jump destination address 50. The instruction fetch unit 2 sets the address indicated by the jump destination address 50 to the instruction logical address 10
To output the instruction fetch. The memory management unit 3 performs address translation and access violation detection. If there is no access violation, the instruction flow is different.
It is stored in the memory 120. Therefore, the instruction on the branch not taken side is stored in the FIFO memory 110, and the instruction on the taken side is stored in the FIFO memory 120.
Will be stored in.

Regarding the instruction supply, until the instruction on the branch taken side is fetched, the instruction on the branch not taken side, that is, the instruction stored in the FIFO memory 110 is supplied, and the instruction on the taken side is fetched. Then, the output of the FIFO memory 120 is supplied to the instruction execution unit 4 through the instruction 31. The instruction execution unit 4 decodes the branch taken side or branch not taken side instruction, stores it in the execution waiting buffer 202, executes it in the arithmetic unit 203, stores it in the completion waiting buffer 204, and waits for the completion of the instruction. When the branch condition is determined during the series of execution operations and the branch is taken, the instruction on the non-taken side of the branch held by the instruction execution unit 4 is invalidated, and at the same time the instruction stored in the FIFO memory 110 is invalidated .. When the branch is not taken, the instructions on the branch taken side of the instruction execution unit 4 and the instruction fetch unit 2 are invalidated. Instructions that have not been invalidated due to branch determination are completed in order and are expelled from the completion waiting buffer 204. After the branch is confirmed, the instruction fetch unit 2 continues to fetch the subsequent instruction on the side that has not been invalidated. Conversely, if there is an access violation in the instruction fetch at the jump destination of the branch, the access violation information 20 is written in the FIFO memory 120 on the branch taken side. Here, the subsequent instruction on the branch taken side is no longer fetched, and the subsequent instruction on the branch not taken side is fetched. Furthermore, when an access violation occurs in the fetch of the subsequent instruction on the branch not taken side, the access violation information 20 is written to the FIFO memory 110 on the branch not taken side. Instruction supply when an access violation occurs on the branch taken side is performed by outputting the access violation information and the dummy instruction on the branch taken side to the access violation information 22 and the instruction 31, respectively. After that, the instruction on the branch not taken side is supplied, and finally, the access violation information and the dummy instruction on the branch not taken side are supplied.

The instruction execution section 4 executes a dummy instruction having access violation information indicating that an instruction access violation has occurred. At this time, the dummy instruction is a NOP instruction, and goes through the execution waiting buffer 202 and the arithmetic unit 203 to the completion waiting buffer 204 for processing. However, the two dummy instructions are completed until the branch condition is fixed, and the completion wait buffer 20
You won't be kicked out of 4. If the branch condition is determined during the series of processes and the branch is not taken, the instruction belonging to the branch taken side instruction stream is invalidated. On the contrary, when the branch is taken, the instruction belonging to the instruction flow on the branch not taken side is invalidated. Naturally, one of the dummy instructions having two pieces of access violation information is invalidated.
Therefore, after the branch is confirmed, only the instructions belonging to the instruction flow determined by whether the branch is taken or not taken are completed in the completion waiting buffer 204. At this time, only the access violation information of the dummy instruction belonging to the completed instruction flow is written in the control register 1 through the access violation information 23. At the same time, an exception occurs and control is transferred to the exception handler. Therefore, the exception handler can obtain the access violation information by reading the control register 1 and perform the processing.

In the present embodiment, the memory management unit 3 is used as a device for detecting an access violation related to instruction fetch, but it is obvious that it may be replaced with any other device for detecting an exception related to instruction fetch. And may be, for example, a bus control unit.

[0023]

As described above, according to the present invention, when an access violation for an instruction fetch occurs in an information processing apparatus that fetches and executes a jump destination of a branch instruction in advance, the access violation information is converted into a dummy instruction. When it is added and supplied to the instruction execution unit and the branch is confirmed in the instruction execution unit,
When an instruction flow is selected and decided, and when the instruction belonging to the selected and decided instruction flow has access violation information indicating access violation, the access violation information is stored in the control register and an exception is generated. However, by transferring control to the exception handler, the exception handler can read the control register to obtain access violation information. Therefore, the access violation information on the side where the branch is taken and the access violation information on the side where the branch is not taken can be selectively stored in the control register and passed to the exception handler.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an information processing device according to an embodiment of the present invention.

FIG. 2 is a block diagram of an instruction fetch unit in the same embodiment.

FIG. 3 is a configuration diagram of an instruction execution unit in the same embodiment.

FIG. 4 is a configuration diagram of a conventional information processing device.

[Explanation of symbols]

 1 control register 2 instruction fetch unit 3 memory management unit 4 instruction execution unit 10 instruction logical address 11 instruction physical address 20, 21, 22, 23 access violation information 30, 31 instruction 40 instruction fetch exception 50 jump destination address 100 instruction fetch unit Control circuit 101 Instruction queue 103 Control signal 104, 105 Selector 110, 120 FIFO memory 111, 112, 113, 114, 121, 122, 123, 124 Buffer 201 Decoder 202 Execution wait buffer 203 Arithmetic unit 204 Completion wait buffer

Claims (1)

[Claims] 1. An instruction execution unit for executing an instruction sequence of a plurality of streams prior to the determination of an instruction stream, and an instruction fetch unit for fetching a plurality of instruction streams requested by the instruction execution unit in advance. In the information processing system, the instruction fetch unit adds the access violation information generated by the instruction fetch to a dummy instruction and supplies the dummy instruction to the instruction execution unit, and the instruction execution unit determines the instruction flow. In the stage, the information processing apparatus, wherein an instruction fetch exception is generated by using the access violation information added to the instruction, and the access violation information is stored in a control register.