JPS61269540A - Spread spectrum communication system - Google Patents

Abstract

PURPOSE:To simplify the circuit and to obtain a strong immunity to jamming by providing a Costas loop PLL including a narrow band loop adding offset signals for frequency hopping and the 1st and 2nd frame period control circuits. CONSTITUTION:An input signal of a reception system is multiplied (50, 51) with a signal of a voltage controlled oscillator 58, the phase difference component obtained is added (54) with a hopping pattern signal and the result is used to control an oscillator 58 thereby constituting a narrow band loop PLL and when not added, a normal Costas loop is formed. In selecting a switch 60 to the high position and the switch 61 to the open state, an FM demodulation signal passes through a correlation device 62 for frame synchronous sweep pattern signal extraction and a frame synchronous signal is extracted. Then a control circuit 66 starts a frequency hopping pattern and scramble at the initial frame synchronization and controls the changeover with a loop constant at the 2nd frame synchronization.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a spread spectrum communication system that switches from carrier acquisition to tracking.

(Prior Art) In a conventional spread spectrum communication system using frequency hopping, a phase discontinuity point occurs in the carrier because the outputs of a plurality of synthesizers are combined and switched for use on the carrier.

Therefore, it is not suitable for a receiver using a coherent detection method, and it has been particularly difficult to realize a high-speed device.

Non-coherent receivers require more complex circuits, have restrictions on the channel spacing of each carrier frequency, and are less favorable than coherent receivers in terms of interference.

On the other hand, in the conventional direct-sequence spread spectrum communication system, a PLL demodulation method is known as a coherent demodulator, but it is limited to cases where the carrier frequency is fixed.

No coherent demodulator is known in the frequency hopping system.

(Object of the Invention) An object of the present invention is to perform FM demodulation of the loop constant of a PLL demodulator when moving from carrier acquisition to data demodulation in a steady state in a coherent frequency hopping spread spectrum communication system. An object of the present invention is to provide a spread spectrum communication system in which switching occurs in the center of a frame synchronization sweep pattern.

(Structure of the Invention) In order to achieve the above object, a spread spectrum communication system according to the present invention uses a narrowband loop and a normal loop for adding frequency hopping offset signals in a frequency hopping coherent detection type spread spectrum system. A control circuit is provided that starts a frequency hopping pattern and a PN for scrambling at the first frame synchronization and switches the loop constant at the second frame synchronization when capturing the frame synchronization and the carrier of the frequency sweep pattern synchronized with the Costas loop PLL. It is composed of

(Example) Hereinafter, the present invention will be described in more detail with reference to the drawings and the like.

FIG. 3 shows a principle block diagram of an embodiment of the transmitting system of the spread spectrum communication system according to the present invention, and FIG. 4 shows an embodiment of the receiving system.

First, the block diagram of the transmission system, FIG. 3, will be explained.

The transmission system block is given an audio signal 3 and a data signal 4 as input signals, and a bit synchronization signal 1 and a frame synchronization signal 2 as synchronization signals.

The audio signal 3 is connected to a low-pass filter 6 via a pre-emphasis circuit 5, band-limited, and A/D converted 7.
Alternatively, it is processed by an ADM8 or the like and converted into a digital signal.

The digital signal is input to the encoder 9 together with the data signal 4 and converted into serial data.

An error correction code is added to this serial data by an error correction code adding circuit 10, interleaved by an interleave circuit 11, scrambled by a 10th order polynomial circuit, and a frame synchronization signal is also added at the same time.

On the other hand, the RF carrier is frequency-hopped using a frequency hopping pattern based on a seventh-order polynomial and a sweep signal for acquisition.

This carrier is a signal scrambled by a scramble circuit 12, modulated by a phase modulator 14, and outputted as an RF output 15.

Next, the blocks of the receiving system will be explained with reference to FIG.

The received RF signal 16 is captured by the capture circuit 17, the PLL of the receiver is locked, and the bit synchronization signal 21. A polynomial is generated using the frame synchronization signal 22 and a hopping pattern is reproduced using the hopping pattern circuit 19.
The LL is kept locked, and at the same time, a 10th order polynomial is generated and descrambled by the descrambling circuit 20.

Thereafter, the deinterleaving circuit 23 deinterleaves the error correction circuit 24, the decoder 25 separates the audio PCM signal and the data signal 29, and the D/A converter 26 converts the audio PCM signal into an audio signal. converted, low-pass filter 27, de-emphasis circuit 2
8 to the output terminal 30.

FIG. 1 shows a signal frame structure of an embodiment of the SS system according to the present invention.

One frame is made up of 2''=1024 bits, and one frame is further divided into eight subframes made up of 27=128 bits.

The signal in one frame has a code length of 1024 bits.
The first 16 bits of the frame are a synchronization signal and are therefore removed from the scramble, forming a specific synchronization pattern.

The frequency-hopped carrier is PSK-modulated with a signal scrambled with this 10th order PN.

On the other hand, within one subframe, there are 7 bits with a code length of 128 bits.
The carrier frequency is hopped in the next series of parallel PN frequency hopping patterns.

However, the first 16 of the first subframe of one frame
For bits, the carrier frequency is digitally swept as shown in Figure 2 for PLL acquisition of the receiver.
It is removed from the 7th order PN frequency hopping pattern.

Note that the 16 bits for acquisition use the same bits as the 16 bits for frame synchronization.

In this way, the signal is 210-102 per frame.
4-bit PN and ■27=128 in subframe units
The bit PN frequency is doubly scrambled using a hopping pattern, and within one frame, the frequency hopping pattern is repeated eight times in units of subframes.

Next, details of the modulation/demodulation section of the embodiment of the spread spectrum communication system according to the present invention will be explained.

FIG. 5 is a detailed block diagram of the modulator.

First, carrier frequency hopping will be explained.

PN by a 7th order polynomial synchronized with the bit frame is P
It is generated by the N generation circuit 40.

Within one 1024-bit frame, 128 bits according to this PN
It is repeated eight times in units of subframes, each cycle of which is a bit.

The frequency hopping signal for the first 16 bits of the frame is a sweep pattern signal for acquisition, and is provided by the frame synchronization control section 38.

The PN frequency hopping pattern signal or acquisition sweep pattern signal is selected by the switch 42 and sent to the D/A converter 43.

That is, for the first 16 bits of the frame, the acquisition sweep pattern from the synchronization control section 38 is provided to the D/A converter 43 with the switch 42 in the down state.

From the 17th bit to the 1024th bit, switch 4
2 is above, a PN frequency hopping pattern signal based on a seventh-order polynomial is supplied to the D/A converter 43.

In this way, when frequency hopping for one frame is completed, the switch 42 is turned down, and the same cycle is repeated.

In this way, the frequency hopping signal is applied to the D/A converter 43, and the converted signal is waveform-shaped by the hold circuit 44 and applied to the VCO 45.

The VCO 45 is frequency-modulated with the frequency hopping signal from the hold circuit 44, and a frequency hopping carrier, that is, a carrier with a spread spectrum, is generated.

Since this carrier is PSK modulated, it is divided into two systems. One side remains as it is, and the other side is set to 1 by the phase shifter 46.
The phase is changed by 80° and selected by the switch 47, and the PS
A K signal is generated.

On the other hand, the interleaved signal is scrambled with a PN signal using a 10th order polynomial synchronized with the frame.

FIG. 6 is a block diagram showing an embodiment of the receiving system of the system according to the present invention.

FIG. 7 shows the Costas loop PLL of the receiving system.

Input signal I + A cosφb (t) to input 49
is entered. The coder corresponds to PSK modulation 10.

This input signal is divided into two, and the signals CO3φb(t) and sinφb(t) from VC058 and the multiplier 5
Each is multiplied by 0.51.

From the product, low-pass filters 55 and 56 separate two orthogonal low frequency components indicating a phase difference, and the two orthogonal components are multiplied together by a multiplier 59 to obtain a phase error component (KI K2 A2 /8) ・sinφc (t)
get.

This phase error component passes through a filter 57 and is added with a hopping pattern signal φd (t) by an adder 54.
It is input to VC058, and the oscillation angular frequency dφd(
t)/dt.

In this case, if the adder 54 is not provided and the hopping pattern signal φd (t) is not added, a normal Costas loop will be formed.

The above signals are connected by the following formula.

dφc(t)/dt = 2 (dφa(t)/dt−φd (t) −ω
f(KI K2 A2/8) ・ /h(t-τ) sin φc (t)dr)
...(1) The left side is the angular frequency of the error signal, the first term on the right side is the angular frequency of the input signal, the second term is the frequency hopping pattern, the third term is the free-running internal frequency of the VCO, and the fourth term is the loop filter. This is the error signal output that passes through.

The input signal angular frequency dφa(t)/dt, the VCO free-running angular frequency ωf, and the frequency hopping pattern signal φd (
If the sums of t) are chosen to be equal, the above equation becomes simple, and becomes dφc(t)/di = -(K, 2A2/4) .f'' h (t-r) sinφc(r)dr.

When t→■, the right side becomes 0, and the phase error φC(1)
is always 0, and the system is in a steady state.

Therefore, even if the carrier frequency is hopping, the system settles into a steady state, so the cutoff frequency of the loop filter can be arbitrarily lowered, and carrier demodulation that is resistant to interference can be performed.

However, for this purpose, the frequency hopping pattern of the input signal and the frequency hopping pattern signal φd (t) applied to the adder 54 must be synchronized.
To do this, the bit synchronization signal and frame synchronization signal must be extracted in advance.

To extract these synchronization signals, the frequency hopping pattern may be demodulated using a PLI FM demodulator that uses a normal Costas loop and has a loop filter with a high cutoff frequency and a large loop gain.

That is, in FIG. 6, the switch 60 is in the up position and the switch 61 is in the open state.

The FM demodulated signal in this state passes through a correlator 62 for extracting a sweep pattern signal for frame synchronization, and a frame synchronization signal is extracted.

Incidentally, at this time, the bit synchronization signal has already been extracted by the PLL 66 shown in FIG.

Expressing it in the same way as the steady state, dφc(t)/dt -2(dφa (t)/dt-ωf -KIK2　A25inφc(t)/8)...(3) becomes.

Since the cutoff frequency of the loop filter is high, P L
L becomes steady in a short time, and the angular frequency of the VCO matches the angular frequency ωa of the input signal.

At that time, the above formula is dφc(t)/dt =〇-2(ωa-ωf (KI K2 A2/8) ・sinφc(t))・
...(4) becomes.

In other words, the phase error φc (t) becomes a constant φ, and si
nφk −8(ωa al f ) / KIK2
A2...(5) It becomes.

That is, in a steady state during acquisition, the phase error signal has an amount proportional to the difference between the angular frequency ωa of the input signal and the free running angular frequency ωf of the VCO.

In this state, the operation of extracting the frame synchronization signal from the FM demodulated signal is "capturing".

As is clear from equation (5), during acquisition, the error signal does not become O except when the angular frequency of the input signal matches the free-running angular frequency of the VCO, and at the end of the lock range, the error signal becomes φ ±π/
It becomes 2.

When φ = o, switching the Costas loop from acquisition to tracking steady state by switching switches 60 and 61 causes the cutoff frequency to be very low, i.e. the impulse response h (B is chosen so that it lasts for a long time). Because of the loop filter 57, the system does not remain in a steady state for a long time and becomes unstable.

On the other hand, if the same operation is performed when φ=o, the system starts from a steady state and is stable.

On the other hand, from the point of view of circuit implementation, the delay time in the loop is mainly determined by the multiplier 59 in the state at the time of acquisition and is relatively short.

Therefore, even if the loop gain is set high, the system remains stable and the lock range can be widened, which is convenient for acquisition.

However, in a steady state when the switches 60 and 61 are switched, the delay time between the adder and the loop filter is large, and if the loop gain is set high, the system becomes unstable.

In other words, if you want to make it more resistant to interference, you have to narrow the lock range, but in the steady state of tracking, the lock range does not need to be wide.

From the above, it is reasonable to switch the loop constant of the Costas loop between the capture and tracking steady states in terms of the feasibility of the circuit and the purpose of the SS system.

The receiving system is broadly divided into Costas loop PLLs 49 to 61, a correlator 62 for extracting sweep patterns, and frequency hopping pattern generators 63 to 65. It is divided into digital signal processing sections 66 to 76.

Assume that the initial setting state is such that the switch 60 of the Costas loop PLL is in the up position and the switch 61 is in the open state, which is a capture state.

The LPFs 55 and 56 are for carrier cutting, have a high cutoff frequency, and have a small delay time in the baseband. The frequency characteristics of the multiplier 59 are equivalent to those of a video amplifier, the delay time is small, and the gain is selected so that the lock range of the Costas loop PLL covers the width of the spectrum spread due to secondary modulation of the carrier.

From equation (5), the lock range is: 1ωa-ωf1 = l KI K2 From A25inφ/81, si
Since nφ=±1, lωa−a>f l=
IK, K2 A2/81・+6).

To expand the lock range, increase the input or loop gain.

At this time, if the delay in the loop is large, the system becomes unstable, the loop gain cannot be increased, and the range cannot be increased. However, in the acquisition state, the circuit constants are selected so that the delay time within the loop is small, so the desired lock range can be secured. When a target signal is input to the Costas loop phase-locked loop circuit in this state, the Costas loop phase-locked loop circuit first locks to the secondary modulated carrier and performs FM demodulation of the frequency hopping pattern that is the secondary modulation signal. A signal is output from the multiplier 59 and input to a correlator 62 for extracting a frequency sweep signal which is a frame synchronization pattern. In parallel with this, the PSKIJ tone signal, which is the -order modulation, is applied to the multiplier 51, which is the I axis of the Costas loop phase-locked loop circuit. vcx output from the LPF 56 and used for bit synchronization signal extraction.

The signal is input to the phase-locked loop circuit 66. The phase-locked loop circuit of this vcxo has a very short time from the start of locking to reaching a steady state, and reaches a steady state within several bits, so a bit synchronization signal can be obtained before extracting a frame synchronization signal. The correlator 62 for frequency sweep signal extraction is operated by the bit synchronization signal thus obtained.

The correlator 62 extracts from the FM demodulated signal from which noise and interfering signals have been removed, a feature in which the differential coefficients are of the same sign continuously over a long bit length, and a frequency sweep pattern is detected.

Meanwhile, in parallel, following bit synchronization signal extraction, P
The SK demodulated signal is followed by the -order modulated signal.

That is, the PSK demodulated signal is filtered by the integration dump filter 67 which operates using the bit synchronization signal described above.

After interference is removed, the output is input to the control section 66 and the descrambling circuit 70.

When the control unit receives the frequency sweep signal, that is, the frame synchronization signal extraction signal, from the correlator 62, it determines the frame position and selects the last bit, that is, the 16th bit of one frame, from the PSK demodulated frame synchronization signal. Bit 0 is detected, and the descrambling circuit 70° frequency hopping signal reproducing circuit 68 and deinter (1B)-leap circuit 71 are started from the 17th bit.

Descramble 709 frequency hopping playback circuit 68
The 10th-order and 7th-order PN generation circuits included in
It is the same as that included in the corresponding transmitter.

Following this (1 frame demodulation, descrambling.

The frequency hopping pattern signal is generated using this loop constant, that is, the acquisition constant.

When one frame is completed and demodulation of the second frame is started, the control section 66 sets the frequency sweep pattern of the frame synchronization signal section to the 8th or 9th bit where the frequency sweep pattern of the frame synchronization signal section is closest to the free-running frequency of the Costas loop phase-locked loop circuit. Switch 60 is turned down and switch 61 is closed to change the loop constant.

Attenuator 58. Loop filter 57. The adder 54 constitutes a reloop circuit.

The cutoff frequency of the loop filter is set low to make it resistant to interference, and since the adder 54 is implemented using an operational amplifier, the delay time is large. Under such conditions, increasing the loop gain will make the system unstable, so the attenuator 58 lowers the loop gain.

The adder 54 has already been connected to the D/A converter 6 before switching.
However, before the switch 61 is closed, there is no input to the attenuator 58, so both the input and the output of the loop filter 57 are constantly at O. It is in a state of

In this state, if an error signal of a certain level is output to the multiplier when the loop constant is changed by the switches 60 and 61, the cutoff frequency of the loop filter 57 is set low and the loop gain is lowered. Since the lock is locked, it takes a long time for it to become unlocked or to reach a steady state.

However, the frequency sweep pattern No. 8. Alternatively, since the 9th bit is close to the free-running frequency of the Costas loop phase-locked loop circuit, the error signal output from the multiplier 59 is approximately O, and even if the loop constant is changed, no transient phenomenon occurs in the loop filter 57. do not have.

Furthermore, as is clearer from (2), if the loop filter force sinφC(τ) is −■〈τ〈t and O, then from now on,
φc (t)=Q constantly, and the Costas loop phase-locked loop circuit is in a steady state regardless of carrier frequency hopping due to secondary modulation.

The Costas loop phase-locked loop circuit itself is PS
In order to track carriers that have no information on which the phase information by K has been erased, the cutoff frequency of the loop filter can be lowered arbitrarily, and carriers on which information has been erased can be stably extracted even under interference.

On the other hand, if the carrier is stably extracted, the PSK demodulated component output from the axis (1) of the Costas loop phase-locked loop circuit will be correlated by the integral dump filter 67 even if it is considerably disturbed by interference. , stable tlm is possible.

(Effect of the invention) Conventional direct-sequence SS with fixed carrier frequency
In the system, the phase error signal was almost 0 regardless of the loop constant, so switching the loop constant was easy.

0 to frequency hopping method with better frequency utilization efficiency
However, according to this method, a phase-locked loop circuit having a narrowband loop filter can be used, similar to the direct-sequence method, and the circuit can be simplified and strong anti-jamming characteristics can be obtained.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a signal frame structure of an embodiment of a spread spectrum communication system according to the present invention. FIG. 2 is a detailed diagram of the frame pattern. FIG. 3 is a block diagram showing an embodiment of a transmission system of a spread spectrum communication system according to the present invention. FIG. 4 is a block diagram showing an embodiment of a receiving system of a spread spectrum communication system according to the present invention. FIG. 5 is a detailed block diagram of a modulator for a spread spectrum communication system according to the present invention. FIG. 6 is a block diagram showing a cabinet system including the Costas loop PLL portion of the reception system of the spread spectrum communication system according to the present invention. FIG. 7 is a circuit diagram for explaining the operation of the Costas loop phase-locked loop circuit of the receiving system of the spread spectrum communication system according to the present invention. 1...Bit synchronization signal 2...Frame synchronization signal 3...Audio signal human power 4...Data signal human power 5
...Pre-emphasis circuit 6...Low pass filter 7...A/D converter 8...ADM 9...Encoder 10...Error correction code addition circuit 11...Interleaving circuit 12... Scramble circuit 13... Hopping pattern generation circuit 14... Phase modulator (PSK) 15.16... RF ratio output 17... Capture circuit 18
... PSK demodulator 19 ... Hopping pattern regenerator 20 ... Descramble circuit 21 ... Bit synchronization signal 22 ... Frame synchronization signal 23 ... Deinterleave circuit 24 ... Error correction circuit 25・・・Decoder 26・
...D/Ai converter 27...Low pass filter 2B
...De-emphasis circuit 29...Data signal 30...Audio output 31
．． 35...Bit synchronization signal 32.34...Frame synchronization signal 33...Bit stream 36...RAM37
...Interleave circuit 38...Frame synchronization control section 39...Polynomial circuit 40...PN generation circuit 41.42...Switch 43...D/A converter 44...Hold circuit 45.・vCO46・
...Phase shifter 47...Switch 48...
RF ratio output 49...RF input 50.51...
- Multiplier 52... Phase shifter 53... VCO 54
... Adder 55.56 ... Low pass filter 57 ... Loop filter 5B ... Attenuator 59 ... Multiplier 60.
61...Switch 62...Correlator 63...Hold circuit 64...D/A converter 65...A
FC66... PLL 67... Integral dump filter 68... Frequency hopping regeneration polynomial circuit 69...
Control unit 70... Descramble circuit 71... Deinterleave circuit 72... Control signal 73... Frame synchronization signal 74... Bit control signal 75... Control signal 76... Bit stream patent application Person Kyocera Co., Ltd. Agent Patent Attorney Hisashi Inoro Procedure Amendment July 5, 1985 Patent No. 1 No. 111920 2, Title of Invention Spread Spectrum Communication System 3, Person Making Amendment Case Relationship between patent applicant 4, agent 6, subject of amendment Contents of amendment to the description (Japanese Patent Application No. 6O-111920) (1) The scope of claims is amended as follows. ``2. Claims: In a frequency hopping coherent detection type spread spectrum communication system, there is provided a Costas loop PLL having a narrowband loop and a normal loop for frequency hopping, an offset signal casing, and a frame synchronization and synchronization thereto. Spread spectrum communication characterized in that it is configured by providing a control circuit that starts a frequency hopping pattern and a PN for scrambling at the first frame synchronization when acquiring a carrier of the frequency sweep pattern, and switches a loop constant at the second frame synchronization. (2) "Signals are added" in lines 10 to 11 of page 3 of the specification is corrected to "signals are being added." (3) Change “Generate polynomial” on page 5, line 11 of the specification to “
Extract sync signal”. (4) "corresponds to 10 of rPSK modulation" in the first line of page 10 of the specification is corrected to "each corresponds to 1.0 of PSK modulation". (5) r sinφC(t) on page 11, line 4 of the specification
dτ)” is corrected to r sinφc (r)clr)J. (6) After “dτ” on page 11, line 16 of the specification, “・
...(2)" is added. (7) In the first line of page 12 of the specification, change “because it calms down” to “
I am calm, so I am corrected. (8) In r- on page 13, line 5 of the specification, 2A2si
nφc (t) /8) J to r−(K, K2A2/
8) Correct to sinφc(t))J. (9) “-0” to “φ” in 1φ on page 14, line 11 of the specification
≠0”. That's it - Riri 7 -

Claims (1)

[Claims] In a frequency hopping/coherent detection spread spectrum communication system, a Costas loop PLL has a narrowband loop for adding an offset signal for frequency hopping and a normal loop, and a Costas loop PLL for frame synchronization and carrier capture for a frequency sweep pattern synchronized with the frame synchronization. A spread spectrum communication system comprising a control circuit that starts a frequency hopping pattern and a PN for scrambling at frame synchronization and switches a loop constant at second frame synchronization.