JPS61269417A - Complementary mos semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent the destruction of an integrated circuit by connecting a resistor in series between a power terminal and a power line so as to block a large current flow even when latchup takes place in the integrated circuit in a complementary MOS semiconductor integrated circuit including plural P and N-channel MOSFETs constituted on a semiconductor substrate. CONSTITUTION:The resistor 3 is connected in series between the power line 1 and the power terminal 2 of the complementary MOS circuit. In general, the complementary MOS circuit has less current consumption and a wide operating power range. When the resistor 3 is 10OMEGA and the current consumption of the complementary MOS circuit in operation in 1mA, the voltage drop of the resistor 3 is 10mV and it gives no effect on the operation of the complementary MOS circuit. If power supply voltage is 5V, a current flowing from the power terminal 2 to the ground potential Vss is limited when the resistor 3 is connected between the power terminal 2 and the power line 1 and the current with latchup is limited to 500mA or below with the power supply voltage 5V and resistor 3 of 10OMEGA. In designing the pattern of the integrated circuit as 500mA, no destruction is caused.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to complementary M (JS) type semiconductor integrated circuits, and particularly to prevention of destruction of complementary MOS type semiconductor integrated circuits due to latch-up.

[Conventional technology]

In conventional complementary MOS type semiconductor integrated circuits, power supply terminals and power lines are directly connected through a conductor such as aluminum.

[Problem that the invention seeks to solve]

In the conventional complementary MOS type semiconductor integrated circuit described above, the power supply terminal and the power supply line are directly connected, so that if latch-up occurs inside the integrated circuit, a large current will flow and the integrated circuit will be destroyed.

Next, the latch-anozo phenomenon will be explained using the cross-sectional view of FIG. In FIG. 2, a Nu well region 12 is formed in a P-type substrate 11. As shown in FIG. In this well region 12, P
P+ type regions 14 and 15 which become the drain and source of the channel MOf9FET 13 and an N+ type region 16 for making contact from the well region 12 are formed, and a gate electrode 17 is further formed on the surface between the P+ type regions 14 and 15. It is formed.

Further, an N+ type region 1920 which becomes the source and drain of the N channel MOSFET 18 is formed in the P type substrate 11, and a gate electrode 21 is formed on the surface between the N++ regions 19 and 20. Both the r-group region 15 and the M-type region 16 are set to the positive power supply potential VDD, and the one N+-type region 19 and the P-type substrate 11 are both set to the ground potential Va8.

In such a configuration, if for some reason the potential of the drain (P+ type region 14) of the P channel MOSF'ET 13 becomes higher than vDD than the forward voltage Vf of the PN junction, the P+ type region 14 becomes the emitter and the N type well. Area 1
A parasitic particle PNP transistor (not shown) having P-type substrate 11 as a base and P-type substrate 11 as a collector is turned on. When this PNP transistor is turned on and a collector current flows, this current flows into Vjljl via the resistor Rp present in the P-type substrate 11. At this time, due to the voltage drop that occurs in this resistance section, the parasitic lateral NPN transistor Qμ, which has the N-type well region 12 as the collector, the P-type substrate 11 as the base, and the N+-type region 19 as the emitter, turns on. . The collector current of Qμ is supplied from vDD via a resistor Rμ existing in the N-type well region 12. At this time, the voltage drop generated across the resistor turns on the parasitic particle PNP transistor Q, which has the P+ type region 15 as its emitter, the N-type well region 12 as its base, and the P-type substrate 11 as its collector. As a result, the PNPN thyristor constituted by a combination of both the above parasitic transistors is turned on, and the voltage from s vDD to V811 is turned on.
A large current continues to flow through the circuit, rendering the entire circuit inoperable. Such a state is called latch-up. In addition, the above latch-up is caused by the N-channel MO
The potential of the drain of SFET 18 (N-type region 20) is V
This also occurs when the forward voltage Vl of the PN junction becomes lower than 88.

[Means for solving problems]

The present invention has been made in view of the above circumstances, and its purpose is to provide a complementary MOS type semiconductor integrated circuit in which a large current does not flow even if latch-up occurs inside the integrated circuit, and the integrated circuit is not destroyed. It is about providing.

The complementary MOS type semiconductor integrated circuit of the present invention includes a plurality of P-channel and N-channel MOSs configured on a semiconductor substrate.
In a complementary MOS type semiconductor integrated circuit including 1i'ET, a resistor is connected in series between a power supply terminal and a power supply line.

〔Example〕

The present invention will be explained with reference to the drawings. FIG. 1 shows an embodiment of the present invention, in which a resistor 3 is connected in series between a power line 1 and a power terminal 20 of a complementary MOS circuit. The resistor 3 is formed of polycrystalline silicon on a semiconductor substrate, or is formed by a method such as impurity diffusion or ion implantation into the semiconductor substrate.

Generally, complementary MOS circuits consume less current and have a wide operating power supply range. Therefore, the value of the resistor 3 is set to lOΩ, and the complementary M0.
Assuming that the current consumption during operation of the 9 circuits is 1 mA,
The voltage drop across this resistor 3 is 10 mV and does not affect the operation of the complementary M08 circuit.

In addition, if the power supply voltage is 5■ and the resistor 3 is not present when latch-up occurs, and the power supply terminal 2 and the power supply line 1 are directly connected, then the voltage from the power supply terminal 2 to the ground potential VB1i is A large current of A flows and destroys the integrated circuit. However, if the resistor 3 is connected between the power supply terminal 2 and the power supply line 10, the current flowing from the voltage source terminal 2 to the ground potential Va8 is limited, and when the power supply voltage is 5V and the value of the resistor 3 is lO
Ω, the current when latte-up occurs is 500
Limited to mA or less. Here, the integrated circuit pattern is 5
If it is designed with 00 mA, it will not be destroyed.0 [Effects of the Invention] As explained above, the present invention prevents latch-up from occurring by connecting a resistor in series between the power terminal and the power line. This has the effect of limiting the current when Therefore, according to the present invention, it is possible to realize a complementary MOS type semiconductor integrated circuit that will not be destroyed even if latch-up occurs.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention. FIG. 2 is a sectional view of a complementary MOS type semiconductor integrated circuit for explaining the present invention. 1... Complementary M08 circuit power line, 2...
・Power terminal, 3...Resistance, 11...P
type semiconductor substrate, 12...Nfi well region, 1
3...P channel MOSFET. 14...Drain of P channel MOSFET,
15...P-channel MOSFET source, 1
6...N-type well region power contact, 17
...P channel MOSF'ET'l -)
, 18 =-...Nf Yarnel M08FET. 19-=-N channel MOSFETtD 7-s, 20
, =...Drain of N-channel MOSFET T, 2
1...Gate of N-channel MOSFET. 2nd f, 2nd

Claims (1)

[Claims] A complementary MOS type semiconductor integrated circuit including a plurality of P-channel and N-channel MOSFETs configured on a semiconductor substrate, characterized in that a resistor is connected in series between a power supply terminal and a power supply line. .