JPS61269071A - Period detection circuit - Google Patents

Abstract

PURPOSE:To perform a stable standing detection by comparing a first memory means for storing a value in accordance with a period corresponding to a rotational speed in response to a pulse having said period and a second memory means for storing the value of the period when the period becomes several times longer with each other. CONSTITUTION:A function generating circuit 4 is operated in response to a pulse with a period in accordance with a rotational speed and, after sampled by a gate circuit 6, the output of the circuit 4 is stored in a first capacitor 7 and indicated by a tachometer. On the other hand, a voltage equal to that obtained when the period of the pulse becomes several times longer is established by a resistor 12 and the value sampled from the voltage is stored in a second capacitor 14. The value (capacitance) of the second capacitor 14 is compared with that of the first capacitor 7 by a comparator 16 and, when the latter value becomes larger than the former one, a switch circuit 17 is turned off. Therefore, by removing the deflection of the pointer of the tachometer when stopped, a stable standing detection can be performed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to period detection, which is performed by detecting the period of a pulse whose period corresponds to the rotation speed of a mechanical device such as a belt conveyor. The present invention relates to circuits, and particularly to circuits that can effectively detect stoppages at very low speeds.

[Background technology and its problems]

When detecting the speed of rotation, the period of the pulse from a pulse generator that generates pulses with a period corresponding to the speed of rotation is generally converted into voltage and used as an indicator of the rotation speed meter. The robot is instructed to read the instructions.

However, in this case, when the rotation speed becomes low, the period of the pulse from the pulse generator becomes longer, so the pointer of the rotation speed indicator vibrates, making it difficult to read the indication accurately. In order to avoid this drawback, a capacitor of large capacity is connected, but this method has the disadvantage that the response speed of the rotation speed meter decreases.

Therefore, the applicant has previously provided a device that does not have such drawbacks.

FIG. 1 shows an example. In the same figure, (
1) is an input terminal, and a pulse PI with a period corresponding to the rotational speed from the pulse generator is supplied to the monostable multipipe rake (2) through this input terminal (1), from which a pulse synchronized with the pulse PI is supplied. PS (Figure 2A) is obtained.

This pulse PS is supplied to a monostable multivibrator (3), from which a pulse PR (FIG. B) in which the pulse PS is slightly delayed is obtained, and this pulse PR is 1/T.
(T is period) is supplied to the function generating circuit (4) as its reset pulse. This L/T function generating circuit (4) outputs a predetermined voltage E at the time of reset by the pulse PR.
M, and from this point until the arrival of the next reset pulse, a downward sawtooth wave output SA (C in the figure) is obtained which hyperbolically decreases from the voltage EM according to the period T of the input pulse PI. Therefore, this output SA is the pulse P
Immediately before being reset by R, the peak value of the downward sawtooth wave in the figure is a voltage corresponding to the period of the large force pulse PI.

The output SA of this function generating circuit (4) is supplied to a sampling gate circuit (6). Then, the pulse Ps from the monostable multi-by-break (2) is the OR gate (5)
is supplied to this sampling gate circuit (6) through the pulse Ps, and the output SA is sampled by the pulse Ps.
The sampled voltage is stored in a capacitor (7). Since the pulse Ps is a pulse immediately before the reset pulse PR, what is sampled by the gate circuit (6) is the downward peak value voltage of the sawtooth wave voltage SA according to the period of the input pulse PI, as described above. , this will be stored in the capacitor (7). This capacitor (7)
The voltage SHo (solid line in the figure) stored in is supplied to the indicator (9) through the buffer amplifier (8).

Therefore, the pointer of the indicator (9) corresponds to the voltage sHo.

The output of the buffer amplifier (8) is also supplied to the comparison circuit αΦ, while the output SA of the function generation circuit (4) is supplied to this comparison circuit αΦ, which makes the output SA lower than the voltage SHo. In such a case, a comparison output SC (Fig. 2 E) that becomes high level is obtained, and this is the OR gate (5).
During the high level period of the output SC, this gate circuit (6) is opened, and the voltage SHo of the capacitor (7) is as shown by the solid line in the second diagram. It changes hyperbolically according to the output SA. The output SC of the comparison circuit Ql becomes high level when the speed decreases and the period of the input pulse PI becomes longer. Therefore, according to the circuit shown in FIG. 1, the pointer of the indicator (9) does not vibrate even when the speed decreases and the period of the input pulse PI becomes longer, and the pointer maintains the speed. The runout changes sequentially to follow the decrease, making it possible to detect even extremely low speeds. By the way, when the above-described period detection circuit is also used as a stop detection circuit, there are the following drawbacks.

That is, in the circuit of FIG. 1, as the speed decreases and the period T becomes longer, the output SA decreases hyperbolically, and the voltage SHo obtained at the capacitor (7) also corresponds to this. If a large force pulse PI arrives even when the speed decreases as shown in Figure 2, the voltage SH of the capacitor (7) will become a low voltage corresponding to the period T at that point.
o is held and displayed on the pointer of the indicator (9).

However, if the input pulse always arrives like this, there is no problem, but when the rotation etc. suddenly stops and the input pulse PI does not arrive, the voltage SHo becomes the output of the function generation circuit (4). This follows the hyperbolic decrease in SA. Since this descending hyperbola has an output of an asymptotic image in practice, the deflection of the pointer does not go to zero even if the rotation or the like suddenly stops, making it inconvenient to detect the stop.
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l. Invention. overview,
1. Normally, mechanical devices such as comparators, which are subject to speed tests such as rotational speed, do not fluctuate in speed very rapidly when in use, and the speed is changed gradually by operating a variable transmission or the like. However, the periodic change of the large force pulse rarely exceeds two times, and only when a sudden stop occurs due to some kind of accident, the period of the human power pulse changes by more than three times.

Therefore, in the present invention, a means is provided for setting a value corresponding to the period when the period of the input pulse suddenly changes and becomes several times longer, and the output of this setting means is synchronized with the input pulse PI.
It is stored in the storage means at the time of the pulse of the same period, and changes according to the stored value of the storage means and the period of the high-force pulse, and moreover, when the period of the input pulse becomes longer, it changes according to the change in the longer period. A stop detection signal is obtained as the comparison output.

〔Example〕

FIG. 3 shows an example of the present invention, in which a stop detection circuit section is added to the period detection circuit of FIG. 1.

That is, in this example, the output of the buffer amplifier (8) is voltage-divided by the resistors (11) and (12). For example, the resistor (12) is adjusted, and the voltage obtained at the connection point of these resistors (11) and (12) is set to 1/3 to 115 of the output voltage value of the buffer amplifier (8). That is, when the period of the input pulse P2 suddenly changes and becomes 3 to 5 times longer than the previous stable state, it is set to the same value. This voltage value is determined by the sampling gate circuit (
13), is sampled by a pulse PS in this gate circuit (13), and the sampled value is stored in a capacitor (14). The storage output voltage SHs (dotted chain line in the second figure) of this capacitor (14) is applied to the comparator circuit (16) through the buffer amplifier (15).
). The comparison circuit (16) is also supplied with the output of the buffer amplifier (8). therefore,
This comparison circuit (16) outputs a comparison output STP which becomes high level when the storage output voltage of the capacitor (7) becomes lower than the storage output voltage SHs of the capacitor (14).
(FIG. 2F) is obtained. In other words, this comparison output ST
P becomes a high level when the input pulse PI suddenly has a long cycle that can be regarded as a sudden stop of the subject, and this is simply a stop detection signal.

In this example, when a stop is detected, the pointer of the indicator is set to indicate zero, and therefore the output of the buffer amplifier (8) is passed through the switch circuit (17) to the buffer amplifier (
18), an output terminal (19) is led out from this buffer amplifier (18), and a signal obtained at this output terminal (19) is supplied to an indicating instrument. Then, the switch circuit (17) is controlled by the output STP of the comparison circuit (16), and when the stop is detected, the output ST
When P becomes high level, the switch circuit (17) is turned off.

Note that when the stop detection output STP becomes high level and the speed of the subject increases after the stop is detected and then returns to the original speed, a short-cycle input is required as shown by the dotted line in Figure 2. As the pulse arrives, the voltage of the capacitor (7) immediately rises as is clear from Figure 2, so the output STP falls to a low level and the switch circuit (17
) is turned on, and thereafter period detection is performed in exactly the same way as in the steady state.

Note that the signal obtained at the output terminal (19) is not limited to being supplied to an indicating instrument, and may be used as one of the inputs of a computer that controls the operation of a mechanical device that is a subject, for example.

Although the example in FIG. 3 is an example of an analog configuration, the present invention can also be configured digitally.

However, the present invention can perform all the above operations through software processing using, for example, a microcomputer. For ease of explanation, an example of this digital configuration will be explained with reference to the hardware and the flowchart of its essential parts in FIG.

In FIG. 4, (21) is a counter as a function generating circuit for period detection, and a clock pulse CP having a sufficiently higher frequency than the input pulse PI is supplied to the clock terminal through a terminal (22). Then, as mentioned above, in synchronization with the input pulse PI, the same periodic pulse PR is applied to the terminal (2
3) to the reset terminal of this counter (21). Therefore, the count value of this counter (21) corresponds to the period length of the pulse PR. The count value output CNT of this counter (21) is stored in the memory
(24), and the pulse Ps just before the pulse PR is supplied from the terminal (25) to this memory (24) through (26), and this pulse Ps
The count value at the moment , and thus just before being reset by the pulse PH, is stored in this memory (24). The stored value M in the memory (24) of this ;
1 is supplied to the comparator circuit (27) and compared with the output count value CNT of the counter (21).
When 1≦CNT, the AND gate (28) is opened by the output of this comparison circuit (27), and this AND gate (28) is opened.
) A clock pulse CP is obtained through (28), which is supplied to the memory (24) through the OR gate (2B), and the contents of the memory (24) are sequentially rewritten to the count value CNT by the pulse CP.

The stored value in the memory (24) thus obtained corresponds to the output value of the capacitor (7) in FIGS. 1 and 3.

The value stored in the memory (24) is supplied to a multiplication circuit (29), where the value is multiplied, for example, by three, and the tripled value is stored in the memory (30) by means of a pulse PS.

Therefore, the value M2 stored in this memory (30) corresponds to the value when the period of the input pulse suddenly becomes three times longer. Memory value M2 of that memory (30) and memory (24)
is compared with the stored value Ml in the comparator circuit (31),
When M 2 <M t (=CNT), a stop detection signal is obtained from this comparison circuit (31).

FIG. 5 shows that the period of the input pulse has become longer than the previous period, so that the stored value M1 in the memory (24) follows the count value CNT of the counter (24), and the period has become more than three times longer. 12 is a flowchart showing how to detect a stop when

〔Effect of the invention〕

As described above, the present invention takes advantage of the fact that mechanical devices, which are the objects of speed detection, generally do not have very rapid speed fluctuations during normal use, and a sudden speed decrease can be regarded as a stoppage. As a result, it is determined that a stop is detected when the period of the pulse to be measured, which is the input pulse, suddenly becomes several times longer, thereby eliminating the drawbacks of the conventional method.

Furthermore, the present invention has the advantage that the circuit for detecting this stoppage can be of a simple configuration that only includes a detection level setting circuit, a storage circuit, and a comparison circuit.

[Brief explanation of the drawing]

Fig. 1 is a system diagram of an example of a conventional period detection circuit, Fig. 2 is a waveform diagram for explaining the same and a detailed explanation of the present invention, Fig. 3 is a system diagram of an example of the inventive circuit, and Fig. 4 is a system diagram of another example of the present invention, and FIG. 5 is a flowchart showing the operation of the main part thereof. (1) is the input terminal of the pulse to be measured, (2) is the monostable multivibrator that obtains the first pulse, (3) is the monostable multivibrator that obtains the second pulse, (4) is 1/T
A function generating circuit, (6) and (13) are sampling gate circuits, (7) and (14) are capacitors as storage means, and αΦ and (16) are comparison circuits. Figure 4 Figure 5

Claims (1)

[Claims] In a period detection circuit that receives a pulse to be measured and outputs a value corresponding to the period, a first storage means stores a value corresponding to the period, and the immediately preceding storage contents from the first storage means are stored. A second storage means for storing a value multiplied by a set value, and a comparison means for obtaining a stop detection output when the stored value of the first storage means becomes larger than the stored value of the second storage means. Period detection circuit.