JPS61265863A - Photoelectric conversion device - Google Patents

Abstract

PURPOSE:To simplify the manufacturing process of the titled device in a high degree as well as to enable to form the semiconductor of the main electrode region which comes in contact with an isolation region by a method wherein at least the main part of the isolation region, with which each cell of the photoelectric conversion device is electrically isolated, is formed in the structure wherein the main part is buried at the position deeper than the surface where light is received. CONSTITUTION:An N<-> epitaxial layer 7 is formed on an N-silicon substrate 1, the N<+> buried layer 5 which serves as an element isolation region is formed in the layer 7, and photosensors which are electrically insulated each other are arranged. Each photosensor cell is constituted in such a manner that the polysilicon 10 to be used for a capacitor electrode, an electrode 12 and an electrode 12' are formed on an N<-> epitaxial layer 7 pinching the P-base region 8 of a bipolar transistor, an N<+> emitter region 9 and a gate oxide film 11, and an electrode is formed on the back side of the substrate 1 through the intermediary of the N<+> region having high density of impurities. The expansion of the depletion layer 17 generating between the P-base region 8 and the N<-> epitaxial layer 7, which is a collector region, is suppressed by the N<+> buried region 5.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a photoelectric conversion device that accumulates carriers excited by light and controls the output based on the accumulated voltage, and particularly relates to a photoelectric conversion device that has a high aperture ratio and a high concentration. The present invention relates to a contemplated photoelectric conversion device.

[Prior Art] FIG. 4(A) is a plan view of a photoelectric conversion device described in JP-A-80-12759 to JP-A-80-12785, and FIG. It is a sectional view taken along the line I-I.

In both figures, optical sensor cells are formed and arranged on an n+ silicon substrate 101, and each optical sensor cell is 5i0
It is electrically insulated from adjacent photosensor cells by an element isolation region 102 made of 2, Si3N4, polysilicon, or the like.

Each optical sensor cell has the following configuration.

Low impurity concentration n formed by epitaxial technology etc.
A p region 104 is formed on the − region 103 by doping p-type impurities, and an n+ region 104 is formed on the p region 104 by impurity diffusion technology or ion implantation technology.
5 is formed. p region 104 and n middle region 10
5 are the base and emitter of a bipolar transistor, respectively.

An oxide film 106 is formed on the n- region 103 in which each region is formed in this way, and a capacitor electrode 107 having a predetermined area is formed on the oxide film 10G. Capacitor electrode 107 faces P region 104 with oxide film 108 in between, and applies a pulse voltage to capacitor electrode 107 to control the potential of p region 104 in a floating state.

In addition, the emitter electrode 1 connected to the n medium region 105
08, wiring 109 for reading signals from the emitter electrode 108 to the outside, wiring 11 connected to the capacitor electrode 107
0, n+ region 11 with high impurity concentration on the back surface of the substrate 101
1 and an electrode 112 for applying a potential to the collector of the bipolar transistor.

Next, the basic operation will be explained. Light 113 enters the p-region 104, which is the base of the bipolar transistor, and a charge corresponding to the amount of light is accumulated in the p-region 104 (accumulation operation).The base potential changes due to the accumulated charge, and the potential change is reflected in the floating By reading out from the emitter electrode 108 in the state, an electric signal corresponding to the amount of incident light can be obtained (readout operation).Also, in order to remove the charge accumulated in the p region 104, the emitter electrode 108 is grounded. death,
A pulse of positive voltage is applied to capacitor electrode 107 (refresh operation). By applying this positive voltage, p region 104 is forward biased with respect to n medium region 105, and accumulated charges are removed. Thereafter, the above-described storage, readout, and refresh operations are repeated.

In short, the method proposed here accumulates charges generated by light incidence in the p-region 104, which is the base, and
The current flowing between the emitter electrode 108 and the collector electrode 112 is controlled by the amount of accumulated charge. Therefore, the accumulated charge is amplified by the amplifier section of each cell before being read out, resulting in high output and high sensitivity.

Even lower noise can be achieved.

Further, the potential Vp generated at the base due to holes accumulated in the base due to photoexcitation is given by Q/C. Here, Q is the R'lR amount of holes accumulated in the base, and C is the capacitance connected to the base. As is clear from this equation, in the case of high integration, both Q and C become smaller as the cell size decreases, and the potential Vp generated by photoexcitation.

It can be seen that it remains approximately constant. Therefore, it can be said that the method proposed here is advantageous for higher resolution in the future.

[Problems to be Solved by the Invention] In general, in photoelectric conversion devices, it is desirable to effectively utilize the cell surface due to the demand for improved sensitivity and higher resolution.However, in this respect, conventional photoelectric conversion devices It wasn't enough.

In the conventional photoelectric conversion device described above, the element isolation region 102 that electrically isolates each cell is made of dielectric material (for example, Si02, etc.).
, the aperture ratio and photoelectric conversion efficiency were substantially lowered without contributing to the photoelectric conversion operation.

In addition, the process of forming the dielectric wall is complicated, and
-''The problem of impairing the crystallinity of the side wall portion of the epitaxial N103 was solved.

Another problem is that stress occurs between the dielectric and the epitaxial single crystal, resulting in leakage current.

Furthermore, if the dielectric walls are made to be high, cracks are likely to occur, making it impossible to form deep element isolation regions, resulting in crosstalk.

Furthermore, if the element isolation region is formed using a semiconductor using an impurity diffusion method instead of a dielectric material, the lateral spread of impurities is large, which hinders high integration, and depending on the positional relationship, problems such as deterioration of the breakdown voltage of the element may occur. It had a point.

[Means for Solving Problems 1] In order to solve the above conventional problems, a photoelectric conversion device according to the present invention has two main electrode regions made of a semiconductor of one conductivity type and a control electrode made of a semiconductor of an opposite conductivity type. A photoelectric conversion device including a plurality of photoelectric conversion cells arranged in a semiconductor transistor comprising a semiconductor transistor region, which accumulates carriers excited by light in the control electrode region, and controls output according to the accumulated voltage; The isolation region for electrically isolating the photoelectric conversion cells is composed of a semiconductor region that has the same conductivity type as the main electrode region of the photoelectric conversion cell and has a higher concentration than the main electrode region to which they are connected, and at least The main portion is buried deeper than the light-receiving surface of the semiconductor transistor.

[Function] By configuring the isolation region in this way, the manufacturing process is extremely simplified, and the semiconductor in the main electrode region that connects to the isolation region can be formed without impairing crystallinity, resulting in more complete element isolation. It can be achieved.

Furthermore, since at least a major portion of the separation region is buried, the substantial aperture ratio of the light-receiving surface can be increased, allowing for higher density integration.

[Example] Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1(A) is a plan view of one embodiment of a photoelectric conversion device according to the present invention, and FIG. 1(B) is a sectional view taken along line A--A of one of the cells.

In both figures, an n″″″ epitaxial layer 7 is formed on an n silicon substrate 1, and optical sensor cells are arranged therein, which are electrically insulated from each other by an n buried region 5 that serves as an element isolation region. .

From the viewpoint of miniaturization, the element isolation region is a region that lowers the aperture ratio and reduces the effective photoelectric conversion efficiency, so in this example, it is not formed on the surface of the element, but is formed as a buried layer.

Each sensor cell has a p base region 8 and an n+ emitter region S of a bipolar transistor on an n- epitaxial layer 7.

A polysilicon electrode 10, which is a capacitor electrode for applying a pulse to the p base region 8, and an electrode 1 connected to the n+ emitter region 9 sandwich the gate oxide [111].
2. The electrode 12' is connected to the polysilicon 10, and an electrode for applying a potential to the collector of the bipolar transistor via the n+ region with high impurity concentration on the back surface of the substrate 1.

As already mentioned, the basic operation of this embodiment is as follows: First, the P base region 8 in the initial state biased to a negative potential is brought into a floating state, and the holes of the electron-hole pairs generated by photoexcitation are transferred to the P base region 8. Accumulate in area 8 (accumulation operation), then
The emitter-e-base is biased in the forward direction, and the accumulated voltage generated by the accumulated holes is read out to the floating emitter side (readout operation).The emitter side is grounded, and the polysilicon capacitor electrode is By applying a positive voltage pulse to 10, the holes accumulated in the p base region 8 are removed to the emitter side (refresh operation).
By removing the accumulated holes, the p base region 8 enters an initial state biased to a negative potential at the time when the positive voltage pulse for refreshing falls. A broken line 17 shows how the depletion layer spreads in this initial state.

In this way, by providing n0 embedded regions 5,
The expansion of the depletion layer 17 generated between the p base region 8 and the n-epitaxial layer 7, which is the collector region, can be suppressed, and crosstalk can be prevented. because,
A strong electric field exists within the depletion layer 17, and as long as the depletion layers do not touch each other, or even if they do, if a potential wall is effectively formed between the cells, the electrons generated within the depletion layer
This is because the hole pairs are separated in opposite directions (holes toward the base and electrons toward the collector) without recombining.

Furthermore, since the isolation region is embedded, the substantial aperture ratio can be increased, and cells can be arranged at high density.

FIGS. 2(A) to 2(E) are manufacturing process diagrams of this example.

First, as shown in FIG. 2(A), the impurity concentration I
X 1015~5 X 1017 cm-3 (1) Impurity concentration IX 1017~ on the back surface of n-type silicon substrate l
An n+10 layer for ohmic contact of I x 102'cm-3 is formed by diffusion of P, As or sb.

Next, an oxide film 3 having a thickness of 6,000 to 10,000 thick is formed on the substrate 1 by a pyrogenic oxidation method, a wet oxidation method, or a steam oxidation method. Subsequently, the oxide film 3 in the portion where the element isolation region is to be formed is selectively removed to form the opening 4 [FIG. 2 CB].

Next, Sb or As is diffused from the opening 4, and
' [Figure (C)].

In order to form the n+ region 5', a method of heat treating the substrate 1 in an Sb atmosphere in which sb2 o 3 is sublimated, and a method similar to that of A
There are methods such as a method of heat treatment in a s atmosphere or a method of implanting As or Sb ions by ion implantation. Here, sb2 o 3 is heated to 800-800 °C in an auxiliary furnace to sublimate it, 02 and N2 are introduced into the furnace with the substrate as carrier gas, and this furnace is heated to 1100-1250 °C to sublimate 2-3 Thermal diffusion was performed for about an hour and good results were obtained.

Next, the oxide film 3 on the substrate 1 is peeled off and removed. Next, n
An oxide film 8 (for example, a Si02 film) having a thickness of 3,000 to 7,000 wafers is formed on the middle layer 2 by the CVD method. This oxide film 6 is called a back coat and is used to prevent impurity vapor from being generated when the substrate 1 is heat treated.

Subsequently, the surface of the substrate 1 was heated to a temperature of 1000°C and HCI was applied for 2 hours.
1/sin, H2 is approximately 1 under the condition of E101/win
．． After etching for 5 minutes, for example, the source gas SiH
2c+z (100%) at 1.2J1/win, doping gas (H2 diluted PH3, 20PPM) at 100
CC flow, growth temperature 1000℃, 120-180
Under vacuum (7 Torr).

n-epitaxial M7 (hereinafter referred to as n-layer 7)
form. At the same time as the n'''' layer 7 is formed, impurities are diffused from the n+ compensation region 5' to the n1 layer 7, and the n0 buried region 5 is formed.
That is, element isolation regions can be formed extremely easily. At this time, the single crystal growth rate was 0.51 m/win, the thickness was 2 to 10 gm, and the impurity concentration was I x 1012
~1016 Cm-3, better <Ha1012~10L'
am-3 [Figure (D)].

In order to improve the quality of n-layer 7, the substrate is first subjected to high-temperature treatment at 1150 to 1250°C to remove oxygen from near the surface, and then heat-treated at approximately 800°C for a long time to generate many micro-defects inside the substrate. It is also extremely effective to use a substrate that has a denuded zone and can perform intrinsic gettering.

A p base region 8 and an n+ emitter region 9 are added to the thus formed n layer 7 by a method such as ion implantation.
is formed, and a gate oxide film 11 is formed on the p base region 8.
Polysilicon 10, which is a capacitor electrode, is formed on both sides. Furthermore, the wiring 12' connected to the emitter electrode 12 and the polysilicon 10 across the interlayer insulation [13, 14],
Then, a protective film 15 and the like covering the entire element is formed [FIG. 3(E) 1°] FIG. 3 is a sectional view of another embodiment of the present invention. As shown in the figure, an n+ region 16 is formed by shallow diffusion on the surface of the n+ layer 7, and forms an element isolation region together with the n+ buried region 5. By providing the n medium region IB in this manner, contact between adjacent depletion layers can be more completely prevented. In addition, because it can be formed by shallow diffusion,
The lateral spread is small, and high integration can be achieved without reducing the aperture ratio.

In this embodiment, an n-level conductor is used in the element isolation region, but the invention is of course not limited to this, and a p-level conductor may be used in the case of a PNP bipolar transistor.

[Effects of the Invention] As explained in detail above, in the photoelectric conversion device according to the present invention, at least the main portion of the isolation region that electrically isolates each cell is embedded at a position deeper than the light receiving surface. The manufacturing process is extremely simplified, and the semiconductor in the main electrode region that is connected to one isolation region can be formed without impairing crystallinity, and more complete device isolation with less crosstalk, leakage current, etc. can be achieved.

Furthermore, since at least the main portion of the separation region is buried, the substantial aperture ratio of the light-receiving surface can be increased;
Furthermore, since the installation distance between each cell can be reduced, it is suitable for high integration.

[Brief explanation of drawings]

FIG. 1(A) is a plan view of one embodiment of a photoelectric conversion device according to the present invention, FIG. 1(B) is a sectional view taken along line A-A of one cell, and FIGS. 2(A) to ( E) is the manufacturing process diagram of this example, No. 3
The figure is a sectional view of another embodiment of the present invention, and FIG.
JP-A-80-12759 to JP-A-60-1278
Plan view of the photoelectric conversion device described in Publication No. 5, No. 4
Figure (B) is a sectional view taken along the line I-I. 1m m*n silicon substrate 5...n 10 buried region 7... 11n- epitaxial layer 8 30p base region 9...n 10 emitter region lO as polysilicon (capacitor electrode) 11...
Gate oxide film agent Patent attorney Seki Yamashita Children Figure 1 (A) Figure 1 (B) Figure 2 (A) (B) (C) Figure 2 (E) Figure 31!1

Claims (1)

[Claims] (1) It has a semiconductor transistor consisting of two main electrode regions made of a semiconductor of one conductivity type and a control electrode region made of a semiconductor of an opposite conductivity type, and carriers excited by light are accumulated in the control electrode region. In a photoelectric conversion device in which a plurality of photoelectric conversion cells are arranged to control output, a separation region for electrically isolating adjacent photoelectric conversion cells is of the same conductivity type as a main electrode region of the photoelectric conversion cells. A photoelectric conversion device comprising a semiconductor region having a higher concentration than a main electrode region to which the semiconductor transistor is connected, and at least a main portion of the semiconductor region is buried deeper than a light-receiving surface of the semiconductor transistor.