JPS61264822A - Pll circuit - Google Patents

Abstract

PURPOSE:To increase the detection sensitivity and to eliminate the effect to an analog circuit system by a low frequency current by connecting a current source to a filter being a component of a PLL circuit. CONSTITUTION:A current source consists of a transistor (TR) 12, a resistor 13 and a voltage source 14 and a minute current flows from a capacitor (filter) 11. Then the potential at a terminal 53 is lowered by the current flowing to the current source even at the lock state, the loop is operated to restore it to flow a current. A current with a shifted phase flows to TRs 37, 38 always for a period t1. The relation of TI1=t1I2 is established, where I1 is a current flowing to the current source, I2 is a current flowing from the TR 37, and T is the period of detection. In selecting a range v1 shown in arrow 72 as a value not giving any hindrance even when the VCO changes and a period t1 as a time operated by a NAND gate, the fluctuation of frequency due to leakage and external disturbance is absorbed by the change in the t1 and an output is given at each detection period, then a slight phase change causes a change in the t1 and the effect of the low frequency current onto other circuits is avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a PLL circuit that is suitable for integration and has good sensitivity.

[Background of the invention]

Figure 2 shows PLL (Phase Lockgct).
An example of a configuration diagram of a Loop) circuit is shown. Reference numeral 21 is a phase detector, 22 is a filter, Kago is a voltage controlled oscillator, and S is a reference signal source. The phase detector 21 detects the phase difference between the reference signal and the output signal of the voltage controlled oscillator mill, and generates a voltage according to the phase difference.The output voltage of the phase detector 21 is applied to the filter n.
The signal is smoothed by the voltage controlled oscillator and applied as a control voltage to the voltage controlled oscillator, causing the oscillation frequency to match the frequency of the reference signal and fixing the phase.

FIG. 3 shows an example of a specific circuit of the phase detector 21. 31
is a terminal for inputting the reference signal, 32 is a terminal for inputting the output signal of the voltage controlled oscillator, 33 is a phase detection output terminal, U is a HAND gate, 35 is an AND gate, 36 is an inverter, 37 is a P-type MOS transistor, North is an N-type MOS transistor, 39 is a ground terminal, and 30 is a power supply. Further, FIG. 4 shows an example of the signal waveform of each terminal shown in FIG. 3, and the operation will be explained. (41 is the reference signal applied to terminal 31,
(A) is the output waveform of the voltage controlled oscillator at a certain moment, which is the waveform at the terminal 320. At that time, the output waveform of the AND gate 35 is rC+, and the output waveform of the NAND gate is (dl). By adding the signals (ff) and (d) to the VOS transistors 37 and 38, the fourth It becomes a low level in the period 410 shown in the figure, and becomes a high level in the period 42.Suppose now that the oscillation frequency is decreasing, the phase is delayed, and the waveform moves toward the weak arrow.Then, the period 42 becomes longer. , 410 periods become shorter. Conversely, when the oscillation frequency increases and the waveform moves in the direction of arrow 43, the period 41 becomes longer and the period 42 becomes shorter. As shown in FIG. If a filter is connected, and the on-resistances of MOS transistors 37 and 38 are designed to be equal, the output of the filter will be a higher voltage as the period 41 is longer, and a lower voltage as the period 942 is longer.In general, the voltage Since the oscillation frequency of the controlled oscillator increases as the control voltage increases, the phase detector 21 and filter n work to correct when the oscillation frequency becomes higher or lower than the frequency of the reference signal. As mentioned above, this type of phase detector always outputs an output signal, and current flows through the MOS transistors 37 and 38 at the frequency of the reference signal.However, a PLL with a phase difference of 100 degrees In ``Basics and Applications of PLL'' written by Hideo Tsunoda, it is stated that there is a drawback of locking at frequencies that are odd multiples of the reference signal frequency or its reciprocal multiples, that is, side locking.

FIG. 5 shows an example of a phase detector that does not cause side lock. 51 is a terminal for inputting a reference signal, 52 is a terminal for inputting an output signal of a voltage controlled oscillator, 53 is a phase detection output terminal, U is an inverter, 1 to 9 are NAND gates, 5
5 is an output signal terminal of the NARD gate 8, 56 is an output signal terminal of the inverter, and those having the same symbols as in FIG. 3 have the same functions. In addition, an example of the signal waveform of each terminal shown in FIG. 5 is shown and explained in FIG. g6. (A) is the reference signal waveform applied to the terminal sIK, and (A) is the output waveform of the voltage controlled oscillator at a certain moment, which is the signal waveform at the terminal 52. At this time, the signal waveforms at terminals 55 and 56 are (ffl, (d)K).In other words, in the circuit shown in FIG. While detection was performed by NAND with logic, the circuit of FIG. 5 is designed to perform detection by comparing the falling portion of the reference signal and the oscillator output signal.

The operations of the MOS transistors 37 and 38 and the output terminal 53 are as explained in FIG. This circuit does not cause side lock, but when the oscillator output matches the reference signal, that is, when the PLL circuit is locked, the terminal s
s and ss K no longer output, and both MOS transistors 37 and 38 remain off. When the filter output changes due to leakage, the MOS transistors 37 and 38 are switched and current flows. Therefore, the detection operation will be performed at a low frequency. For example, when trying to put the above PLL circuit in the same semiconductor chip as the analog circuit of the delay line of the video signal, the low frequency current causes the potential of the power supply and board to fluctuate, causing the analog signal system circuit to This may cause interference and appear as noise on the screen when the output video signal is played back. Furthermore, there is a problem in the sensitivity of the PLL because there is a delay in the gate, which makes it impossible to detect a slight change in phase between the reference signal and the oscillator output signal from the matched state.

As mentioned above, the circuit in Figure 3 is a side lock,
The circuit shown in the figure had problems such as low frequency current and detection sensitivity.

[Purpose of the invention]

An object of the present invention is to provide a highly sensitive PLL circuit that does not adversely affect the analog circuit and does not cause side lock when built into the same semiconductor chip as the analog circuit.

[Key points of invention]

An output signal is output from the detector every detection cycle, eliminating the influence of low frequency current on the analog circuit system and increasing transverse wave sensitivity.

[Actual example of invention]

An embodiment of the present invention is shown in FIG. 1 and will be described.

Components with the same symbols as in FIG. 5 have the same functions.

11 is a capacitor) corresponding to the filter 22 in FIG. 12 is an Np s u transistor, 13 is a resistor,
14 is a voltage source. Transistor 12. A current source is constituted by a resistor 13° and a voltage source 14 K, so that a minute current always flows from the capacitor 11. Then, even in the locked state, the terminal 530 level will drop by the amount of current flowing into the current source, and the loop will operate to return it to its original state, allowing current to flow. FIG. 7 shows the waveforms of each part in the locked state.

(α) is the terminal 510 reference signal, (bl is the vehicle power signal of the voltage controlled oscillator input to the terminal 52, (C1, (dl is the signal at the terminals 55 and 56, and (-) is the output waveform at the terminal 53. The difference from the conventional example shown in FIG. 5 is that when locking, the phases of the reference signal and the oscillator output signal match and no current flows through the MOS transistor 37 #38, whereas the period t shown by 71 always The phase is shifted by , and the current flows.The relationship between the current and voltage is as follows: If the value of the capacitor is cs Cp, then v = apricot fidt, so the current flowing into the current source is 11, and the current flowing from the MOS transistor 37 is !3.If the detection period is T, TI,
=t, I holds true. Also, the range ν indicated by the arrow 72
1 is determined by = J 7 = 't, CI
C. If vl is set to a value that does not cause any problem even if the oscillation frequency of the voltage controlled oscillator changes, and period t is set to a time that allows the NAND (HAND) gate etc. to operate, frequency fluctuations due to disturbances during leakage will be caused by changes in tl. Since the output is output every detection cycle, even a slight change in phase appears as a change in tl, and it is also possible to eliminate the influence of low-frequency current on other circuits.

Other embodiments are shown in FIGS. 8 to 13. Each figure is a circuit diagram indicated by the broken line 15 in FIG. 1, and parts with the same reference numerals have the same functions. 81 in FIG. 8 is an N-type MOS transistor. The operation is the same as that in FIG. 1, with the MOS transistor 81 forming a current source to allow current to flow. 9th
The figure shows a pNp type transistor 9, contrary to the examples shown so far.
A current source is formed by a 1° resistor 13 and a voltage source 14, and current is caused to flow into the capacitor 1. That is, the MOS transistor North is switched every detection cycle to cause current to flow in the direction of lowering the voltage that has increased due to the current flowing from the current source.

FIG. 10 uses a P-type MOS transistor 101 as a current source, and the operation is exactly the same as that in FIG. 9.

1] The figure shows bipolar transistors and M
By using a depletion-type MOS transistor for the P-type MOS transistor 37 or the N-type MOS transistor 3B instead of using an OS transistor, current can constantly flow in or out from there, and the same effect as using a current source can be obtained. It's something you get.

In FIG. 12, a high-resistance element 121 is used to cause a minute current to flow from the capacitor 11, and in FIG. 13, it is caused to flow toward the capacitor l.The operation is the same as that in which a current source is provided.

〔Effect of the invention〕

According to the present invention, in a digital phase detector with an infinite capture range, it is possible to eliminate the influence of a current flowing at a low frequency on an analog circuit system, and the detection sensitivity can be increased.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a phase detection circuit and filter according to the present invention, Fig. 2 is a configuration diagram of a PLL, Figs. 3 and 5 are examples of phase detection circuits, and Figs. 4 and 6 are Fig. 3. , FIG. 7 shows operating waveforms of the circuit in FIG. 1, and FIGS. 8 to 13 show other examples of circuits according to the present invention. 1 to 9...HAND gate 1)...Capacitor

Claims (1)

[Claims] It comprises at least a voltage controlled oscillator, a phase detector into which the output of the voltage controlled oscillator and a reference signal are input, and a filter connected to the output of the phase detector, and the output of the filter is used as the control voltage of the voltage controlled oscillator. 1. A PLL circuit having a configuration in which a current source is connected to the filter.