JPS61264768A - Device for driving recording element array - Google Patents

Device for driving recording element array

Info

Publication number
JPS61264768A
JPS61264768A JP60107553A JP10755385A JPS61264768A JP S61264768 A JPS61264768 A JP S61264768A JP 60107553 A JP60107553 A JP 60107553A JP 10755385 A JP10755385 A JP 10755385A JP S61264768 A JPS61264768 A JP S61264768A
Authority
JP
Japan
Prior art keywords
recording
circuit
recording element
line
light
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60107553A
Other languages
Japanese (ja)
Inventor
Kiyoshi Futaki
二木 清
Yasuo Inui
乾 泰夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic System Solutions Japan Co Ltd
Original Assignee
Matsushita Graphic Communication Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Graphic Communication Systems Inc filed Critical Matsushita Graphic Communication Systems Inc
Priority to JP60107553A priority Critical patent/JPS61264768A/en
Publication of JPS61264768A publication Critical patent/JPS61264768A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dot-Matrix Printers And Others (AREA)
  • Exposure Or Original Feeding In Electrophotography (AREA)
  • Led Devices (AREA)

Abstract

PURPOSE:To correct any difference in recorded data in a recording element array without substantially increasing the scale of circuits, by providing a line memory for storing picture signals, a memory circuit in which a number of times of recording in one-line scanning is set as a correction data based on the amount of data recorded in each element and a control circuit supplying the picture signals to a driving circuit for driving the recording element array according to the correction data. CONSTITUTION:Picture signals inputted from a picture signal input terminal 4 are stored in a line memory 5. The stored signals are read out for (n) times during one line scanning and inputted into a control circuit 7. The control circuit 7 selectively supplies the picture signals to a driving circuit 3, based on correction data from a memory circuit 6. That is, the picture signals are recorded for (n) times while one line is scanned, and the period of time for which electric current is applied to each element is changed by changing the number of times of recording. Further, more times of recording are performed for the elements emitting smaller amount of light, while fewer times of recording are performed for the elements emitting larger amount of light, so that any difference in amount of light among the various elements is properly corrected.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、電子写真プロセスの光書込みヘッドに使われ
る発光素子アレイ駆動装置などの記録素子アレイ駆動装
置に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a recording element array driving apparatus such as a light emitting element array driving apparatus used in an optical writing head of an electrophotographic process.

従来の技術 従来この種の装置としての発光素子アレイ駆動装置は、
第6図に示すような構成になっていた。
BACKGROUND ART Conventionally, a light emitting element array driving device as this type of device is
The configuration was as shown in Figure 6.

画信号入力端子1o4から加えられる画信号を基に電源
入力端子101からの電流を駆動回路102で制御して
発光素子(LED)アレイ1o3に印加する。
Based on the image signal applied from the image signal input terminal 1o4, the current from the power input terminal 101 is controlled by the drive circuit 102 and applied to the light emitting element (LED) array 1o3.

発明が解決しようとする問題点 しかし、従来の構成によれば、各LED素子及び駆動回
路の特性ばらつきによるI4Dアレイの発光ばらつきが
生じるという現象があり、これを補正しようとすると回
路規模が大幅に増大するという問題があった。
Problems to be Solved by the Invention However, with the conventional configuration, there is a phenomenon in which variations in the light emission of the I4D array occur due to variations in the characteristics of each LED element and drive circuit. The problem was that it was growing.

かかる問題は、各LED素子及び駆動回路の特性ばらつ
きを補正する為には、一般的に各素子毎に補正回路を持
ち、各素子毎に電流印加時間又は印加電流値を制御しな
ければならないという理由によって生じていた。又、こ
のことはllCDのみでなく感熱素子等の記録素子にも
同等に言えることである。
This problem arises from the fact that in order to correct variations in the characteristics of each LED element and drive circuit, it is generally necessary to have a correction circuit for each element and control the current application time or applied current value for each element. It happened for a reason. Further, this is equally true not only for IICDs but also for recording elements such as heat-sensitive elements.

本発明は、上述の問題点に鑑みて為されたもので、大幅
に回路規模が増大することなく、記録素子アレイの記録
ばらつきを補正することのできる記録素子アレイ駆動装
置を提供する事を目的とする。
The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a recording element array driving device that can correct recording variations in a recording element array without significantly increasing the circuit scale. shall be.

問題点を解決するための手段 本発明は上述の目的を達成するため、画信号を蓄えるラ
インメモリと、記録素子毎の記録量に基づいて補正情報
とじて一ライン走査における記録回数を設定した記憶回
路と、この補正情報によって画信号を記録素子アレイの
駆動回路に供給する制御回路とを備えている。
Means for Solving the Problems In order to achieve the above-mentioned object, the present invention includes a line memory for storing image signals, and a memory for setting the number of recordings in one line scan as correction information based on the recording amount for each recording element. and a control circuit that supplies an image signal to a drive circuit for the recording element array based on the correction information.

作用 ラインメモリから出力される画信号は、記憶回路に記憶
された記録素子毎の補正情報に基づき、制御回路で一ラ
イン走査中に所定回数読出され、駆動回路に供給される
The image signal output from the active line memory is read out a predetermined number of times by the control circuit during one line scan based on correction information for each recording element stored in the storage circuit, and is supplied to the drive circuit.

実施例 第1図は、本発明の一実施例であり、記録素子としてL
EDを用いたLEDアレイ駆動装置を示す概略ブロック
図である。
Embodiment FIG. 1 shows an embodiment of the present invention, in which L is used as a recording element.
1 is a schematic block diagram showing an LED array driving device using an ED.

このLEDアレイ駆動装置は、LEDを複数個並べたL
EDアレイ1と、電源入力端子2を有し、LEDアレイ
を駆動する駆動回路3と、端子4から入力される画信号
を−ライン分蓄えると共に、クロック端子CLKからの
クロック信号に同期して作動するラインメモリ5とを備
えている。さらに、この装置は、上記画信号に対する補
正情報が格納され、上記ラインメモリ6と同様、クロッ
ク端子OLEからのクロック信号に同期して作動する記
憶回路6と、ラインメモリ5から入力される画信号を記
憶回路6の補正情報に基づき制御して駆動回路3へ供給
する制御回路7とを備えている。
This LED array drive device is an L
It has an ED array 1, a power input terminal 2, a drive circuit 3 for driving the LED array, and a drive circuit 3 that stores -line image signals input from the terminal 4, and operates in synchronization with a clock signal from a clock terminal CLK. The line memory 5 is also provided with a line memory 5. Further, this device includes a storage circuit 6 in which correction information for the image signal is stored and operates in synchronization with a clock signal from a clock terminal OLE, similar to the line memory 6, and an image signal inputted from the line memory 5. The control circuit 7 controls the correction information based on the correction information in the storage circuit 6 and supplies the control information to the drive circuit 3.

ラインメモリ5は、−ライン走査中にクロック信号に同
期して複数回(例えばn回)画信号の読出しが行なわれ
、これによって一ライン走査時間がn分割さnる。また
、制御回路7は、例えば第2図に示すように、ラインメ
モリ5からの画信号入力と記憶回路6からの補正情報入
力との間で論理積をとって出力するアンドゲート71L
から成り、その出力は補正画信号(あるいは変換画信号
)として駆動回路に供給される。
In the line memory 5, image signals are read out a plurality of times (for example, n times) in synchronization with a clock signal during -line scanning, thereby dividing one line scanning time into n divisions. Further, as shown in FIG. 2, for example, the control circuit 7 includes an AND gate 71L that performs a logical AND operation between the image signal input from the line memory 5 and the correction information input from the storage circuit 6.
The output is supplied to the drive circuit as a corrected image signal (or converted image signal).

記憶回路6は、各LEDが同一ライン入力画信号に対し
て同一出力を得られるように、上記読出し回数nに対応
して、LICD素子毎に、それぞれの発光量に応じた記
録回数を補正情報として記憶している。この記憶回路6
には例えば第3図に示すような形態がとられる。この記
憶回路6は、横方向に1,2.・・・・・・a、b、・
・・・・・pと各LED素子に対応するビットに配列さ
れ、縦方向に1,2゜・・・・・・3・・・xl、・・
・x2t・・・nとこの記憶回路6に対する読出し回(
LEDアレイにおける記録量に相当する)がアドレス情
報として格納される構成になっている。そして、例えば
、第1番目のLID素子のように、発光量が少ない素子
に対しては、全読出し回について発光させるようにオン
情報“1”が書込まれる一方、第2番目のLED素子の
ように、発光量が多い素子に対しては早い読出し回で発
光を止める様オフ情報“0”が書込まれ、全体としての
補正情報が形成される。かかる補正情報によって入力画
信号に対して補正が加えられ、同一ラインの画信号入力
に対して各LzD素子の発光量が均一化せしめられるよ
うになっている。
The storage circuit 6 stores, for each LICD element, correction information on the number of times of recording according to the amount of light emitted, corresponding to the number of readings n, so that each LED can obtain the same output for the same line input image signal. I remember it as. This memory circuit 6
For example, the configuration shown in FIG. 3 is taken. This memory circuit 6 is arranged horizontally as 1, 2, .・・・・・・a, b,・
・・・・・・Arranged in bits corresponding to p and each LED element, 1, 2 degrees in the vertical direction...3...xl,...
・x2t...n and the readout times for this memory circuit 6 (
(corresponding to the recording amount in the LED array) is stored as address information. For example, for an element that emits a small amount of light, such as the first LID element, on information "1" is written so that it emits light for all reading times, while for the second LED element, Thus, off information "0" is written to elements that emit a large amount of light so as to stop emitting light at an early readout time, thereby forming correction information as a whole. The correction information is used to correct the input image signal, so that the amount of light emitted from each LzD element is made uniform for input image signals on the same line.

次に動作を説明する。Next, the operation will be explained.

画信号入力端子4から入力される画信号は、ラインメモ
リ6に蓄えられる。その後−ライン走査中に1回読出さ
れ、制御回路7に入力される。制御回路7では、記憶回
路6からの補正情報を基に、選択的に画信号を駆動回路
3に供給する。すなわち、この実施例では、−ライン走
査中にn回記録を行い、記録回数を変化させることによ
り、各素子の電流印加時間を変化させる。さらに、発光
量の少い素子には多い回数、発光量の多い素子には少い
回数記録を行う事によシ各素子の光量ばらつき補正を行
なう。
The image signal input from the image signal input terminal 4 is stored in the line memory 6. Thereafter, it is read out once during line scanning and input to the control circuit 7. The control circuit 7 selectively supplies the image signal to the drive circuit 3 based on the correction information from the storage circuit 6 . That is, in this embodiment, recording is performed n times during -line scanning, and by changing the number of recordings, the current application time of each element is changed. Furthermore, by performing recording more times for elements that emit less light and fewer times for elements that emit more light, variations in light amount of each element are corrected.

かかる発光量のばらつき補正操作を第3図及び第4図を
参照して説明する。既に述べたように、−ライン走査中
における読出し回数及び記録回数は共にnであり、記憶
回路7には各発光素子1゜2.3.・・・a、・・・b
、・・・pの発光量のばらつきを考慮した補正情報が格
納されている。ここで、ラインメモリ5に第4図(a)
に示すような画信号pixが入力されたとする。すると
、制御回路7は一ライン走査中にこの画信号をn回、ラ
インメモリ5から読出す一方、記憶回路7からは各読出
し回に対応する補正情報を読出し、双方のデータ間の論
理積を算出して演算結果を記録用の画信号p1x(補正
さnた画信号である)として駆動回路3へ出力する。こ
うして出力された補正画信号を各記録回数毎についてみ
ると第4図中)に示す通りとなる。即ち、第1番目の発
光素子については、記憶回路7に、全読出し回について
オンするためのデータ″1°゛が格納されているから、
補正画信号も全記録口について駆動できるようになって
いる。
The operation for correcting variations in the amount of light emitted will be explained with reference to FIGS. 3 and 4. As already mentioned, the number of readings and the number of recordings during -line scanning are both n, and the memory circuit 7 has each light emitting element 1°2.3. ...a, ...b
, . . . correction information that takes into account variations in the amount of light emitted by p is stored. Here, in the line memory 5, as shown in FIG.
Assume that an image signal pix as shown in is input. Then, the control circuit 7 reads this image signal from the line memory 5 n times during one line scan, while reading the correction information corresponding to each readout from the storage circuit 7, and calculates the logical product between both data. The calculation result is output to the drive circuit 3 as a recording image signal p1x (corrected image signal). Looking at the corrected image signals output in this way for each number of recording times, the results are as shown in Fig. 4). That is, for the first light emitting element, data "1°" for turning it on for all reading times is stored in the memory circuit 7.
The corrected image signal can also be driven for all recording ports.

これに対して1番目ビットに対応する発光素子にはx1
回目までは駆動信号が発せられるが、X++1回目から
は駆動信号が発せられない。また5番目ビットに対応す
る発光素子にはx2回目までは駆動信号が発せられるが
x2千1回目からは駆動信号が発せられない。なお、第
2番目及びp番目のピットについては最初から0”デー
タであるためこれに対応する発光素子は駆動されない。
On the other hand, the light emitting element corresponding to the 1st bit has x1
A drive signal is emitted up to the X++th time, but no drive signal is emitted from the X++1st time onwards. Further, a drive signal is emitted to the light emitting element corresponding to the fifth bit up to x2 times, but no drive signal is emitted from x2,011 times. Note that since the second and p-th pits have 0'' data from the beginning, the corresponding light emitting elements are not driven.

このようにして、最初に入力された画信号pixは1回
読出される間にそれぞれのビットについて補正情報に基
づいてビット変換さn、補正画信号pixとして駆動回
路3に供給される。
In this way, while the first input image signal pix is read out once, each bit is converted into bits based on the correction information n, and is supplied to the drive circuit 3 as a corrected image signal pix.

かかる操作を総合的に勘案すれば、結局、第6図に示す
ように、−ライン走査時間to 中n回記録を行い、発
光量の多い素子aの記録回数x1  より、発光量の少
い素子すの記録回数x2を多くし、−ライン走査中の総
合的な発光量を一致させていることになる。
If such operations are taken into consideration comprehensively, as shown in FIG. 6, recording is performed n times during -line scanning time to, and the element with a smaller amount of emitted light is This means that by increasing the number of times x2 is recorded, the total amount of light emitted during -line scanning is made the same.

上述は、光量ばらつき補正について述べたが、各素子毎
に発光量を制御する操作全般に使用可能である。
Although the above description is about light amount variation correction, the present invention can be used for all operations that control the amount of light emitted by each element.

発明の効果 以上の説明から明らかなように、本発明によれば、あら
かじめ記録素子毎に設定した補正情報により選択的に供
給される画信号を一ライン走査中複数回記録を行う事に
より、各記録素子毎に電流印加時間制御回路を持つ事な
く、各記録素子毎に電流印加時間を制御することができ
る為、各記録素子毎の記録量を制御して、記録ばらつき
補正を行うことができる。
Effects of the Invention As is clear from the above explanation, according to the present invention, image signals selectively supplied based on correction information set for each recording element in advance are recorded multiple times during one line scan, so that each Since the current application time can be controlled for each recording element without having a current application time control circuit for each recording element, it is possible to control the recording amount for each recording element and correct recording variations. .

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例のm*、)アレイ駆動装置を
示す概略ブロック図、第2図は第1図に示す制御回路の
一例を示すブロック図、第3図は第1図に示す記憶回路
の補正情報格納形態の一例を示す図、第4図(a)は第
1図に示すラインメモリへの入力画信号の一例を示し、
(b)はこの入力画信号に対する、制御回路から出力さ
れる補正画信号の一例を示す図、第6図は第1図に示す
装置の発光時間タイミングチャート、第6図は従来のL
EDアレイ駆動装置の一例を示す概略ブロック図である
。 1・・・・・・LEDアレイ、3・・・・・・駆動回路
、6・・・・・・ラインメモリ、6・・・・・・記憶回
路、7・・・・・・制量回路。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名IR
敏 区 塀羽−回 eつ 派 さ            ご ロー                       
   偽、区−7−7 嘴t
FIG. 1 is a schematic block diagram showing an m*) array driving device according to an embodiment of the present invention, FIG. 2 is a block diagram showing an example of the control circuit shown in FIG. 1, and FIG. 3 is a block diagram showing an example of the control circuit shown in FIG. FIG. 4(a) shows an example of an input image signal to the line memory shown in FIG.
(b) is a diagram showing an example of a corrected image signal output from the control circuit in response to this input image signal, FIG. 6 is a light emission time timing chart of the device shown in FIG. 1, and FIG.
FIG. 1 is a schematic block diagram showing an example of an ED array driving device. 1...LED array, 3...drive circuit, 6...line memory, 6...memory circuit, 7...control circuit . Name of agent: Patent attorney Toshio Nakao and one other IR
Toshi-ku Keiwa - Etsuha Goro
False, Ward-7-7 Beak t

Claims (1)

【特許請求の範囲】[Claims] 記録素子アレイを複数個並べた記録素子アレイと、前記
記録素子アレイを駆動する駆動回路と、画信号を蓄える
ラインメモリと、前記記録素子毎に設定された読出回数
情報を記憶した記憶回路と、前記ラインメモリから入力
される画信号を前記記憶回路から入力される読出回数情
報に基づき、対応する記録素子毎に前記読出回数だけ読
出し、読出した信号を選択的に前記駆動回路に供給する
制御回路とを備えた記録素子アレイ駆動装置。
a recording element array in which a plurality of recording element arrays are arranged; a drive circuit for driving the recording element array; a line memory for storing image signals; and a storage circuit for storing read count information set for each recording element; a control circuit that reads the image signal inputted from the line memory for the number of times of reading for each corresponding recording element based on the number of readings information inputted from the storage circuit, and selectively supplies the readout signal to the drive circuit; A recording element array drive device comprising:
JP60107553A 1985-05-20 1985-05-20 Device for driving recording element array Pending JPS61264768A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60107553A JPS61264768A (en) 1985-05-20 1985-05-20 Device for driving recording element array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60107553A JPS61264768A (en) 1985-05-20 1985-05-20 Device for driving recording element array

Publications (1)

Publication Number Publication Date
JPS61264768A true JPS61264768A (en) 1986-11-22

Family

ID=14462100

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60107553A Pending JPS61264768A (en) 1985-05-20 1985-05-20 Device for driving recording element array

Country Status (1)

Country Link
JP (1) JPS61264768A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59194566A (en) * 1983-04-20 1984-11-05 Matsushita Graphic Commun Syst Inc Picture recorder

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59194566A (en) * 1983-04-20 1984-11-05 Matsushita Graphic Commun Syst Inc Picture recorder

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