JPS61263283A - Manufacture of field effect transistor - Google Patents

Abstract

PURPOSE:To obtain an element which has high mutual conductance and small feedback capacity by forming polycrystalline silicon layers of different thickness in holes for forming two gate regions, and ion implanting through the holes to form gate regions of different depths. CONSTITUTION:An N-type epitaxial layer 2 is formed on a P-type silicon substrate 1, and a P<+> type separating region 3 which arrives at the substrate 1 is formed through the layer 2 to form the layer 2 as an insular region. Then, with an SiO2 film 4 as a mask phosphorus ions are diffused to form source and drain regions 5, 6. Then, the film 2 is selectively removed to form two windows 7, 8 for forming a gate region. Then, a polycrystalline silicon layer 9 is formed in the window 8, boron difluoride ions are implanted, subsequently heat treated to form gate regions of different depth in the windows 7, 8.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention provides a junction electric field having a structure that has high mutual conductance qm in the high frequency range and low drain current range, excellent saturation characteristics of drain current ID, and small feedback capacitance Cx5s. This relates to an effect transistor (hereinafter abbreviated as J-FET).

BACKGROUND TECHNOLOGY I-
Fll:T is superior mainly in that it can reduce feedback capacitance. First, this will be explained. This T-FET has a source region 20. First gate region 21. Second gate region 22. The diffusion depth of the first gate region 21 is a second drain region.
It is deeper than the diffusion depth of the gate region 22. In order to realize such a structure, conventionally gate diffusion is performed twice to form the first. The depth of the second gate regions 21 and 22 is controlled. By adopting a structure in which the source region 20 is connected to the p-type silicon substrate 26 through, for example, the metal wiring 24 and the p+ type isolation region 26, the gate input capacitance and feedback capacitance Cr5s are reduced, and the high frequency characteristics are improved. Note that 24, 27, 28 and 29 in the figure are source regions 20. First gate region 21. Electrodes of the second gate region 22 and drain region 23; 30 is a eutectic layer of metal and silicon formed on the die-bonding surface between the silicon chip and the metal header; 31 is an n-shade region; 32 is an insulating layer made of a silicon dioxide film, etc. It is.

FIG. 3 is a diagram showing an equivalent circuit shown to explain the operating characteristics of the cascode type J-FET, where the cascode type ff -FET is the J-FET+1 and )-FE
T42 can be represented as cascade-connected. The substrates of both 1-FETs are commonly connected to the source 36. This substrate is p-type silicon substrate 2 in FIG.
6, and 34.33 correspond to the first gate regions 21.6, respectively. This corresponds to the second gate region 22 , and the drain 35 corresponds to the drain region 23 .

By the way, the cascode type 1-FET has the advantage that the feedback capacitance, which becomes a problem at high frequencies, is smaller than the single gate type having one gate, but has the disadvantage that the mutual conductance qm is small. This will be explained in more detail with reference to FIG. 3 below. Gate 3 of J-FET37
Since a reverse voltage is applied to the gate 34 of the 3 and 1-FET 38, the voltage of 1o-11 to 10-1 is applied to the gates 33 and 34.
Only a current of about 2 A flows, and this current can be ignored compared to the drain current. Therefore, T-FETs 37 and 38
Since the drain currents ID flowing through both are continuous, they can be considered to be the same. Here, if the maximum saturation drain current that can flow through J-FET38 is 1Ds81, then this ID5
s is its structural dimensions and the voltage applied to the gate 34 vG1
This value is determined by the voltage vD1s1 between the drain and source 36 of the T-FET 38. On the other hand, J-FET37
If the maximum saturation current that can flow through SS2 is SS2, this also depends on its structural dimensions and the voltages vG2 and vD applied to the gate 33.
The difference voltage between lsl (vG2-vDlsl) and devy3
s+! = 7-voltage between the terminals 36 vD2s1 and vDls
This value is determined from the voltage difference between D2s1 and Dlsl (■D2s1 Dlsl).

Therefore, SS is not greater than ssl and ID5S2 than the maximum saturation current of the cascode type 1-FET, and is determined by the smaller value of either Ds81 or ID582.

Note that, in practical terms, it is more desirable that SS1< than SS2. This will be further explained with reference to FIGS. 4 and 6. FIG. 4 shows the second gate region 22 as the source region 2o.
and the vicinity of the gate region of the l-FET connected to the substrate 26, in which the first and second gate regions 21.
A depletion layer region (shaded area) formed at the interface between 22, its periphery, and the substrate 26, and a channel region between this depletion layer region are shown. Even if vG2 is OV, a reverse bias is applied to the second gate region 22 by the amount of vDlsl. The area 22 is different. The depletion layer region under the second gate region 22 becomes wider than the depletion layer region under the first gate region 21 by an amount corresponding to the deeper reverse bias. Therefore, if the thickness tl from the bottom of the first gate region 21 to the substrate 26 and the thickness t2 from the bottom of the second gate region 22 to the substrate 26 are set to be equal, then the second Gate area 2
The channel below 2 becomes narrower and DSS2 becomes smaller than ID5s1. For example, if ssl is 1 or ILA
Even so, if ■Ds82 is 5 mA, the drain current ID of the cascode T-FET is limited by the unsaturated drain current of the l-FET37, as shown in Fig. 6 (A).
As shown in the figure, when the drain current ID is 2 and around smA, gm becomes large, and the mutual conductance qm becomes relatively small in a region where the drain current is larger. In order to make this mutual conductance gm as large as possible, 1
- “DS” so that the saturation current of FET38 flows as it is.
Since it is necessary to make S2 larger than ssl, care is taken to establish the relationship 11) and 12 between tl and t2, which are related to the width of the channel region, as shown in the figure.

In other words, the drain current ID of the cascode type 1-FET
The uniformity within the wafer is highly dependent on the thicknesses tl and t2. By the way, controlling the thicknesses t and t2 becomes difficult if the first gate region 21 and the second gate region 22 are formed as shallow diffusion regions, and conversely, if these regions are too deep, qm becomes low. has been confirmed.

That is, the deeper the gate region is made, the larger the lateral spread becomes, and the effective channel lengths Ll and L2 become larger. Therefore, for example, a cascode type 1-FΣ having static characteristics as shown in FIG. 6(B) is obtained, and ID≦0.
When trying to obtain 5mA, gm≧2.3m,
The thicknesses tl and t2 are individually controlled from 0.1 to 0.2.
This must be done with an accuracy within the μ door range. For such control, conventionally, the first and second gate regions 21 and 22 were diffused separately, for example, the first gate diffusion was followed by the second gate diffusion.

Problems to be Solved by the Invention In the conventional method, the impurities in the first gate region 21 formed earlier are diffused again during the second gate diffusion, and the thickness tl and The effective channel length Ll changes, making it difficult to secure the control index in the range of 0.1 to 0.2 μm. This results in tl and ri.

control becomes extremely inaccurate. Therefore, it is difficult to realize a 1-FET having desired values of qm and feedback capacitance, and the manufacturing yield and reproducibility are extremely poor.

Means for Solving the Problem The manufacturing method of the present invention to solve this problem uses active dose control by ion implantation through the polycrystalline silicon film, thereby reducing the gate diffusion process in one time. In the above 1. This is a method in which the second gate regions 21 and 22 are simultaneously formed and their depths are independently controlled.

Function: According to the manufacturing method of the present invention, impurity ions are simultaneously implanted into the two regions to become the first and second gates of the cascode-type ■-NET, and the implanted ions are further activated by the same heat treatment. Therefore, it is possible to independently and accurately control the distances tl and t2 from the bottom of the gate region to the substrate, and to create a cascode type 1-FE with desired characteristics.
It becomes easy to manufacture T.

Embodiment FIGS. 1A to 1F are diagrams showing the process of manufacturing a cascode T-FET by the manufacturing method of the present invention.

First, as shown in FIG. 1(A), for example, when the resistivity is 1Ω,
・On the p-type silicon substrate 1 of α, the resistivity is 0.5Ω・α
, by forming an n-type epitaxial layer 2 with a thickness of approximately 2.3 μm, and further forming a p + type isolation region 3 penetrating this layer to reach the p-type silicon substrate 1.
The epitaxial layer 2 is formed into an island-like region. Note that 4 is a StO□ film covering the surface.

Next, by selective diffusion using the SiO□ film 4 as a mask, phosphorus is diffused to a high concentration to form an n-type source region 6 and an n+-type drain region 6 [see FIG.
)].

5lo2 film 2 is applied to the silicon substrate that has undergone the above processing.
A photo-etching process is performed to selectively remove the gate area, thereby forming a window 8 for forming the first gate area and a window 8 for forming the second gate area (FIG. 1(C)).

Thereafter, a polycrystalline silicon layer with a thickness of about 1000 nm is formed over the entire surface, and the formed polycrystalline silicon layer is selectively removed to completely fill the inside of the window 8 for forming the second gate region. 310 around window 8.
A polycrystalline silicon layer 9 is formed extending over the two film portions [FIG. 1(D)].

Next, boron difluoride (BF2) was accelerated at a voltage of 40 KeV.
, Ion implantation is performed at a dose of 1×1o15σ−2, followed by heat treatment for activation and annealing of the implanted ions. By this treatment, a deep p+ type region 1 is formed in the portion corresponding to the window 7 in the n type epitaxial layer.
0, and on the other hand, there is a shallow p+ type region 1 in the part corresponding to the window 8.
1 is formed [Fig. 1(E)].

These p shadow regions 1o and 11 are regions that function as the first gate region and second gate region of the 1-FET, and gate regions with different depths are formed in one process.

Finally, contact windows are opened in the source region 6 and drain region e, and metal electrodes 12 are connected to each region.
16, a J-FET according to the manufacturing method of the present invention is completed [FIG. 1(F)].

By the way, in the above explanation, the case where the polycrystalline silicon layer is formed on one of the gate formation window portions is illustrated, but the polycrystalline silicon layer is formed on both gate formation window portions, and these By varying the thickness of the polycrystalline silicon skin, we can also target cascode-type 1-FET.
It is possible to produce.

As described in detail, according to the manufacturing method of the present invention, first and second gate regions having different depths can be formed in one process, and two gate regions can be formed in two diffusion processes. There are no disadvantages that existed in the conventional method of forming one gate region, that is, there is no change in the thickness tl of the epitaxial layer portion existing between the lower part of the first gate region and the silicon substrate, and there is no change in the effective channel length L1. Therefore, tl and Ll can be determined with high precision, mutual conductance gm is high, drain current saturation characteristics are good, and the feedback capacitance Cr5s is small.
T is realized.

[Brief explanation of drawings]

FIGS. 1(A) to (F) are cross-sectional views showing the process of manufacturing a cascode J-FET using the manufacturing method of the present invention, and FIG. 2 is a cross-sectional view showing the structure of the cascode FF-FET. Figure 3 is an equivalent circuit diagram of a cascode type l-FET,
Figure 4 is a structural diagram of the main parts for explaining the operation of the cascode knee FET, and Figures 6 (A) and (B) are the cascode type 1
-Fl! : It is a figure explaining the static characteristic of T. 1.26...p-type semiconductor substrate, 2,31...
...N-type epitaxial island region, 3, 25...
...p+ type isolation region, 4, 32--...insulating layer (5i
o2 film), ey, 20...source region, 6.2
3...Drain region, a. 8...window, 9...polycrystalline silicon layer,
10.21...First gate region, 11.23.
...Second gate region, 12-18, 24. ．． 27
．． 28.29... Electrode. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 4
Figure 21 = -541 Det tilting bee 22--%tq Figure 5 □Vom(V) 1□Vomtv)

Claims (1)

[Claims] A step of separating a semiconductor layer of an opposite conductivity type formed on a semiconductor substrate of one conductivity type into islands to form island regions, and coating the entire surface of the semiconductor substrate through the same step with an insulating layer, a step of introducing impurities of the same conductivity type into the island region to form a source region and a drain region, and forming first and second openings for forming a gate region in an insulating layer located between the source region and the drain region. a step of forming a polycrystalline silicon layer in one of the first and second openings, or a step of forming a polycrystalline silicon layer having a different thickness in both of the first and second openings; A method for manufacturing a field effect transistor, comprising the step of ion-implanting impurities of one conductivity type to form first and second gate regions having different depths.