JPS6126326A - Transmission system in semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce an area of a signal line wiring area on a pellet by transmitting and receiving a signal between logical blocks by means of a multi-value signal so as to reduce remarkably the signal lines. CONSTITUTION:An output signal of a logical block 1 is converted to a quadri signal by a binary/tetral converting circuit 2 as a transmission line from the logical block 1 to a logical block 4, the signal is converted into a binary signal by a tetral/binary converting circuit 3 again and becomes an input signal of the logical block 4. The signal transmission from the logical block 4 to the logical block 1 is conducted similarly by way of a binary/tetral value converting circuit 5 and a tetral/binary value converting circuit 6.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to the configuration of large-scale logic integrated circuits. [Prior Art] In an integrated circuit chip, the area occupied by active elements such as transistors and diodes is It is relatively small, and the area occupied by the power supply wiring for driving these elements, the common ground line, and the coupling wiring between elements is large. In order to reduce the area of these interconnects, multiple interconnect technology has been developed, but only two or three layer interconnects have been put into practical use.

As the degree of integration increases, the proportion occupied by interconnects decreases, but the absolute amount still increases, which is a bottleneck in realizing large-scale logic integrated circuits.

[Problem that the invention seeks to solve]

Currently, semiconductor logic integrated circuits are realized using binary logic circuits. Furthermore, large-scale logic integrated circuits often use a building block system, in which case they are realized by integrating logic blocks. Furthermore, the number of wiring lines required to spread signals between logic blocks is also considerable. Reducing the wiring area within a logic block is difficult because emphasis must be placed on the logic function, and each logic block has its own problems. However, since the transmission wiring for transmitting and receiving signals between logic blocks does not differ depending on the function of the logic blocks, it is possible to reduce the area of the transmission wiring.

An object of the present invention is to reduce the number of signal transmission wires between logic blocks in a large-scale logic integrated circuit, thereby reducing the area ratio of the wiring area within the integrated circuit.

[Means for solving problems]

In the present invention, the transmission of logic signals between binary logic blocks is
A multi-value logic signal is used, and a binary e-multi-value conversion circuit is provided between each of the binary logic blocks and the transmission line. A binary/multi-value conversion circuit includes a case where a binary code is converted into a multi-value signal, and a case where the signal is converted into a multi-value signal. Therefore, the output signal from the binary logic block is converted from binary to multi-value, and signal transmission between logic blocks is performed using multi-value signals.
Multivalue-to-binary conversion is performed again and input to the logic block as a binary code.

〔Example〕

Embodiments of the present invention will be explained with reference to the drawings.

FIG. 1 is an example in which the present invention is applied to transmission between two logical blocks.

As a transmission path from logical block l to logical block 4,
The binary/quaternary conversion circuit 2 converts the output signal of the logic block 1 into a quaternary code, and the quaternary/binary conversion circuit 3 converts it into a binary code, which is then converted into the input signal of the logic block 4. Become.

Signal transmission from logic block 4 to logic prick 1 is similarly carried out via binary/quaternary conversion circuit 5 and quaternary/binary conversion circuit 6.

In the binary/four-value conversion method, the number of wires required for signal transmission is reduced to 1/2. In order to maximize the effect of reducing wiring, each conversion circuit is placed as close to each logic block as possible.

〔Effect of the invention〕

As described above in detail, the present invention is for transmitting and receiving signals between logic blocks in the integrated circuit in a large-scale semiconductor integrated circuit using a multilevel signal instead of a binary signal. It is possible to significantly reduce the area of the signal line arrangement region on the semiconductor bullet. Although it is conceivable to configure the entire integrated circuit with multi-value logic circuits starting from t4 on the logic block, it is extremely difficult to design multi-value logic functions for all blocks, and it is difficult to implement. Since the present invention uses multivalued logic signals only for signal transmission, it has great practical value.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention. 1.4...Logic block, 2,5...binary/quaternary patent applicant NEC Corporation 2'・-11 agent Patent attorney Lip Uchihara, Figure 1

Claims (1)

[Claims] In a semiconductor integrated circuit, transmission of logic signals between binary logic blocks is performed using multi-value logic signals, and a binary/multi-value conversion circuit is provided between each of the binary logic blocks and the transmission path. A transmission method within a semiconductor integrated circuit characterized by: