JPS6126324A - Switched capacitor circuit - Google Patents

Abstract

PURPOSE:To decrease number of clock signals of a slide capacitor circuit by using a PMOS switch and an NMOS switch in mixture. CONSTITUTION:When a clock signal phi is at a high level, NMOS TR switches 50-1 and 60-1 are turned on and PMOS TR switches 50-2, 60-2 are turned off. Thus, a capacitor 2 is charged through the NMOS switches 50-1, 60-1 with an input signal 1. When the signal phi goes to a low level, the NMOS switches 50-1, 60-1 are turned off, and the PMOS switches 50-2, 60-2 are turned on. Thus, charge of the capacitor 2 is transferred to a feedback capacitor 3 and an output signal 7 integrating an input signal 1 is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a switched capacitor circuit, and particularly to a switched capacitor circuit suitable for high integration.

[Background of the invention]

A switched capacitor circuit is a circuit that performs signal calculation by charging and discharging charge in a capacitor via a switch that opens and closes at a constant cycle, and is a conventional switched capacitor (SC) circuit as shown in Figure 1. In this case, switches with the same polarity were used to control charge transfer. An example of an SC integration circuit, which is a basic component of an SC circuit, will be explained. As shown in the time chart of FIG. 2, the lock signal φ1 turns on the NMOS transistors 5-1, 6-1 of the switches 5 and 6, charges the capacitor 2 with the input signal 1, and the clock φ2 other NM
Other NMOS switches consisting of OS transistors
By turning on transistors 5-2 and 6-2, the charge in the capacitor 2 is transferred to the feedback capacitor 3 between the negative input terminal and the output terminal of the high gain amplifier 4, and the output terminal 7, that is, the amplifier 4 A signal obtained by integrating input signal 1 was obtained at the output terminal of . In this case, if the period in which φ and φ2 are simultaneously at a high level (all NMOS transistor switches are on) is long, the capacitor 2 will be short-circuited and will no longer operate as an integrating circuit. Therefore, the clock signal φ,.

As shown in Figure 2, φ2 had to be a clock signal such that the high level times do not overlap with each other, or at least φ1 and φ2 had to be clock signals in which the high level and low level times were reversed. . Therefore, the first
Even a simple SC circuit as shown in the figure requires two clock wires, and the chip area becomes large when the SC circuit is integrated.

Further, although FIG. 1 uses an NMOS transistor switch, a similar configuration can be made using a PMOS transistor switch. Furthermore, when using a CMOS transistor switch, in addition to φ1° and φ2, φ1. φ, (φ
1. (signal that inverts the high level and low level of φ2)
signal is required.

As described above, conventional SC circuits require a large number of clock signals, which makes it difficult to reduce the chip area and achieve high integration when integrated into an LSI. Regarding SC circuits, IEE
E Proceeding vol 71 Nn 8p
, 941-966 (August 1983)
R in “5” by Gregorian et al.
w1tched Capacitor Circuit
It is introduced in detail in the document entitled ``Design''.

[Purpose of the invention]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an SC circuit which has a simple means for supplying a clock signal and can easily be highly integrated or reduce the chip area.

[Summary of the invention]

In order to achieve the above object, the present invention uses a PMOS switch and an NMOS switch in combination, so that the same clock signal allows one switch to be on and the other switch to be off, except at the transition point of the clock signal. , and vice versa, thereby reducing the number of clock signals in the SC circuit.

[Embodiments of the invention]

The present invention will be explained below using examples. FIG. 3 is a circuit diagram of an embodiment of the SC circuit according to the present invention, which has the same circuit function as FIG. 1. The configuration of this circuit includes an input capacitor 2 that stores an input signal 1, a feedback capacitor 3 and a high gain amplifier 4 connected to the negative input terminal and output terminal of a high gain amplifier 4 whose positive input terminal is connected to the ground. An NMOS transistor switch 50-9 whose drain is connected to the input signal 1, whose source is connected to one terminal of the input capacitor 2, and whose gate is connected to the clock signal φ, and an NMOS transistor switch 50-9 whose drain is connected to the ground (NHO2)- a PMOS transistor switch 50-2 whose source is connected to the source of input capacitor 1 and whose gate is connected to the clock signal φ; a high-gain amplifier 4 whose source is connected to the other terminal of input capacitor 2 and to which feedback capacitor 3 is connected; A PMOS transistor switch 60-2, a PMOS transistor switch 60-2 whose drain is connected to the input terminal of , and whose gate is connected to the clock signal φ, and a PMO8+-transistor switch 60-2.
The NMOS transistor switch 60-1 has a drain connected to the source thereof, a source connected to the ground, and a gate connected to the clock signal φ.

The operation of this circuit is that the clock signal φ is at a high level and o - L.
/ It can be divided into two cases: F/L/. At high level, NMo5 transistor switch 5°-1,60
-1 is on, PMOS transistor switch 5
0-2.60-2 is off. Therefore, the input signal 1 is the NMo5 transistor switch 50-1.60-1
The input capacitor 2 is charged through the input capacitor 2. Next, when the clock signal φ becomes low level, the NMo5 transistor switch 50-1.60-1 is turned off and the PMO8 transistor switch 50-2.60-2 is turned on. Therefore, the charge on the input capacitor 2 is transferred to the feedback capacitor 3, and an output signal 7 obtained by integrating the input signal 1 is obtained.

In addition, when the embodiment of FIG. 3 is configured with CMOS transistor switches, the transistors 5°-1, 50-2
, 60-1, 60-2, transistors with channels of opposite polarity are connected in parallel to the sources and drains of the transistors 60-1, 60-2, respectively, and a clock signal 1 obtained by inverting the clock signal φ is applied to their gates.

According to this embodiment, the number of clock signals for the SC circuit can be reduced from two in the conventional circuit shown in FIG. 1 to one. This example is an example of a simple SC circuit, but it is a general complex SC circuit.
In circuits as well, although the number of switches increases, in most cases the number of combinations of switches whose on and off states can be reversed and the number of clock signals increases. Therefore, even in such a case, the number of clock signals can be reduced to about half of the conventional one by combining the switches according to the present invention and replacing the NMOS transistor switch with a PMOS transistor switch.

In addition, as suggested in the above explanation, in the case of the present invention,
At the time of the clock signal transition, both the NMo5 transistor switch and the PMOS transistor switch pair are in an intermediate state between on and off. Therefore, in order to realize a highly accurate SC circuit, the rise time and fall time of the clock signal must be the product of the on-resistance of the switch and the SC capacitor (for example, NMOS switches 50-1 and 60-1 in FIG. 3). (product of on-resistance set and capacitor 2). When constructing an actual SC circuit, the SC circuit capacitor (for example, 2, 3) should be made larger, the switch transistor (for example, 50-1.50-2.60-1.
6O-2) (channel width/channel length), increase the resistance of the signal wiring to the switch (using polysilicon or diffusion layer wiring), and the rise and fall times of the clock signal (for example, φ). Consideration, such as making it small, is necessary if high-precision operation is the aim.

〔Effect of the invention〕

As explained above, according to the present invention, the number of clock signals in a switched capacitor circuit can be reduced, so the area of clock wiring and drivers can be reduced, and when converting a switched capacitor circuit into an LSI, the chip area can be reduced or High integration becomes possible.

[Brief explanation of the drawing]

Figure 1 shows an example of a conventional switched capacitor circuit. FIG. 2 shows the clock signal), and FIG. 3 shows an embodiment of the switched capacitor circuit of the present invention. 1... Input signal, 2... Input capacitor, 3... Feedback capacitor, 4... High gain IfM device, 5, 6...
・Switch, 50-1.60-1...NMOS transistor switch, 50-2.60-2...PMOS transistor

Claims (1)

[Claims] A switched capacitor circuit including a capacitor and a switch connected to an electrode of the capacitor, the switch having an on state and an off state reversed from each other.
A combination of an S transistor and a PMOS transistor is used, and the same clock signal is applied to the gates of the two types of transistors to control the state in which the switch by the NMOS transistor is on and the switch by the PMOS transistor is off, and vice versa. A switched capacitor circuit characterized by being able to perform the following functions.