JPS61261900A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To execute easily the effective test of an EPROM by providing a mask ROM to store an EPROM and a program for a test in the same chip. CONSTITUTION:An EPROM 11 and a mask ROM 12 are arranged in the same chip, the chip is connected to a micro processor 13, the enable signal is supplied from a terminal 16, the ROM 12 is made active and then, based upon the test program stored at the ROM 12, the EPROM 11 is tested. Consequently, it is not necessary to connect the large-sized tester and the test of the EPROM can be easily executed effectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device that enables effective testing of a semiconductor nonvolatile memory, particularly an EPROM.

[Background technology] EPRO installed in a semiconductor integrated circuit device
Conventionally, testing of non-volatile memories using M or the like has generally been carried out using large, expensive testers. For this reason, various methods have been proposed to test such non-volatile memories by simple means, such as the method disclosed in Japanese Patent Application Laid-Open No. 58-53093. ing.

In other words, the means shown here is to separately prepare a memory cell that stores a code corresponding to the test program when testing a mask ROM, thereby automating the test of the mask ROM board. This is what you want to do so that it can be executed. Specifically, a code determined corresponding to the information content stored in the mask ROM under test is stored and set in a memory cell having the same mask ROM structure. Then, the tester itself selects a test program prepared in advance, and the test is automatically executed.

In addition, a one-chip microcomputer has a built-in mask ROM in which a test program is stored, and the microprocessor itself executes the program in the mask ROM.

This allows the self-test to be executed.

Furthermore, as an example of integrating EPROM and mask ROM in general-purpose EPROMIC,
It has a silicon signature. This is used to mask the code corresponding to the writing conditions etc. when writing to EPROM.
Make memory settings for OM, and set PRO when writing.
The M writer reads the code to facilitate the write operation.

However, with these means, when the capacity of the memory increases, the test becomes more complicated as the capacity increases.

[Problems to be Solved by the Invention] This invention has been made in view of the above-mentioned points. It is an object of the present invention to provide a semiconductor integrated circuit device in which a memory test can be easily and reliably executed, and in particular can effectively cope with the increase in memory capacity.

[Means for Solving the Problems] That is, in the semiconductor integrated circuit device according to the present invention, a nonvolatile memory using an EPROM, a mask ROM storing a test program for this memory, and a mask ROM that stores a program for testing this memory are included in the same chip. The microprocessor accesses the mask ROM and tests the nonvolatile memory in accordance with the stored test program.

[Operation] In the semiconductor integrated circuit device configured as described above, the test program is stored in the mask ROM, so if the mask ROM is accessed by the microprocessor, the above storage A test of the nonvolatile memory will be executed according to the set test program. In this case, the test program stored in the mask ROM is set according to the capacity and bit configuration of the nonvolatile memory, and this program is stored in accordance with the instruction code of the microprocessor. That's what I do.

Therefore, tests corresponding to the contents of the nonvolatile memory and corresponding to the capacity state can be effectively executed.

[Embodiments of the invention] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

Figure 1 shows its configuration; in this case, a general-purpose EPRO
MIC is shown. That is, in this semiconductor integrated circuit, a nonvolatile memory 11 made of EPROM is set, and a mask ROM 12 is formed which is set in the same integrated circuit as this memory 11. This mask ROM 12 stores and sets a test program for the nonvolatile memory 11. Further, a microprocessor 13 is used in combination with this integrated circuit, and this microprocessor 13, the nonvolatile memory 11, and a mask ROM 1 are used in combination.
2, an address bus 14 and a data bus 15 are connected to
is set. For example, an enable command is given to the mask ROM 12 from a test terminal 16.

That is, in the integrated circuit device configured as described above, the test terminal 16 is set to an enabled state when setting the D1-mode. The microprocessor 13 accesses the mask ROM 12 via the address bus 14 and the data bus 15. Through this access, the test program stored in the mask ROM 12 is read out, and the nonvolatile memory 11 is tested. will be executed.

In this case, a test program corresponding to the capacity, bit configuration, etc. of the nonvolatile memory 11 is stored in the mask ROM 12 using the instruction code of the microprocessor 13. Therefore, the non-volatile memory 1
1 matches the contents of this memory 11,
It comes to be executed in response to instructions from the microprocessor 13.

When performing such a test, the nonvolatile memory 11
The address space of the mask ROM 12 must be set separately. However, this can be easily achieved by additionally configuring an address bus.

Figure 2 shows the mask ROM that stores and sets the test program.
This figure shows the configuration of 12 address spaces. In this case, the capacity of the nonvolatile memory 11 is 64 Kbits, and the bit configuration is 8 bits. In other words, $0 of this ROM12
The address space 21 of the nonvolatile memory 11 is from 000 to $1 FFF, and the address space 21 from $2000 is the mask ROM 1.
2 address space. And the above address space 2
1, the test program is set to be stored in the nonvolatile memory 11.

In other words, if the memory 11 is tested by such means, in a semiconductor integrated circuit device including an EPROM (particularly 0TP), by switching from the system operation mode to the EPROM test diagnosis mode, the non-volatile memory can be tested. A self-diagnosis of the EPROM constituting part 11 is executed, and it is highly effective in improving the reliability of this system.

Furthermore, even if the contents of the nonvolatile memory 11 are erased by ultraviolet rays or the like, the test program in the mask ROM 12 will not be erased, and the nonvolatile memory 11 will not be erased.
Testing after erasing step 1 is also possible.

In the above embodiment, the nonvolatile memory 11 and the mask RO
The microprocessor 13 is shown to be set up independently of the chip that forms M12. However, the microprocessor 13 may be integrated with the nonvolatile memory 11 and the mask ROM 12 and configured in a single state (71). This is equivalent to a 1-chip microcomputer (Ko-Q) with a built-in EPROM and a built-in EPROM test program.

[Effects of the Invention] As described above, in the semiconductor integrated circuit device according to the present invention, a test program corresponding to the capacity, bit configuration, etc. of the nonvolatile memory set in the integrated circuit can be stored in the same chip. The non-volatile memory is stored and set in a mask ROM set to 1, so that the test of the non-volatile memory can be effectively executed by commands from a microprocessor or the like. In this case, the test program stored in the mask ROM is
Since the state is set to correspond to the configuration of the non-volatile memory being tested, the test can be easily performed even if the capacity of the non-volatile memory has been increased, for example. It is something.

[Brief explanation of drawings]

FIG. 1 is a block diagram illustrating a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a diagram showing the structure of an address space of a mask ROM used in the above embodiment. 11...Nonvolatile memory (EPROM), 12...
・Mask ROM, 13...Microprocessor, 14
...Address bus, 15...Data bus, 16...
・Test terminal, 21... EPROM address space, 2
2...Mask ROM address space.

Claims (1)

[Scope of Claims] A semiconductor non-volatile memory; a mask ROM formed on the same semiconductor chip with the non-volatile memory and storing a program for testing the memory; and a mask ROM that is accessed and stored in the ROM. means for executing a test of the non-volatile memory by a test program written in the mask ROM, and the mask ROM includes:
A semiconductor integrated circuit device characterized in that an address space of the nonvolatile memory is set in a specific manner.