JPS61260711A - Timing signal generating circuit - Google Patents

Abstract

PURPOSE:To prevent the reduction in the pulse width of a timing signal by providing a basic clock generating means and a means changing the basic clock period of the basic clock generating means for synchronization. CONSTITUTION:When the level of a DATA-OUT signal goes to logical 1 while the level of a CLK 4 is logical 1, FF circuits 2a-7a, 75 in reset state start shift operation based on VCOs 1, 2 by using an IR signal. After the CLK 4 signal goes to '1', a CLK 5 signal goes to '1' by the 4th leading, the CLKA signal goes to logical 1 at the 5th leading with a delay for one period's content. Thus, a logical 1 of the CLKA signal is fed to a terminal D of the FF circuit 2a to start the shift repetitively and the logical 1 of the DATA-OUT signal outputs timing signals CLKs 0-5 synchronously with the CLK 2 signal.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a timing signal generation circuit, and particularly to a circuit that generates a timing signal by inputting the output of a voltage controlled oscillator and data output from a phase locked circuit. The present invention also relates to a timing signal generation circuit suitable for ensuring the pulse width of the timing signal.

[Background of the invention]

In a magnetic tape device or the like, a phase synchronization circuit 10 and a timing signal generation circuit 60 shown in FIG. 3 are used to generate a timing signal synchronized with data read from a storage medium.

That is, the phase synchronization circuit 10 has a frequency tracking function to cope with frequency fluctuations of the read data (DATA-IN) signal caused by changes in the running speed of the storage medium, power supply voltage, ambient temperature, etc., and a pattern peak shift function. , a phase comparator 20 that detects the phase difference between the DATA-IN signal and the VCO-OUT signal, and its detection signal. a low-pass filter 30 that smoothes the signal and outputs a DC signal proportional to the phase difference; a voltage controlled oscillator 11t (VCO) 40 that controls the oscillation frequency with the DC signal and outputs a VCO-OUT signal; VCO-0
A theta discrimination window is generated based on the UT signal, and the DATA
It is composed of a data discrimination circuit 50 that discriminates between data (or data and clock) and synchronizes the DATA-OUT signal according to the timing of the -IN signal.

On the other hand, the timing signal generation circuit 60 includes VCO-OU
A function for frequency dividing the T signal into timing signals CLKO~5 for data processing control in other circuits, and a function for dividing one of the timing signals consisting of multiple bits into the DAT.
In order to provide a function for synchronizing with the A-OUT signal, the circuit configuration shown in FIG. 4 is used.

The timing signal generation circuit 60 includes FF circuits 2 to 7 that frequency divide the VCOs 1 and 2 into timing signals CLKO to CLKO5, and D
ATA-OUT signal and clock phase adjustment timing (C
T) AND circuit 8 that ANDs the signal and the AND circuit 8
OR to logically add the output of and the initial reset (IR) signal
It consists of circuit l. Note that VCOI and VCO2 are VCO-0UT signals whose waveforms are in opposite phases to each other, CT is a signal that is sent out during the synchronization area of the gap on the track of the storage medium and instructs synchronization, and IR is F
This is a signal that initializes the F circuits 2 to 7 to set/reset.

The operation of the timing signal generation circuit 60 with the above configuration is performed when the CT multiplied signal is 0'' shown in FIG.
If you do not want to synchronize CLKO~5 with the OUT signal, I
The R-multiplied signal 'I'' passes through the OR circuit 1 and passes through the FF circuits 2 and 3.
, 6.7 to the R terminal to reset the CLK
o, 1, 4.5 to '0', and at the same time, the FF circuit 4,
It also joins the S terminal of CLK2 and CLK3 to set it to the set state.
Set to "1". After changing to the IR double signal II O11, the D terminal becomes "0" due to the first rise of VCO2.
FF circuit 4 whose D terminal is '1'' and FF circuit 6 whose D terminal is '1''
and invert each output CLK2 to 0''.

Set CLK4 to "L". Similarly, at the first rise of VCO1, FF circuits 5 and 7 are inverted to make CLK3°5 , ou and u 11', respectively. VCO2 (7
) at the second rising edge of CLK4. O respectively I Q I
Make it I, II I II. c at startup iJ of VCOl
Set LK5.1 to uO11゜''1''.

In this way, based on VCOI, 2, FF circuits 2 to 7'
1'' is shifted in a link-like manner, and the CLKO~5 signal is generated at the timing shown in Fig. 5.
T1 in the figure is the pulse width of the timing signal CLKO~5, which is equal to the cycle time of VCO1.

On the other hand, in the case of CT multiplied signal II I11, that is, CL
When synchronizing KO~5 with the DATA-OUT signal, initialize the IR double signal FF circuits 2~7 in the same way as above,
Based on the rise of VCO1 or 2, the FF circuits 11111 of FF circuits 2 to 7 are caused to shift in a ring shape. However, the CT multiplied signal ``1'' and the first bit of the DATA-OUT signal pass through the AND circuit 8° and the OR circuit 1, and similarly to the IR multiplied signal, the FF circuit 2°3.6.7 is reset.
Since F circuits 4 and 5 are set, CLKo,
1, 4.5 are LL O11, CLK2, 3 are rr 1
becomes #. From the second bit onward, only the FF circuit 3 is inverted, and the pulse width of CLK1 is shortened to T2, which is a problem. This means that when the frequency of the VCO-OUT signal becomes higher (T1→smaller) and the pulse width of the CLKI signal becomes narrower (T2→smaller), the FF circuit in other control circuits that use the timing signal CLKO~5 mentioned above. This was causing malfunctions such as not being able to set the settings.

[Purpose of the invention]

An object of the present invention is to solve such conventional problems and to solve the above-mentioned timing signal that occurs when the data processing control timing signal CLKO~5 is synchronized with the DATA-OUT signal using a simple and inexpensive method. An object of the present invention is to provide a timing signal generation circuit that can prevent reduction in pulse width.

[Summary of the invention]

In order to achieve the above object, the timing signal generation circuit of the present invention has means for generating a timing signal by frequency-dividing the VCO output of the phase-locked circuit, and synchronizes the timing signal with the data output of the phase-locked circuit. basic clock generating means (FF circuit 75) for generating a basic clock which is a frequency division condition of the timing signal generating means from the VCO output;
means (NAND circuit 7) for changing the basic clock cycle of the basic clock generating means to perform the synchronization;
2).

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of a timing signal generation circuit showing one embodiment of the present invention, and FIG. 2 is an operation time chart of FIG. 1.

In FIG. 1, 70 indicates NAND circuits 71 to 73, OR
A basic clock signal generation circuit 60a is composed of a circuit 74 and an FF circuit 75 and controls the frequency dividing operation of the FF circuits 28 to 7a by a method described later.
This timing signal generation circuit generates six types of timing signals CLKO to CLKO5 by dividing the frequency of the CO-OUT signal by FF circuits 2a to 7a. In addition, vC of the VCO-OUT signal
ol and VCo2 are FF circuits 3a and 5a, respectively.

The T terminals of FF circuits 2a, 4a, 6a are connected to the T terminals of 7a, 75.
Connect to the terminal.

The timing signal generation circuit 60a outputs the initial reset (IR) signal when the clock phase adjustment timing (CT) signal shown in FIG. 1
", all of the FF circuits 2a to 7a and the FF circuit 75 are reset, and all of CLKO to 5.A are set to the 0" level. After the IR multiplied signal changes to 0'', the FF circuit 75 is set by the first rise of the VCo 1 multiplied signal, and the C
The LKA signal becomes l I II. The subsequent fall, that is, the first rise of the vC02 signal, sets the FF circuit 2a receiving 0111 of the CLKA signal at its D terminal, and the CLKO signal becomes 1''.The second rise of the VCO1 signal causes the CLKO signal to change to 1''. II +, II to D
At the same time that the FF circuit 3a received at the terminal is set and the CLK1 signal becomes "1", the FF circuit 3a whose D terminal is "0"
The circuit 75 is reset and the CLKA signal becomes 0'' again. In this way, the FF circuits 4a, 5a+, .

By repeating the set/reset operation as 2a..., CLKO~5 is set to VCO 1, 2 (711 cycles, count 11).
11Z becomes a waveform in which the two-cycle period is "0", and its timing becomes CLKo, 1. ...5,0,1゜...
. . . is shifted by 1/2 period of VCO1. Note that T3 in the figure is one cycle time of the CLKA and O to 5 signals, which is three times the VC01 cycle.

Also, since +11 II of the CLK2 signal is applied to the R terminal of the FF circuit 75 through the OR circuit 74, the FF circuit 75
(7) “O”L/Bevel VCo 1 cycle double tonari,
The timing is the same as the waveform of the CLK5 signal.

Next, the case (1) of the CT multiplied signal 1'' shown in FIG.

In other words, the timing signal CLKO~5 is set to DATA-OU.
When synchronizing with T signal, DA for synchronization
When the TA-OUT signal becomes 11117 during the rr 1 rr of the CLK4 signal, the FF circuits 2a to 7a, 75 which are in the reset state by the IR double signal are similar to the above.
starts a shift operation based on VCOL,2, and C
After the LK4 signal becomes "1", the CLK5 signal becomes "1" at the fourth rise of vcoi, but the CLKA signal becomes "1" at the fifth rise, delayed by one cycle.

This is because the CLKO signal is 0", so the DATA-OUT
This is to reset the FF circuit 75 by passing through the NAND circuit 73, 72° OR circuit 74 and invalidating the fourth rising edge.After this, the 1" of the CLKA signal passes through the FF circuit 73 and 72° OR circuit 74. By applying the signal to the D terminal of 2a, the same shift operation as above starts, and by repeating it, the DATA-
1" of the OUT signal outputs a timing signal CLKO~5 that is synchronized with 111+7 of the CLK2 signal. Note that the reset of the FF circuit 75 during synchronization is performed using CLK2 and D.
This is done using both ATA and OUT signals.

Next, in case (2) of the CT multiplied signal 1" shown in FIG. 2, that is, when the timing signals CLKO~5 are synchronized with the DATA-OUT signal,
-OUT signal is rt 1 while CLKO signal is '1'
If it becomes rr, as above, the IR multiplied signal LL
FF circuits 2a to 7a, 75 in the reset state at 171
starts a shift operation based on VCOI,2, and C
C at "1'" of LKA signal and the fourth rising edge of VCo2.
After setting the LK1 double sign to '1'', the CLK5 signal is output to the VCO.
It becomes ``0°'' due to the rise of 5#El of l, but
The CLKA signal becomes 0 at the fifth falling edge of VCO1, and the period between levels "1 and rr" is 1.5 times one cycle of VCo.

This is because the CLKO signal is -111 (the O output terminal of the FF circuit 2a is 'O'), so the + of the DATA-OUT signal is
1'' passes through the NAND circuits 73 and 71 to set the FF circuit 75, invalidating the 5th rising edge of VCO1°, and at the same time, the 5th rising edge of VCO2 causes CLK to be set.
This is because the FF circuit 4a receiving 1 times the signal II I II at its D terminal is set, and the CLK2 signal becomes 11111, passes through the OR circuit 74, and continuously resets the FF circuit 75.

After this, at the sixth rise of VCo2, the CLKO signal becomes 'O' and the CLK4 signal becomes '1', and the level becomes 11111.
The interval is sequentially shifted by a pulse width of two cycles.

Note that the 7th rising edge of VCOl for the FF circuit 75 is invalidated by the continuous rr I II of the CLK2 signal, and the subsequent 8th rising edge is invalidated by the DATA-OUT signal since the CLKO borrowed sign is '0''. 2nd bit 17)
"1" is NAND times M73, 72. It is made invalid by being reset through the OR circuit 74, and the 2.
Set the CLKA signal to ``0'' state for 5 times.After this,
At the 9th rise of vco t, the FF circuit 75 is set, and the CLKA signal is set to II 14' to start the FF circuit wI.
By applying the DATA-OUT signal (7) to the D terminal of 2a, the same shift operation as above starts and is repeated.
) II II II outputs a timing signal CLKO~5 synchronized with '1' of the CLK2 signal.

Regarding the case of the CT double signal '1'', in addition to the two examples mentioned above, the DATA-O1JT signal is the 111 I of the CLK2 signal.
In some cases, the value becomes 1'' during the I period, but since this is normal timing, the explanation will be omitted.

(Effects of the Invention) As explained above, according to the present invention, data output (D
1°' of ATA-OUT signal) is CLKO or CLK
4 signal, the basic clock (CL
K A) Since the period is changed to synchronize the data processing control timing signal (CLKO~5) with data output, the pulse width of the data processing control timing signal can be reduced by synchronization without using special circuit components. can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a timing signal generation circuit showing an embodiment of the present invention, FIG. 2 is an operation time chart of FIG. FIG. 4 is a circuit diagram of a conventional timing signal generation circuit, and FIG. 5 is an operation time chart of FIG. 4. 1.74: OR circuit, 2-7.2a-7a, 75: FF
circuit, 8: AND circuit, 10: phase locked circuit, 20: phase comparator, 30: low pass filter, 40: voltage controlled oscillator (
VCO), 50: data discrimination circuit, 60.60a: timing signal generation circuit, 70: basic clock signal generation circuit, 71 to 73: NAND circuit.

Claims (1)

[Claims] (1) In a timing signal generation circuit that has means for generating a timing signal by frequency dividing the VCO output of the phase-locked circuit, and synchronizes the timing signal with the data output of the phase-locked circuit and sends out the timing signal, the VCO output A basic clock generating means for generating a basic clock that is a frequency division condition of the timing signal generating means from the above, and a means for changing the basic clock cycle of the basic clock generating means to perform the synchronization. timing signal generation circuit.