JPS61260649A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61260649A JPS61260649A JP10290285A JP10290285A JPS61260649A JP S61260649 A JPS61260649 A JP S61260649A JP 10290285 A JP10290285 A JP 10290285A JP 10290285 A JP10290285 A JP 10290285A JP S61260649 A JPS61260649 A JP S61260649A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- performance
- retained
- erased
- wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
- H01L2223/5448—Located on chip prior to dicing and remaining on chip after dicing
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体集積回路において、最終工程後のウェ
ーハチェック時に、チップの性能などを段階分けし、そ
の結果をチップ上に表示し選別することに関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention is a semiconductor integrated circuit that classifies chip performance, etc. when checking a wafer after the final process, and displays the results on the chip for selection. Regarding things.
従来技術においては、ウェーハからチップに分割した後
、各チップの性能を外観よシ判別する事は不可能で、I
Cとして組立てた後、改めて選別機にて区分けする必敬
があった。In the conventional technology, after the wafer is divided into chips, it is impossible to determine the performance of each chip based on its appearance, and the I
After assembling it as C, it was necessary to sort it again using a sorting machine.
上述した従来のチップの選別法は、ダイシング工程後、
ICとして組み立てるまで不可能であシ、徴求する性能
を示すチップ以外のチップまで組立てなけれはカらカい
という欠点があった。In the conventional chip sorting method described above, after the dicing process,
This was impossible until it was assembled as an IC, and it had the disadvantage that it would be cumbersome unless other chips than those exhibiting the desired performance were assembled.
本発明は、ウェーハチェック時にチップの性能を測定し
、チップ内にパターンニングのとき同時に作シこんだ複
数の標識を、前記測定結果に応じて一部、または、全て
を消去し、外観だけでチップの性能を判別出来る表示を
している。The present invention measures the performance of a chip when checking a wafer, erases some or all of the multiple marks that were simultaneously printed on the chip during patterning, depending on the measurement results, and removes only the external appearance. It has a display that allows you to judge the performance of the chip.
つぎに本発明を実施例によシ説明する。 Next, the present invention will be explained using examples.
第1図1al 、 (blは、本発明の一実施例に係る
チップの性能判別St識について説明するための平面図
である。まず1w、1図(a)のように、半導体ウェー
ハ内のスクライプ領域3で囲まれた各チップ領域内に、
例えは、アルミによる配線パターンlの形成と同時に、
チップ内の不要な部分2内に、アルミ層でA、L(、C
の英文字を作シ込んでおく。それから最終工程後のウェ
ーハチェックにおいて、各チップの性能を測定し、性能
の区分段階なA。1A and 1A are plan views for explaining the chip performance discrimination method according to an embodiment of the present invention. First, as shown in FIG. 1W and FIG. In each chip area surrounded by area 3,
For example, at the same time as forming the wiring pattern l using aluminum,
A, L (, C
Write down the English letters. Then, in the wafer check after the final process, the performance of each chip is measured and the performance is classified.
B 、 Cの3段階に区分けしたとき、Aの性能段階に
あるものに対し、麺1図1b)のように、アルミの標識
A 、 H、CのうちAを残して残りのIJ 、 Cを
レーザによっ″′C消去する。1川様にチップの性能区
分がBの一合ねBf、CQ)場合はCの榛鍼を残して、
その他は消去する。よって、このチップの性能は、それ
ぞれ、残された標識によシ容易に判別できる。When classifying into three stages, B and C, for those in the performance stage A, as shown in Figure 1b), of the aluminum labels A, H, and C, leave A and the remaining IJ and C. ``'C is erased by a laser. If the chip's performance classification is B (Bf, CQ), leave the C acupuncture,
Delete the others. Therefore, the performance of each chip can be easily determined based on the marks left behind.
第2図ta+は、性能判別標識として、チップ内の不要
部分2内に、4個の四角ガドット5を湛べて形成した例
の平面図であり、第2図Tblのように、残されたドツ
ト50位置によシ、轟該チップの性能区分が表示される
。Fig. 2 ta+ is a plan view of an example in which four square gadots 5 are formed in the unnecessary part 2 in the chip as a performance discrimination mark, and as shown in Fig. 2 Tbl, the remaining Depending on the dot 50 position, the performance classification of the chip is displayed.
第3図ial 、 (blVi、性能判別標識として、
1,2゜3の3数字を用いた例を示す。第2図1blO
ようV(レーザなどによって残された数字がそのまま、
にl−能区分3なる性能を乃くすのである。Figure 3 ial, (blVi, as a performance indicator,
An example using three numbers 1, 2°3 is shown. Figure 2 1blO
YoV (numbers left by laser etc. remain as they are,
This results in a performance of class 3.
なお上記実施例は、アルミ層で標識を作り込んでいるが
、これはアルミに限らず、物理的、あるいは化学的に容
易に消去でき、残されたものが容易に判別でき、チップ
を汚染するものでなけれは使用できる。また、レーザに
より消去しているが。In the above example, the mark is made of an aluminum layer, but this is not limited to aluminum and can be easily erased physically or chemically, making it easy to identify what is left behind and preventing it from contaminating the chip. You can use it as long as it's not a thing. Also, it is erased by laser.
レーザ以外の方法で消去Jることもでき、また、化学的
にエツチングで性能を表示することもできる。It is also possible to erase by a method other than laser, and the performance can also be displayed by chemical etching.
以上説明したように1本発明は、ウエーノ・チェック時
にチップの性能区分に応じて、パクーニングした標識の
一部、筐たは、全部を消去することによって、チップの
段階でチップの外観だけで性能区分の判別が可能であシ
、市場費求に応じた性能のものを選別する場合、むだな
く、すげやく対応出来るので非常に効果的である。前記
の判別の為のea識ね、ウェーハチェック時(1’/W
)に針傷で示すことも可能であり、相対比精度の要求
されるA/D 、D/Aを含んだLSIKI&適である
。As explained above, (1) the present invention makes it possible to improve the performance of the chip at the chip stage by erasing part, the casing, or all of the markings that have been punctured depending on the performance classification of the chip during the Ueno check. It is possible to distinguish between categories, and when selecting products with performance that meets market costs, it is very effective because it can be handled quickly and without waste. When checking the wafer (1'/W),
) can also be indicated by a needle wound, and is suitable for LSIKI & D/A, which require relative precision.
第1図(a) 、 (+)lは本発明cii>一実施例
に係るチップ性能表示の一例を示す平面図、第2図1a
) 、 (b)は四角ドツト標識によるチップ性能表示
の例を示す平面図、第3図は数字標識によるチップ性能
表示例を示す平面図である。
1・・・・・・配線パターン、2・・・・・・不要部分
、3・・・・・・スクライプ領域、5・・・・・・ドツ
ト標識。
にジ
第。
(bノ
ゴ図FIG. 1(a) and (+)l are plan views showing an example of chip performance display according to the present invention cii>one embodiment; FIG. 2(a)
), (b) is a plan view showing an example of chip performance display using square dot indicators, and FIG. 3 is a plan view showing an example of chip performance display using numerical indicators. 1...Wiring pattern, 2...Unnecessary portion, 3...Scribe area, 5...Dot mark. Second time. (bnogo diagram
Claims (1)
ウェーハ内の各チップ内に該チップの性能表示用の複数
個の標識を形成しておき、ダイシング工程前の前記ウェ
ーハのチエック時に各チップを測定し、測定結果に応じ
て各チップの前記複数個の標識の一部または全べてを消
去することにより、該チップの性能を表示選別すること
を特徴とする半導体装置の製造方法。In the manufacturing process of semiconductor devices, a plurality of marks for indicating the performance of the chips are formed in each chip in the wafer at the same time as patterning, and each chip is measured when checking the wafer before the dicing process. A method for manufacturing a semiconductor device, characterized in that the performance of each chip is displayed and selected by erasing some or all of the plurality of marks of each chip depending on the result.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10290285A JPS61260649A (en) | 1985-05-15 | 1985-05-15 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10290285A JPS61260649A (en) | 1985-05-15 | 1985-05-15 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61260649A true JPS61260649A (en) | 1986-11-18 |
Family
ID=14339789
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10290285A Pending JPS61260649A (en) | 1985-05-15 | 1985-05-15 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61260649A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07147302A (en) * | 1993-11-25 | 1995-06-06 | Nec Corp | Classification of semiconductor chip according to characteristics |
-
1985
- 1985-05-15 JP JP10290285A patent/JPS61260649A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07147302A (en) * | 1993-11-25 | 1995-06-06 | Nec Corp | Classification of semiconductor chip according to characteristics |
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