JPS61260352A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To avoid occurrence of system down by a relatively simple and inexpensive additional circuit by making one of REQUESTING UNITs supply a bus clock signal on a bus clock signal line according to a predetermined order when the bus clock on the signal line disappeared. CONSTITUTION:In the initial state, an F/F 13 is reset by a signal INIT and a buffer gate 9 is closed and a bus clock signal 16 is not outputted from any of REQUESTING UNITs. This state is detected by a clock monitoring circuit 15, and a counter circuit 11 counts output pulse of an oscillator. When the counted value coincides with a value set to a setting switch 10, a signal is outputted from a comparator 12 to set the F/F, and the buffer gate is controlled to on state, and the output of the oscillator 8 is sent on a system bus 5 as the bus clock signal 16. As the numerical values of the setting switch 10 are different, the bus clock signal 16 is outputted from only one microprocessor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiprocessor system used for plant process control and the like.

[Conventional technology]

When each unit such as a processor, a storage device, an input/output device, etc. is called a module, a plurality of modules are connected to a common system bus to configure a multiprocessor system.

Figure 3 shows, for example, MULTIBUS from Intel1 in the United States.
IIARCHITECTURE DATABOOK (1
984) is a block diagram of a conventional multiprocessor system shown in FIG. In the figure (1a)...(1n
) are each a microprocessor, and (2) t:t
Although it is a microprocessor, it differs from other microprocessors (1a)...(in) in that it has a central service module (3) completely built-in. (4a)...
(4m) is an input/output device, and (5) is a system bus.

Connected to a common system bus (1a)...(in
), (2), (4a)...(4m), etc. are each called a module, and each module includes a processor,
In addition to input/output devices, storage devices and others are also included, and some of these modules include modules that can acquire bus usage rights, such as microprocessors, and modules that can acquire bus usage rights, such as relatively simple input/output devices. There is a module that receives a data transfer request from a microprocessor and returns a response via the bus used by the microprocessor, without acquiring data.The former is called REQUESTINGAGENT,
The latter is called t-REPLYING AGENT.

In Figure 3, (1a)...(in), (2) are generally speaking REQUESTING AGENT, and (4a) and (4m) are REPLYING AGENT.
ENT, but in the following explanation, they will be explained as a microprocessor and an input/output device, respectively. System bus (5
) includes an address bus, a data bus, and a control signal 1fs. The control signal lines include a bus clock signal line that transmits a system clock (referred to as a bus clock signal in this specification) that is commonly used in each module.

Next, the operation will be explained.

Transfer operations on the system bus (5) are basically Arbi
It consists of a bus arbitration cycle called a transaction cycle and a transfer cycle called a transfer cycle.

A microprocessor that needs to use the bus (referred to as microprocessor (1a)) outputs a bus use request signal and its own identification number onto the system bus (5). These signals are transmitted to each microprocessor (1a)...(in
) and (2), each of which is identified by a built-in bus arbitration circuit, and controlled so that the microprocessor with the highest priority at that time acquires the right to use the bus. This is called a parallel arbitration operation, and an arbitration cycle is executed by this parallel arbitration operation.

When this arbitration cycle is completed, the microprocessor that has acquired the right to use the bus (microprocessor (1a)) sends addresses, data, and input to a specific REPLYING AGENT (the input/output device (4a)) K. A transfer cycle is executed in such a way that a necessary signal such as a command indicating whether the output is output is output on the system bus 151, and the input/output device (4a) responds to this signal.

A central service module (
3) onto the system bus (5) as the system clock.

[Problem that the invention seeks to solve]

Conventional multiprocessor systems are configured as described above, and although each processor has a built-in bus arbitration circuit and parallel arbitration is possible, the bus clock signal used as the system clock is sent to a central service. Since this problem occurs only in the module (3), if the central service module (3) fails for some reason, the entire system becomes inoperable, resulting in a 5+D system down.

The present invention has been made to solve the above-mentioned problems, and aims to provide a multiprocessor system that does not cause a system down due to a bus clock signal failure.

[Means for solving problems]

In this invention, all REQUEST I
N G AGENT is equipped with a bus arbitration circuit, a bus clock monitoring circuit, and a bus clock supply circuit, and when the bus clock on the bus clock signal line disappears, it will be used in accordance with the predetermined order.
(JNIT now supplies the bus clock signal on the bus clock signal line.

[Effect]

According to this invention, if even one UNIT among "REQUESTING UNII" is operating normally,
! Accidents of loss of the lt bus clock signal do not occur.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.
In the figure, the same reference numerals as in FIG.
In TINGAGENT, (7a) −(7(n-1))
, (7n) ij each microprocessor (6a
)...(6(n-1)), (6n) is a built-in bus clock monitoring/supply circuit.

FIG. 2 is a block diagram showing the internal configuration of the bus clock monitoring/supply circuit in FIG. (9) is a buffer gate, (10) is a setting switch, (11) is a counter circuit, (12) is a comparator, (13) i! Flip-flop (hereinafter abbreviated as &ri), S is its set terminal, R is its reset terminal, Q is its output terminal, (1
4) Vi OR circuit, (15) is clock monitoring circuit, (1
6) is a bus clock signal. Note that the signal shown as INIT at one input of the OR circuit resets FIF (13) at the time of initialization, sets the signal at its Q terminal to logic "0", and generates an oscillator (8) at the buffer gate (9).
) is a signal for blocking the output.

Next, the operation will be explained. The operations other than the supply of the bus clock signal are the same as those of the conventional multiprocessor system, so the explanation thereof will be omitted.

The identification number of each microprocessor is set in the setting switch (10). In the initial state, from the signal INITK
FlF (13) has been reset and is a buffer)
t912>E closed tL Taite (!” OREQUE
Bus clock signal (16) also from STING UNIT
Since the Vi low output is not possible, the bus clock signal is lost on the system bus (5). This state is detected by the clock monitoring and recovery 15), and the counter circuit (11) is controlled to start operating from that point on. The counter circuit (11) counts the output pulses of the oscillator, and when the counted value matches the value set in the setting switch (io), a signal is output from the comparator (12) to set the FIF to the buffer gate. (9) is turned on, and the output of the oscillator (8) is sent onto the system bus (5) as a bus clock signal (16).

By the way, the identification number of each microprocessor is set in the setting switch (10), and each number is different, so the signal is output first from the comparator (12) of the microprocessor to which the smallest number is set. Then, the bus clock signal (16) of that microprocessor is supplied to the system bus (5), inputted to the clock monitoring circuit (15) of the other processor via the system bus (5), and is input to the clock monitoring circuit (15) of the other processor. 11) stop the operation. Therefore, there is only one bus clock signal (16) on the system bus (5) from one microprocessor.
will be output.

Other than the time of initialization, when the microprocessor that has been outputting the bus clock signal (16) fails and the bus clock signal on the system bus (7) is lost, the operation is the same as that at initialization. be.

Next, a description will be given of the operation when the bus clock signal is output from a plurality of microprocessors for some reason and an abnormal state occurs. Bus clock signals from different microprocessors (16) t-1 Although they have the same frequency, they generally do not have the same phase, so the bus clock signals are output from multiple microprocessors and the system bus (5
), the pulse interval of the superimposed pulses is shortened, and this abnormality can be easily detected.

When this type of abnormality is detected, the clock monitoring circuit (15
) resets FIF (13) via the OR circuit (14) and closes the buffer gate +91. When the clock signal (16) is no longer output (from any processor), a clock loss condition occurs on the system bus (5), and the normal state is restored by the same operation as in the clock loss condition.

The output of the oscillator (8) is monitored by the clock monitoring circuit (15), and if the oscillator (8) output is abnormal, FIF (1
3) is reset and the buffer gate (9) is closed.

Note that the present invention can be applied not only to multiprocessor systems but also to general circuits in which a plurality of control circuits use a common system clock through a common path clock signal line.

〔Effect of the invention〕

As described above, according to this invention, all REQUES
Since the bus clock monitoring/supply circuit is provided for the TNG AGENT, system down due to loss of the bus clock signal can be avoided by a relatively simple and inexpensive additional circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing the internal configuration of the path clock monitoring/supply circuit shown in FIG. 1, and FIG. 3 is a block diagram showing a conventional multiprocessor system. It is. (4a), ・(4m) ti input/output devices,
(5) is the system bus, (6a), +++ (6(n
-1)), (6n) are respectively microprocessors,
(7a),...(7(n-1)). (7n) are bus clock monitoring and supply circuits, and (8)
is an oscillator, (9) is a buffer gate, (10) is a setting switch, (11) is a Vi counter circuit, (12) is a comparator, (13) is &, (15) is a clock monitoring circuit,
(16) is a bus clock signal. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] When each unit such as a processor, a storage device, an input/output device, etc. is referred to as a module, in a multiprocessor system configured by a plurality of modules connected to a common system bus, among the plurality of modules described above, Each module capable of acquiring the right to use the system bus is provided with a bus clock monitoring/supply circuit, and this bus clock monitoring/supply circuit includes an oscillator that outputs pulses at a predetermined pulse frequency as a bus clock signal, and a a buffer gate that connects the output pulse of the bus clock signal line to the bus clock signal line in the system bus or cuts it off from the bus clock signal line; a flip-flop that controls the buffer gate; and a flip-flop that monitors the bus clock signal on the bus clock signal line. , if the bus clock signal is not restored within a predetermined time determined for the module after the loss of the bus clock signal is detected, the flip-flop is set and the output pulse of the oscillator is passed through the buffer gate to the bus. and means for monitoring the output of the oscillator and, when detecting an abnormality in the output, resetting the flip-flop and blocking the output pulse of the oscillator by the buffer gate. Features a multiprocessor system.