JPS6126028B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse counting device that counts pulse signals generated in relation to changes in a measured quantity, such as the running speed of an automobile or the rotational speed of an engine.

Generally, to display a measured quantity using a repetitive pulse signal proportional to the measured quantity, the repeated pulse signal proportional to the measured quantity is counted at a gate time set by a reference clock signal, and this counted value is latched. A device is known that displays information in a sequentially updated manner. In this device, the updateable time is determined by setting the gate time using the reference clock signal.
Measurement accuracy depends on the density of the number of repetitive pulses input within this gate time, but in general, pulse generators are quite expensive to increase the density of repetitive pulses that are proportional to the change in the measured quantity. Not only will it be a good thing, but even if it is provided at a low price,
At high speeds, the number of pulses generated within a clock cycle becomes extremely large, requiring an increase in the capacity of the counter, resulting in an overall extremely large and expensive device. Furthermore, a method of increasing the gate time and relatively increasing the input pulse within this gate time can be easily achieved, but this method has the disadvantage that it is not possible to follow sudden changes in the measured quantity. Therefore, in general, when a repetitive pulse proportional to the change in the measured quantity is input to the input terminal 1 as shown in FIG. Counter 2 shifts the counting start time and counts,
When each counter 2 finishes counting, the count value of the counter 2 is stored in registers 3 ₁ , 3 ₂ , 3 ₃ , and 3 ₄ , respectively, and these registers 3 ₁ to _{3 4}
The count values stored in are added by an adder 4, and the value obtained by dividing this added value P by the number of registers (P/4 in this example) is displayed.

To explain the operation of the circuit shown in Fig. 1 using Fig. 2, when a repetitive pulse A proportional to a change in a measured quantity (for example, running speed) is input, when counter 2 finishes counting,
Each display switching time t (for example, 1 sec) is set at t ₁ , t ₂ , t ₃ , and t ₄
The number of repetitive pulses P ₁ , P ₂ , P ₃ , respectively counted in
P ₄ is stored in registers 3 ₄ , 3 ₃ , 3 ₂ , 3 ₁ , respectively, and the stored repetition pulse numbers P ₁ , P ₂ ,
P ₃ and P ₄ are added by adder 4, and (P ₁ +
The traveling speed corresponding to the value of P ₂ +P ₃ +P ₄ )/4 is output and displayed on the display.

Here, the running speed suddenly decreases and at t ₄
Assuming that the speed reaches 0 km/h, at the end of counting by counter 2, at _t5 , the number of repetitive pulses _P5 = 0 counted during the new display switching time _t4 to _t5 is newly stored in register _31.
The number of repetitive pulses P ₁ counted during the oldest display switching time t ₀ to t ₁ is shifted out of the register, added up in the adder 4, and calculated from the arithmetic unit 5 as (P ₂ +
The traveling speed corresponding to the value of P ₃ +P ₄ +0)/4 is output to the display. That is, even though the traveling speed has reached 0 km/h, the traveling speed display does not become 0. At the end of the next count, t ₆ , the display switching time is
The number of repetitive pulses P ₆ =0 counted from t ₅ to t ₆ enters the register ₃₁ , and the number of repetitive pulses P ₂ counted from the display switching time t ₁ to _{t 2} is shifted out of the register. It is added by adder 4, and from arithmetic unit 5 (P ₃ + P ₄
The traveling speed corresponding to the value of +0+0)/4 is displayed. Furthermore, at the end of counting t ₇ , the number of repetitive pulses P ₇ =
0 enters register 3 ₁ , (P ₄ +0+0+0)/
The traveling speed corresponding to the value of 4 is displayed. and,
At the end of counting, t ₈ , the number of repeated pulses P ₈ = 0 is stored in register 3.
₁ , the number of repetitive pulses _P4 counted during the display switching time _t3 to _t4 is shifted out of the register,
The sum of registers ₃₁ to ₃₄ is (0+0+0+
0), and the running speed is 0 km/h starting here.
will be displayed.

As described above, conventional pulse counting devices have the drawback of poor tracking performance, requiring 4 seconds from when the car actually stops until the display reaches 0 km/h.

In order to solve the above-mentioned drawbacks of the conventional example, the present invention multi-divides the gate time that can determine the change in the number of repetitive pulses into the display switching time that switches the display on the display, and the gate time that occurs within this divided gate time. Repetitive pulses are counted by a counter and sequentially stored in multiple registers, and a new register containing the total sum of the contents of the registers stored each time the display switching time elapses and the number of repeated pulses counted at the new display switching time is created. Find the difference between the contents of and the total addition value, and if this difference is within the set value, shift the contents of the register up to that point, and if it is not within the set value, calculate the optimal value using the new number of repetition pulses. The contents of all the registers are rewritten to this value, and the contents of the rewritten registers are used for displaying the respective contents.The purpose is to provide a pulse counting device with good followability. be. below,
Examples will be explained in detail with reference to the drawings.

FIG. 3 shows a circuit diagram of a pulse counting device according to an embodiment of the present invention, where 6 is a timer for setting the display switching time t, and 7 is a counter for counting repetitive pulses A input from terminal 8. ,9 ₁ ,9
₂ , ₉₃ , ₉₄ , and ₉₅ are registers that sequentially shift and record the number of pulses counted by the counter 7 at each time t.
There is one more number than the number (4) divided into. 10
11 is the first adder that calculates the sum of the number of pulses counted at the gate time T before the latest display switching time t, and 11 is the new gate time T that includes the number of pulses counted at the latest display switching time t. a second adder for calculating the sum of the counted number of pulses, 12
13 is a subtracter that determines the difference between the first adder 10 and the second adder 11, 13 is a determiner that determines whether the difference between the subtracters 12 and 12 is within a set value, and 14 is the latest pulse number. An optimum value calculation calculator 15 calculates the optimum numerical value P according to P', a display data calculator 15 determines the numerical value to be displayed based on the value of the second adder 11, and a drive 16 which has a latch function and controls the display. circuit, 17
is an indicator.

Next, the operation of this embodiment will be explained with reference to FIG. First, the number of repetitive pulses P ₁ , P ₂ , P ₃ , P ₄ , counted by the counter 7 at every display switching time t set by the timer 6 for the repetitive pulse A input from the terminal 8 is
Registers 9 ₅ , 9 ₄ , 9 3 , 9 ₂ , 9 ₁ while sequentially shifting P ₅ to counting end times t ₁ , t ₂ , t ₃ , t _{4 ,} t ₅
hold it. In the first adder 10, the register 9 ₅ ,
The total value (P ₁ +P ₂ +P ₃ +P ₄ ) of the number of repetitive pulses counted at 9 ₄ , 9 ₃ , _and 9 2 is calculated, and the second adder 1
Registers 9 ₄ , 9 ₃ , 9 ₂ , 9 including the number of repetitive pulses P ₅ counted at the latest display switching time t ₅ in 1
The sum of the number of repetitive pulses counted in ₁ (P ₂ + P ₃ + P ₄
+P ₅ ), the subtracter 12 calculates |(P ₁ +P ₂ +P ₃
+P ₄ )−(P ₂ +P ₃ +P ₄ +P ₅ ) | is determined, and the determiner 13
Enter. The determiner 13 determines whether the difference output of the subtractor 12 is within the set value K, that is, |(P ₁ +P ₂ +
P ₃ +P ₄ )−(P ₂ +P ₃ +P ₄ +P ₅ )|K is determined, and if the difference value is within the set value K, the output of the determiner 13 is
The display data calculator 15 determines the numerical value to be displayed on the display 17 based on the value of the second adder 11, sends the numerical value to the drive circuit 16, displays it on the display 17, and also sends the numerical value to the drive circuit ₁₆ to display it on the display ₁₇ . The numbers P _{1 ,} P ₂ , P ₃ , P ₄ , and P ₅ of repeated pulses stored in registers 3, _{9 2} , and 9 _{1 are shifted, respectively, and the new numbers of repeated pulses are stored in register 9 1 .}

Here, if the running speed suddenly decreases and reaches 0 km/h at display switching time t ₄ , then the display switching time
At t ₅ , the number of repetition pulses P ₅ =0 counted during the new switching time t ₄ to _{t 5} is input into the register ₉₁ . _{Therefore , the first adder} 10 calculates the sum ( _{P 1}
+P ₂ +P ₃ +P ₄ ), and the second adder ₁₁ outputs the number _of repetition pulses P ₂ ,
The sum of P ₃ , P ₄ , and 0 (P ₂ +P ₃ +P ₄ +0) is output. In the determiner 13, the output of the subtracter 12 |(P ₁ +P ₂
+P ₃ +P ₄ ) - (P ₂ +P ₃ +P ₄ +0) | is not within the set value K, the optimum value calculation calculator 14 calculates the optimum value P' according to the latest pulse number P ₅ =0. seek,
Write the optimum value P' into all registers ₉₁ to ₉₅ , and register 9 rewritten with the optimum value P'.
The data display calculator 15 is controlled to input the contents of ₂ to ₉₄ . In accordance with this command, the data display calculator 15 determines the value to be displayed on the display 17 based on (P'+P'+P'+P')/4=P' added by the second adder 11, and determines the value to be displayed on the display 17. send to In addition,
Generally, the optimal value P' is preferably the newly input number of repetitive pulses P ₅ =0. Further, even when the number of repetitive pulses P increases rapidly, the same operation as described above is displayed.

The flowchart of the above embodiment is as shown in FIG. 5, where ΣP _A is the total sum of the contents of registers ₉₁ to ₉₄ including the new number of repetition pulses, and ΣP _B is the register It is the total addition value of the contents of 9 ₂ to 9 ₅ , K is the set value, and t is the display switching time.

In this embodiment, the difference between the sum of the contents of the registers 9 ₁ to 9 ₄ containing the new number of repetitive pulses and the sum of the contents of the registers 9 ₂ to 9 ₅ that have stored the previous number of pulses is the set value K. Since it is determined whether or not it is within the range of , and the display on the display 17 is rewritten according to the new number of repetition pulses, there is an advantage that followability is improved.

As explained above, according to the present invention, the display is rewritten according to the new number of repetitive pulses input to the counter, so the display does not become 0 a few seconds after the car stops, unlike the conventional example. This method has the advantage of eliminating such inconveniences and improving the ability to follow sudden changes in the measured quantity.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a conventional pulse counting device, Fig. 2 is an explanatory diagram of the operation of Fig. 1, Fig. 3 is a circuit diagram of an embodiment of the present invention, and Fig. 4 is a circuit diagram of Fig. 3. FIG. 5 is a flowchart explaining the operation of FIG. 3. 6...Timer, 7...Counter, 8...Input terminal, ₉₁ , ₉₂ , ₉₃ , ₉₄ , ₉₅ ...Register, 10...First adder, 11...Second addition device, 12...subtractor, 13...determiner, 14...
Optimal value calculation calculator, 15...display data calculator,
16...Drive circuit, 17...Display device.

Claims (1)

[Scope of Claims] 1. A counter that counts the number of repetitive pulses generated in proportion to a change in the measured quantity at each display switching time, a plurality of registers that store the number of repetitive pulses counted by this counter, and the display switching. a subtractor that calculates the difference between the total addition value of the contents of the register and the total addition value of the contents of the register including the latest number of repetition pulses counted at the latest display switching time every time the difference elapses; If the difference is within a certain set value, shift the contents of the register; if the difference is not within the set value, calculate an optimal value from the latest number of repetition pulses and instruct to rewrite the contents of the register; A pulse counting device comprising: an arithmetic unit; and a display device that displays the contents of the register.