JPS61259352A - Memory copy system - Google Patents

Abstract

PURPOSE:To attain high speed copy by writing data other than all '0' to a copy destination memory with a data not all '0' and address information via a central processing unit managing the execution of copy. CONSTITUTION:When the central controller 1 sends a CLR signal to the memory 3 being copy destination, a memory clear circuit 33 clears all areas into zero. Then the controller 1 sends a COPY signal to a memory 2 being a copy sender, a control circuit 22 of the memory 2 receives the COPY signal, then extracts a data sequentially from an address zero and sends the address information and the data to the controller 1. In this case, the result of discrimination of all zero discrimination bit arranged corresponding to each address is received from a discrimination circuit 21, and in case of all zero discrimination, the address is incremented by one to repeat the extraction of the data in the next address. In the case of other than all zero, the address information and the data are sent to the controller 1. The controller 1 sends them to the memory 3 as they are and a memory section 30 sets the data sent from the address zero to the address sent from the controller 1.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a one-sided copy method between duplicated storage devices in a memory copy method 1.411C storage program control method 2.

(Prior art) Conventionally, in storage program control systems, copying between duplicated memories (storage devices) is performed by a central control unit reading from one memory and writing the contents to the other memory. This is done by repeating the address.

(Problems to be Solved by the Invention) In the conventional copying method as described above, it takes a long time to copy everything, including all-zero data that does not need to be copied. There is a drawback.

In the present invention, all areas of the copy destination memory are set to 0 in advance.
The object of the present invention is to solve the above-mentioned drawback by clearing the data and transferring only data other than all 0 from the copy source, and to provide a one-sided copying method that can perform high-speed memory copying.

(Means for Solving the Problems) The memory copy method according to the present invention includes a clear circuit that can clear all areas at once in a memory device, and an all-clear circuit that displays whether or not the data at the address is all 0 in response to an address. 0 indication bit, and a determination circuit that skips data transmission of the address if the all 0 indication bit is 0 when memory copy is specified, and the copy source memory is set to the address information of the address where the all 0 indication bit is not Off according to the copy instruction. The data at the address is sent to the central processing unit, and the central processing unit writes the address information and data to the copy destination memory, thereby copying the entire area.

(Example) Hereinafter, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a memory copy system according to an embodiment of the present invention. A central control unit (central processing unit) 1 has a function of receiving and receiving address information and data from a copy source memory, and also writes it to the copy source. 2
3 is the copy source memory device, and 3 is the copy destination memory device. The memory device will hereinafter be simply referred to as memory. 20° and 30 are the copy source memory 2. Indicates the memory section of copy destination memory 3, Dt+D! + Dn, D
n+t pDH+2 are each memory address X0111n
In+1 I Indicates the data at address n+2 (other than all 0). 0 at address l, J+1, n+2
~0 indicates that the data at the address is all O's. 21. 31 are copy source memory 2°, copy destination memory 30, all 0 judgment circuit %, 22. 32 are copy source memory 2, respectively. This is a control circuit for the copy destination memory 3. The determination circuit 21.31 determines whether the memory control circuit 22
．． 32 to the next address.

23. 33 is a memory all area clear circuit which has a function of clearing all areas in the memory at the same time when one circuit is activated. 24 and 34 are all 0 display bits corresponding to the addresses of memories 2 and 3 as the copy source and copy destination, respectively. In the figure, the copy signal line is an instruction signal to copy, AD
D is an address information signal.

DATA is a data signal, CLR is a clear signal, and the arrow on the signal line indicates the direction of the signal.

Next, the copy operation in this embodiment will be explained step by step. First, the central control unit 1 stores the copy destination memory 31CC.
When the LR signal is sent, the memory clear circuit 33 clears all areas to 0. Thereafter, the central control unit 1 sends a C0PY signal to the copy source memory 2. When the copy source memory 20 control circuit 22 receives the copy signal, it sequentially extracts the data starting from address 0 and sends the address information and data to the central control unit 1. At this time, the judgment result of the all 0 judgment bit set corresponding to the address is is received from the determination circuit 21, and in the case of all 0 determination, the address is updated by +1 and the extraction of data at the next address is repeated. If all values are other than 0, the address information and data are sent to the central control unit 1.

The central control unit IVi sends the address information and data sent from the copy source to the copy destination memory 3 as they are. Therefore, in the memory unit 30 in the copy destination memory 3, only the address sent from the central control unit 1 is set from data 0 to the sent data. Memory copying is performed in the copy destination memory 3 by repeating the operation until the address reaches the O address to the END address. Therefore, in this embodiment, all 0s are included! From the street number! All m words of data up to address O can be copied without going through the central controller 1.

(Effects of the Invention) As explained above, according to the present invention, all 0 data can be copied without going through a central control unit (central processing unit), so all areas can be copied unconditionally unlike in the past. This has the effect of providing a faster memory copying method than a method of copying via a central control unit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a memory copy system according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Central control unit, 2... Copy source memory, 3... Copy destination memory, 20.30... Memory section, 21.31... All 0 judgment circuit, 22.32... Memory control circuit, 23.33...Memory all 0 clear circuit, 24.3
4... All O display bit corresponding to address.

Claims (1)

[Claims] An information bit is provided for each word in the memory to indicate whether the content of the word is all 0 or not, and when copying from one side of the memory to the other, all areas of the copy destination memory are cleared in advance, and the copy source memory When transmitting address information and data at the address, the information bits are determined as to whether all are 0 or not, and only data that is not all 0 and the address information are transmitted through a central processing unit that manages copy execution. A memory copy method characterized in that data other than all 0 is written to a copy destination memory according to the address information.