JPS61259351A - Buffer storage error processing system - Google Patents

Abstract

PURPOSE:To apply buffer storage error processing by providing an error control circuit detecting the presence of an error in a data detected from the storage unit after move-in by a separate access and applying error processing. CONSTITUTION:An error control bit indicating the 1st state representing the absence of an error in each storage unit in a buffer storage array 111, the 2nd state representing generation of an error, and the 3rd state disconnected with the storage unit is provided to an error control bit memory 130 in each storage unit. When an error is detected in the data of the storage unit of the array 111, the error control circuit 140 revises the error control bit in the storage unit in the memory 130 from the 1st state into the end state, the storage unit is made ineffective, the presence of the error in a data read from the storage unit after move-in by separate access is detected to apply error processing.

Description

[Detailed description of the invention] 〔table of contents〕 The present invention will be described in the order of the following items.

A1mRequired B, Industrial field of application C9 Prior art 0 Problems to be solved by the invention E9 Means for solving the problems (Fig. 1) F9 Effects G, Examples (Figs. 2 and 3) Figure) G1. Configuration description G2. Explanation of operation H0 Effect A: In the store-through one-sided buffer strainer processing method using ill-required hardware, after an error occurs, the error location is invalidated and a non-Hi is returned in another access.
When the data moved in from the main memory is read to the location where the error occurred at t, it is determined whether the error is a hard (fixed) error or a soft (intermittent) error based on the presence or absence of an error, and error handling is performed. .

B. Industrial Field of Application The present invention provides a method for determining whether an error occurs in a buffer storage in which writing is performed using a store-through method, whether the error is a soft (intermittent) error or a hard (fixed) error. This invention relates to a buffer storage error handling method that determines whether there is a buffer storage error by simple hardware control and processes the error.

Buffer storage (hereinafter referred to as BS) is a high-speed, small-capacity storage device provided separately from main memory, and stores part of the data on main memory. By accessing this BS, the CPU can shorten the time required to access the main memory and speed up the overall data processing.

Methods of writing data to the BS include store-through (s
tore-through) method and swap (SWA)
P) There is a method. In the store/slew system, data is written to blocks in both the main memory and the BS, and the contents of both blocks always match. In the swap method, only the BS is written and the main memory is not written.

The present invention relates to an error processing method for a store-through type BS, and the BS in the following description is assumed to be a store-through type BS.

When an error occurs in the data retrieved from the BS, processing is different depending on whether the error is a hard error in the BS or a soft error. In the former case, it is a failure of the memory element that makes up the BS, so it is necessary to separate the block and prevent it from being used, and in the latter case, it is a temporary destruction of data due to noise, alpha rays, etc. , the BS hardware is normal. Therefore, if an error occurs in the BS, is the error caused by hardware? It is necessary to determine whether the error is an error or a soft error and then process it.

C. Conventional Technology When an error occurs in the BS, an error processing method using a CPU microprogram and an error processing method using hardware are used.

In the microprogram method, when the microprogram is notified of the occurrence of a BS error from the control unit of the BS, the microprogram performs a predetermined number of attempts at the error location. If this retry fails, it is assumed that it is due to a hard error, and the BS is generally disconnected in block units or WAY units based on the error address notified from the BS control unit at the same time as the error occurs. .

Although it is possible to handle such errors using hardware, since the control to retry at the location where the error occurs is complicated, it is possible to determine whether a BS error is a soft error using simple hardware control. It was difficult to determine whether it was a hard error.

For this reason, conventionally, an error processing method using a CPU microprogram has often been used for error processing in the BS.

Problems that the D0 Invention attempts to solve With the microprogram-based BSS error management method, it is easy to determine whether an error that has occurred is a hard error or a soft error. Since it is necessary to have a means to notify the error address from the BS to the microprogram and a means to instruct the B5Ir1@ unit to disconnect the faulty block, this increases the amount of hardware and complicates the control, resulting in an increase in the interface between the BS and the microprogram. The problem was that it became complicated.

On the other hand, the hardware-based BS error processing method can simplify the interface between the BS and the microprogram, but as mentioned above, it is difficult to easily determine whether a BS error is caused by a soft error or a hard error. The problem was that it couldn't be done.

Means for solving the E0 problem The means taken by the present invention to solve the above problem are as follows.
This will be explained using figures. FIG. 1 is a block diagram showing the configuration of the present invention.

In FIG. 1, 110 is a buffer storage (BS)
The device is equipped with a BS array 111 and a tag (TAG) 112 that constitute the BS, as well as other peripheral parts (not shown) necessary for writing to and reading from the BS, as in conventional BS devices. It is being The BS array 111 stores data in storage units. Also, T.A.
The GII2 is provided with a control bifurcation l-(V) that instructs whether data in a storage unit is valid or invalid. The storage unit is usually a block.

Reference numeral 120 denotes an error detection circuit that detects the presence or absence of an error in data read from the BS array 111.

130 is an error control bit memory (ECBM); B
The BS array 111 is provided separately from the S array 111.
The first state in which there is no error in the data of each block, the second state in which an error occurs, and the third state in which the storage unit is separated.
The error control bit that indicates which state is in
It is provided corresponding to each storage unit.

140 is an error control circuit, and when an error is detected in the storage unit data of the BS array 111, the ECBMI 30
The error control bit of the storage unit in the first state (for example, "00") to the second state! @ (for example “01”
) and invalidates the storage unit. Furthermore, if an error is detected in the data read from the storage unit after the move-in due to another access is completed after the error control bit becomes the second state (01),
The corresponding error control bit in ECBMI 30 is changed from the second state (01) to the third state (e.g. “11”).
At the same time, the storage unit is invalidated and separated.

If no error is detected in the read data after the move-in, the error control bit is set to the second state (01).
The state is returned to the first state (00) where there is no error.

150 is a replacement determining means, which is an error control circuit 140;
When the storage unit that has been invalidated is subsequently accessed and there is no hit, data in the main memory (MSU) is moved into the invalidated storage unit.
In).

F9 action: Initially, the fetch request causes the BS array 111 to be sent from the MSU to the BS array 111.
Data is written to each storage unit, the address of each storage unit is written to the TAG 112, and the control pin l-V is set to valid "1".

Further, the ECBMI 30 is set to the first state (00) in which there is no error in the data by the initialization operation.

Data read from the BS array 111 accessed by the read request address from the CPU to the BS is transferred to the CPU and also applied to the error detection circuit 120.

When an error is detected in the data, the error detection circuit 120 notifies the error control circuit 140 of the occurrence of the error.

When the error control circuit 140 receives the error occurrence notification,
The TAG 112 updates the error control bit in the storage unit of the ECBMI 30 from the first state (00) to the second state (01) indicating the occurrence of an error, and invalidates the storage unit. Control of the entry for the storage unit and invalidates the bit v to "0".

Thereafter, another access to the invalidated storage unit or a retry by the CPU microprogram is performed by B.
When S is not hit (non Hit), n
The on Hit signal is sent to the replacement determining means 150.

When the replacement determining means 150 receives this non-Bit signal, it determines the replacement way (WAY), that is, the storage unit to be replaced. However, since the storage unit in which the error was detected earlier has been invalidated (the corresponding one in the TAG 112 If the control bit (2) of the entry is "0"), this storage unit will be replaced.

When the replacement process is completed, the data of the MSU is moved into the replaced storage unit according to instructions from the replacement determining means 150.

At this time, a new address is written to the TAG112 and the control bit ■ is set to valid "1".
The error control bit of ECBMI 30 is in the second state (0
1) remains the same.

Thereafter, when another access reads the data of this storage unit for the first time, the error detection circuit 120 detects the presence or absence of an error in this data.

If an error is detected again in the read data,
The error control circuit 140 determines that it is a hard error in the BS because the error was detected twice in a row with the move-in writing in between from the same storage unit, and the ECB
The error control bit corresponding to the storage unit in the MI 30 is updated from the second state (01) to the third state (11), and the storage unit is invalidated and separated. The separated storage unit will no longer be a target for address comparison or replacement to detect the old one.

If no error is detected in the read after the move-in, the error control circuit 140 determines that the first error is a soft error.
Assuming an error (intermittent error), the corresponding error control bit of the ECBMI 30 is returned from the second state fl (01) to the first state (00).

By simply adding the small-capacity ECBMI 30 and the error control circuit 140, which requires a simple circuit configuration, as described above (
The replacement determining means 150 is also used in a normal BS processing method) and can perform BS error processing.

In addition, a dedicated write cycle is not provided to write data after an error occurs, and data is moved in from the MSU to the BS array 111 when the BS is non-hit. Processing control is simplified.

Intermittent errors occurring in the RAM constituting the BS array 111 can be recovered by writing normal data.

The present invention focuses on this property, and if no error is detected after data is written after an error occurs, it is regarded as an intermittent error and storage processing is not separated. This prevents unnecessary disconnection processing and simplifies BS error handling.

G. Embodiment An embodiment of the present invention will be described with reference to FIGS. 2 and 3. FIG. 2 is a block diagram illustrating the configuration of the present invention, and FIG. 3 is a diagram illustrating a TAG entry and an error control bit memory provided therein.

G+, explanation of the configuration In FIG. 2, error detection circuits 120, 208M13
0, error control circuit 140 and replacement determining means 15
The part other than 0 is the BS device 110.

In the BS device 110, the BS array 111 is a 2WAY
It has a configuration (111A, 111B), and data is written or read in a storage unit consisting of a block, and is accessed by a lower address among addresses. TAG112 also has a 2WAY configuration (112A, 112B
), and is accessed by lower-order addresses. As shown in FIG. 3, the TAG entry corresponding to each block in the BS array 111 is provided with the upper address of the corresponding block and a control bit v indicating whether the block is valid or invalid, as well as a control bit v that will be explained later. The error control bit (ECo
, ECI) are provided. The BS array 111 and TAG 112 constitute a BS.

113 is an address register (ADH) in which an address for accessing the BS is set. The address is sent to the MSU to read the data at that address, the lower address is added to the BS array 111, TAG 112 and LRU memory (described later), and the upper address is added to the comparator 114.
added to.

There are two comparators 114 (114A,
114B) is provided, and the upper address of ADR113 and 2
Compare each upper address in the TAG entry of WAY.

Reference numeral 115 is a gate, and when a match of upper addresses is not detected in both comparators 114A and 114B, n
An on Hit signal is output and sent to the CPU and replacement determination circuit 150.

116 is a main memory data register (MSDR);
The data of U is set. Reference numeral 117 denotes a buffer storage data register (BSDR) in which data read from the BS array 111 is set. 11
8 is a BS array selector (BS-3EL) which receives the output of the comparator 114, selects the data of BS array IIA when TAG112A is hit, and selects the data of TAG1
When 12B is hit, data in BS array 111B is selected and written to BSDR 117. 119 is a control bit selector (V-3EL) which receives the output of comparator 114A, and when TAG112A is hit, TAG1
12A is selected, and when TA0112B is hit, the control bit V of TAG112B is selected and added to the replacement determination circuit 150.

The error detection circuit 120 performs a parity check to detect B.
The presence or absence of an error in the data read from the S array 111 is detected.

The ECBMI 30 is provided in the TAG 112 and the TAG
2WAY configuration (130A) similar to 112.

130B), and as shown in Figure 3, each TAG
Two error control bits ECo and EC1 are provided in which error information of data in the corresponding block of BS array 111 is set in the entry. In the first state where there is no error in the data, the error control bits E Co and ECI are set to 00", in the second state where an error occurs they are set to 01", and in the third state where the block is detached, they are set to "00". 11”. 131 is an error control bit selector (ECB-5EL) which receives the output of the comparator 114, selects ECBMI 30A when TAG112A is hit, and selects TA0112B.
When the signal is hit, the ECBM 130B is selected and sent to the error control circuit 140.

The error control circuit 140 is as described in FIG.

In the replacement determining means 150, 151 is L RU
The (Least Recently Used) table records the past usage status of each block of the BS array 111. 152 is the LRU register (LRU
R), i D of the block of the BS array 111 to be replaced taken out from the LRU table 151
(Either WA Yo or WA Y l) is written. Reference numeral 153 denotes a replacement determination circuit which, when receiving a non-hit signal from the gate 115, selects the LRU table 15.
A block to be replaced is determined by a well-known LRU method using 1. At this time, control is performed so that a block that has been invalidated due to a data error occurring first is replaced. In other words, rather than depending on the value from LRU, TA
The block with control bits vo of G is preferentially replaced.

G2. Description of operation: First, a fetch request is sent from the MSU to the BS array 111.
Data is written to each block, the upper address of each block is written to TAG112, and the control bit V
is set to valid "1". Further, the error control bits ECO and EC1 of the ECBMI 30 are set to the first state "00" with no error by the initialization operation.

The read request address from the CPU to the BS is ADR11.
3, and TAG112, B is set to the lower address.
S array 111 and LRU table 151 are accessed simultaneously. When a lower address is provided to TAG 112, the upper address within that TAG is read and applied to comparator 114.

Comparator 114 compares the upper addresses of ADR 113 and TAG 112. The block data in the BS array 111 corresponding to the TAG 112 with the matching upper address is set in the BSDR II 8 and applied to the CPU and error detection circuit 120.

The error detection circuit 120 performs error detection by parity checking, and when an error is detected in the data, it notifies the error control circuit 140 and the microprogram of the CPU.

When the error control circuit 140 receives the error occurrence notification,
Error control bins of that block in the ECBMI 30) Update ECO and EC1 from the first state (00) to the second state (01) indicating the occurrence of an error;
The control bit V of the block is set to 10' to invalidate the block.

After that, when another access with the same lower address as the error access or a retry by the CPU microprogram does not hit the BS because the upper address does not match, the comparator 114 and gate 115 select
The Hit signal is sent to the replacement determination circuit 153. On the other hand, control bit selector 119 sends a control bit "O" indicating that the block at the lower address is invalidated.

The replacement determination circuit 153 determines a block to be replaced by a known LRU method using the LRU table 151, but at this time, blocks that were invalidated due to an error occurring in data are replaced first, giving priority to the LRU method. control so that it is done.

On the other hand, the address that accessed the BS is sent from the ADR 113 to the MSU. After a certain period of time, the data sent from the MSU is set in the MSDR 116 and then written into the block of the BS array (111A or 11B) specified by the replacement determination circuit 153.

At this time, TAG (1
12A or 112B), a new upper address is written to the entry, and the control bit V of that entry is written.
is set to valid "1". However, the error control bits ECo and EC! in that entry remains in the second state (01).

Thereafter, when another access first reads the data of this replaced block, the error detection circuit 120 detects the presence or absence of an error in this data by parity checking.

If an error is detected again in the read data,
The error control circuit 140 determines this error to be a hard error in the BS, and changes the error control bits ECo and EC1 in the TAG entry corresponding to the block in the TAG 112 from the second state (01) to the third state ( 11) and disable control bit B to “0”.
” and detach the block. The detached block will no longer be subject to address comparison or replacement to detect the old one.

If no error is detected, the error control circuit 140 determines that the first error is an intermittent error that occurred in the RAM constituting the BS array 111, and that the information in the RAM has been successfully recovered by the move-in. The error control bits ECo and EC1 in the TAG entry are returned from the second state (01) to the first state (00) indicating no error. Since the control bit v is set to valid "1", the TAG entry indicates that the corresponding block of the BS array 111 has valid data without errors.

Although one embodiment of the present invention has been described above, each structure of the present invention is not limited to the structure of this embodiment.

For example, error control bit memory (ECBM)13
Of course, 0 may be provided separately without being shared with the TAG 112.

In addition, if the storage unit for normal reading is different from the block in the BS array 111, identification information ID is provided in the TAG 112 that indicates the error location within the block, and if an error occurs when rereading the same location, If there is no error when disconnecting and re-reading the same location, control is restored to the first state with no error, so even if a hard error occurs, only the error location is removed without needlessly disconnecting the normal section. It can be made to separate.

Effect of H0 invention The present invention has the following effects.

(b) Buffer storage error processing can be performed by distinguishing between intermittent errors and fixed errors by simply adding a small-capacity error control bit memory and a simple error control circuit, so a small amount of hardware is required. By adding , it is possible to implement buffer storage and error handling in hardware.

(b) After an error occurs, there is no dedicated write cycle for writing data for error processing, and data is moved in from the main memory to the buffer storage array when the buffer storage is non-hit. Since this is done by using the BS error processing control, it is possible to simplify the BS error processing control.

[Brief explanation of drawings]

FIG. 1: A block explanatory diagram of the configuration of the present invention; FIG. 2: A block explanatory diagram of an embodiment of the present invention; FIG. 3: Tag (TAG) entry and error control bit memory in the embodiment. Explanatory diagram. In FIG. 1, 110-buffer storage (BS) device, 111-
Buffer storage (BS) array, 112-tag (TAG), 120-error detection circuit, 130-error control bit memory (ECBM), 1
40-Error control circuit; 150-Replacement determining means.

Claims (3)

[Claims] (1) In the buffer storage error handling method in which error processing is performed by hardware when an error occurs in the buffer storage where writing is performed using the store-through method, (a) the buffer storage array (111) and is provided separately and includes a buffer storage array (111
), each storage unit has an error control bit that indicates whether it is in a first state with no errors, a second state with an error, or a third state in which the storage unit is disconnected. Error control bits and
(b) When an error is detected in the data in the storage unit of the buffer storage array (111), the error control bit of the storage unit in the error control bit memory (130) is set to the first an error control circuit (1) that updates the storage unit from a state to a second state, invalidates the storage unit, detects the presence or absence of an error in data read from the storage unit after move-in by another access, and performs error processing;
40), and (c) a replacement determining means (15) for moving data in the main memory into the invalidated storage unit when the invalidated storage unit is accessed and does not result in a hit.
0), a buffer storage error handling method comprising: (2) If the error processing in the error control circuit (140) detects an error again in the data read from the storage unit, the error control bit memory (140)
30) The buffer according to claim 1 is a process of updating the corresponding error control bit from the second state to the third state and invalidating and separating the storage unit. -Storage error handling method. (3) If the error processing in the error control circuit (140) detects no error in the data read from the storage unit, the error control bit memory (
130) The buffer storage error handling method according to claim 1, characterized in that the process returns the corresponding error control bit in step 130) from the second state to the first state.